CN109002265B - Data processing method and related device - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
Abstract
The embodiment of the invention discloses a data processing method, which comprises the following steps: when the target data is failed to be written into the first storage area, the main control chip writes the target data into the second storage area; the main control chip reads the target context information from the second storage area; the main control chip carries out data splitting processing on the target context information to obtain a plurality of first subcontext information; the main control chip sends the plurality of first subcontext information to the first storage area, so that the first storage area stores the plurality of first subcontext information. The embodiment of the invention also discloses a data processing device. The embodiment of the invention provides a method, which can process data when a write error occurs, so that the data can be successfully stored in a flash memory chip, and the integrity of user stored data is ensured.
Description
Technical Field
The present invention relates to the field of data processing technologies, and in particular, to a data processing method and a related apparatus.
Background
With the development and wide application of technologies such as internet, cloud computing, internet of things, big data and the like, massive data needs to be processed and stored at every moment, and therefore higher requirements are put forward on the performance of a storage system. Solid State Drives (SSD) are widely used because of their high read/write speed and low power consumption.
The important component in the SSD is Nand-type (Nand Flash) particles, which have characteristics of large capacity, fast writing, etc., but have disadvantages of unstable storage performance and relatively short lifetime, and in the read/write operation of the SSD, the read/write error caused by the Nand Flash particles is difficult to avoid. Once a write error occurs, data is lost without corresponding processing, thereby causing irreparable loss to the user.
Disclosure of Invention
The embodiment of the invention provides a data processing method and a related device, which realize the rewriting operation of wrongly written data when a writing error occurs, and reduce the probability of data loss.
In view of the above, a first aspect of the present invention provides a data processing method, including:
when the target data is failed to be written into the first storage area, the main control chip writes the target data into the second storage area;
the main control chip reads target context information from the second storage area, wherein the target context information comprises the target data and address information of the target data;
the main control chip performs data splitting processing on the target context information to obtain a plurality of first sub-context information, wherein each first sub-context information comprises first sub-data and address information corresponding to the first sub-data;
the main control chip sends the plurality of pieces of first subcontext information to the first storage area, so that the first storage area stores the plurality of pieces of first subcontext information.
With reference to the first aspect of the embodiment of the present invention, in a first possible implementation manner of the first aspect, the address information corresponding to the first sub-data includes a logical address corresponding to the first sub-data;
the method further comprises the following steps:
the main control chip writes the logic address corresponding to the target data into the second storage area;
the main control chip performs data splitting processing on the target context information to obtain a plurality of first subcontext information, including:
and the main control chip carries out data splitting processing on the logic address corresponding to the target data to obtain a plurality of logic addresses corresponding to the first subdata.
With reference to the first aspect of the embodiment of the present invention, in a second possible implementation manner of the first aspect, the address information of the target data includes: a first physical address and a second physical address, wherein the first physical address is a physical address corresponding to the target data stored in the second storage area, and the second physical address is a physical address corresponding to a write failure occurring in the first storage area;
the address information corresponding to the first subdata comprises a first physical address corresponding to the first subdata;
the method further comprises the following steps:
the main control chip writes a first physical address corresponding to the target data into the second storage area;
the main control chip performs data splitting processing on the target context information to obtain a plurality of first subcontext information, including:
and the main control chip carries out data splitting processing on the first physical address corresponding to the target data to obtain a plurality of first physical addresses corresponding to the first subdata.
With reference to the second possible implementation manner of the first aspect of the embodiment of the present invention, in a third possible implementation manner of the first aspect of the embodiment of the present invention, the causing the first storage area to store the plurality of first subcontext information includes:
the main control chip sends a write-in request to the first storage area in a target period so that the first storage area stores the first subcontext information;
or the like, or, alternatively,
and the main control chip sends a plurality of write requests to the first storage area in the target period so that the first storage area stores a plurality of pieces of first subcontext information.
With reference to any one implementation manner of the first aspect of the present invention to the third possible implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect of the present invention, after the main control chip sends the plurality of first sub-context information to the first storage area, so that the first storage area stores the plurality of first sub-context information, the method further includes:
1) the main control chip judges whether first subcontext information is successfully stored in the first storage area, wherein the first subcontext information is any one of the plurality of first subcontext information;
2) if the first subcontext information is successfully stored in the first storage area, the main control chip deletes the first subcontext information stored in the second storage area;
and repeatedly executing the step 1) and the step 2) until the main control chip deletes the plurality of pieces of first subcontext information from the first storage area.
A second aspect of the present invention provides a data processing apparatus, the data reading apparatus comprising:
the write-in module is used for writing the target data into a second storage area by the main control chip when the target data fails to be written into the first storage area;
a reading module, configured to read, by the master control chip, target context information from the second storage area, where the target context information includes the target data and address information of the target data;
the error processing module is used for the main control chip to perform data splitting processing on the target context information to obtain a plurality of pieces of first sub-context information, wherein each piece of first sub-context information comprises first sub-data and address information corresponding to the first sub-data;
a sending module, configured to send, by the master control chip, the plurality of pieces of first subcontext information to the first storage area, so that the first storage area stores the plurality of pieces of first subcontext information.
In combination with the second aspect of the embodiments of the present invention, in a first possible embodiment of the second aspect, there is provided a data processing apparatus, including:
the writing module is further used for writing the logic address corresponding to the target data into the second storage area by the main control chip;
the error processing module is further configured to perform data splitting processing on the target context information by the main control chip to obtain a plurality of first subcontext information, and includes:
and the main control chip carries out data splitting processing on the logic address corresponding to the target data to obtain a plurality of logic addresses corresponding to the first subdata.
In combination with the second possible embodiment of the second aspect of the present invention, in a second possible embodiment of the second aspect, there is provided a data processing apparatus including:
the address information of the target data includes: a first physical address and a second physical address, wherein the first physical address is a physical address corresponding to the target data stored in the second storage area, and the second physical address is a physical address corresponding to a write failure occurring in the first storage area;
the address information corresponding to the first subdata comprises a first physical address corresponding to the first subdata;
the writing module is further used for writing the first physical address corresponding to the target data into the second storage area by the main control chip;
an error processing module, configured to perform data splitting processing on the target context information by the master control chip to obtain multiple pieces of first subcontext information, where the error processing module includes:
and the error processing module is specifically configured to perform data splitting processing on the first physical address corresponding to the target data by the main control chip to obtain a first physical address corresponding to the plurality of first subdata.
In combination with the second possible embodiment of the second aspect of the embodiments of the present invention, in a third possible embodiment of the second aspect, there is provided a data processing apparatus, including:
a sending module, configured to send a write request to the first storage area in a target period, so that the first storage area stores one piece of the first subcontext information;
or the like, or, alternatively,
the sending module is further configured to send a plurality of write requests to the first storage area in the target period, so that the first storage area stores a plurality of pieces of the first subcontext information.
With reference to any one implementation manner of the second aspect to the third possible implementation manner of the second aspect of the embodiment of the present invention, the data processing apparatus in the fourth possible implementation manner of the second aspect of the embodiment of the present invention includes:
an error processing module further configured to:
1) the main control chip judges whether first subcontext information is successfully stored in the first storage area, wherein the first subcontext information is any one of the plurality of first subcontext information;
2) if the first subcontext information is successfully stored in the first storage area, the main control chip deletes the first subcontext information stored in the second storage area;
and repeatedly executing the step 1) and the step 2) until the main control chip deletes the plurality of pieces of first subcontext information from the first storage area.
According to the technical scheme, the embodiment of the invention has the following advantages:
the embodiment of the invention provides a data processing method, which is characterized in that a firmware running on an SSD main control chip can process data when a write error occurs, so that the data can be successfully stored in a flash memory chip, and the integrity of the data stored by a user is ensured.
Drawings
FIG. 1 is a schematic diagram of an SSD for a method of data processing according to an embodiment of the present invention;
FIG. 2 is a diagram of an embodiment of a method for data processing according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an embodiment of a data processing apparatus according to the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The embodiment of the invention provides a data processing method and a related device, which realize the rewriting operation of wrongly written data when a writing error occurs, and reduce the probability of data loss.
It should be understood that the present invention is mainly applied to data processing of a Solid State Drive (SSD), wherein a Flash memory type of the SSD is a Nand Flash, for easy understanding, please refer to fig. 1, fig. 1 is a schematic diagram of the SSD of the data processing method in the embodiment of the present invention, and the embodiment of the present invention is the data processing method applied to the SSD, and the following description is made in conjunction with fig. 1.
As shown in fig. 1, the SSD may be divided into three parts, which are a main control chip, a nand-type flash memory, and a cache chip, where the main control chip is used to run an operation instruction including firmware of the SSD, and an interface connected to a host (host) exists on the main control chip; nand flash memory, which includes two parts: the Logical Unit Number (LUN) is configured to process a command issued by the main control chip, and read, write, or erase target data on the flash memory chip according to the command, where a plurality of LUNs, typically 4 or 8 LUNs, exist on one flash memory chip, and the LUNs may process the command in parallel, which is not limited herein. The flash memory chip is used for storing target data, wherein the flash memory chip is a Nand-type flash memory, and the Nand-type flash memory can be further divided into single-level cells (SLC), multi-level cells (MLC), and triple-level cells (TLC) according to a difference in density of electronic units, where the type of the Nand-type flash memory is not limited, and the SSD generally includes an array of 8, 16, or 32 Nand-type flash memory chips. The cache chip is used for storing data temporarily required by an operating instruction running on the main control chip, and the type of the cache chip is mainly a Dynamic Random Access Memory (DRAM) or a Static Random Access Memory (SRAM), which is not limited here. In the Nand Flash type Flash memory, data storage is realized by changing 0/1 of cells (cells), when in write operation, 0 or 1 of the corresponding Cell is modified, the Cell is a minimum operation erasing and writing unit and corresponds to a floating gate transistor and can store 1bit or more data, in the Nand Flash type chip, the minimum writing unit is a page (page), the general size is 4 Kilobytes (KB) or 512 bytes (B), the minimum erasing unit is a block (block), the block corresponding to the hardware end of the SSD is called a physical block (physical block), the SSD writing data is written in a super page mode, and one super page is distributed on different physical blocks.
As shown in fig. 1, a Flash Translation Layer (FTL) in a main control chip on an SSD receives a write command from a host to write target data into the flash memory chip, and when a write failure occurs, the main control chip writes the target data into a cache chip, and writes a logical address corresponding to the target data at the host. And then, the main control chip reads target context information containing target data from the cache chip, and the target context information also contains address information corresponding to the target data, wherein the address information contains a first physical address and a second physical address, the first physical address is a physical address corresponding to the target data stored in the cache chip, and the second physical address is a physical address corresponding to the write failure in the flash memory chip. Then, the main control chip performs a data splitting operation on the target context information to obtain a plurality of first sub-context information, where each first sub-context information includes first sub-data and address information corresponding to the first sub-data, the address information corresponding to the first sub-data includes a first physical address corresponding to the first sub-data, and when performing the data splitting operation on a physical address, the physical address may be intercepted according to a certain data size interval, and the intercepted physical address is a physical address corresponding to the sub-data, and generally, the data size interval is 4KB or 512B, which is not limited herein. The address information also comprises a logic address corresponding to the split target subdata, and the process of the main control chip obtaining the logic address corresponding to the target subdata comprises the step of searching the logic address corresponding to the target subdata according to a preset offset after the first physical address corresponding to the target subdata. After the main control chip performs data splitting operation on the target context information to obtain a plurality of first subcontext information, the FTL on the main control chip sends a write-in request to the flash memory chip according to the first subcontext information, the sending of the write-in request includes sending a write-in request, one write-in request includes one piece of first subcontext information and is used for writing one piece of subdata corresponding to the first subcontext information in the flash memory chip, and a plurality of write-in requests can also be sent, the plurality of write-in requests include a plurality of pieces of first subcontext information and are used for writing in the subdata corresponding to the plurality of pieces of first subcontext information in the flash memory chip. After the main control chip judges that the first subcontext information is successfully stored in the flash memory chip, the main control chip can release the space of the cache chip by deleting the corresponding first subcontext information stored in the cache chip so as to store new context information, and simultaneously avoid data errors and resource waste caused by repeated processing of the same subcontext for many times.
Referring to fig. 2, in the following, a method for data processing in the present invention is explained, and in the embodiment of the present invention, a schematic diagram of an embodiment of the method for data processing includes:
101. the main control chip writes the target data into a second storage area;
in this embodiment, the firmware running on the SSD main control chip receives a write instruction from the host to write the target data into the flash memory chip, and the flash memory chip is named as a first storage area, and when the target data fails to be written into the first storage area, the main control chip writes the target data into the cache chip, and the cache chip is named as a second storage area.
102. The main control chip reads the target context information from the second storage area;
in this embodiment, the firmware running on the SSD main control chip reads the target context information from the second storage area, where the target context information includes the target data and the address information corresponding to the target data.
103. The main control chip carries out data splitting processing on the target context information;
in this embodiment, the firmware running on the SSD main control chip performs data splitting on the read target context information, and obtains a plurality of first sub-context information after the data splitting, where the first sub-context information includes first sub-data and address information corresponding to the first sub-data.
The target data is split according to the data size of 4KB or 512B, the obtained subdata is named as first subdata, and the subcontext information containing the first subdata is named as first subcontext information.
104. The main control chip sends a plurality of pieces of first subcontext information to the first storage area.
In this embodiment, the firmware running on the SSD main control chip sends a write request to the FTL running on the SSD main control chip, and after the FTL processes the received write request, the main control chip sends a plurality of first sub-context information to the first storage area, so that the first storage area stores the plurality of first sub-context information.
The FTL avoids the storable blocks in the first storage area according to a preset bad Block table, data writing operation is carried out, the bad Block table is preset in the SSD by an SSD manufacturer and is called by a main control chip, the existence mode of the bad Block table is generally marked on the first page or the last page of the blocks, when a reading error or a writing error occurs in the using process, the bad Block table can be updated, the updating mode can be that the first page or the last page of the Block with the error occurs is marked, an array can also be formulated, bits (bits) corresponding to the blocks one by one exist in the array, when the error occurs, the corresponding bits are modified, if the bits are 0 in normal condition, the bits are modified into 1 in error, and the existence mode and the marking mode of the bad Block table are not limited.
The embodiment of the invention provides a data processing method, which comprises the steps that firstly, a firmware running on an SSD (solid State disk) main control chip receives a write-in instruction of a host end to write target data into a flash memory chip, the flash memory chip is named as a first storage area, when the target data are failed to be written into the first storage area, the main control chip writes the target data into a cache chip, and the cache chip is named as a second storage area. Secondly, the firmware running on the SSD master control chip reads the target context information from the second storage area, wherein the target context information comprises target data and address information corresponding to the target data. And thirdly, the firmware running on the SSD main control chip carries out data splitting processing on the read target context information, and a plurality of pieces of first sub-context information are obtained after splitting, wherein the first sub-context information comprises first sub-data and address information corresponding to the first sub-data. And thirdly, the firmware running on the SSD master control chip sends a write request to the FTL running on the SSD master control chip, and after the FTL processes the received write request, the master control chip sends a plurality of pieces of first subcontext information to the first storage area, so that the first storage area stores the plurality of pieces of first subcontext information. Through the mode, the rewriting operation of the wrongly written data is realized when the writing error occurs, and the probability of data loss is reduced.
Optionally, on the basis of the embodiment corresponding to fig. 2, in an embodiment of the second data processing method provided in the embodiment of the present invention, the address information corresponding to the first sub-data includes a logical address corresponding to the first sub-data; further comprising:
the main control chip writes the logic address corresponding to the target data into a second storage area;
the main control chip performs data splitting processing on the target context information to obtain a plurality of first subcontext information, and the method comprises the following steps:
the main control chip carries out data splitting processing on the logic address corresponding to the target data to obtain the logic addresses corresponding to the plurality of first subdata.
In this embodiment, in the process that the main control chip writes the target data into the second storage area, writing a logical address corresponding to the target data into the second storage area, performing data splitting processing on the target context information by the main control chip, and performing data splitting processing on the logical address corresponding to the target data, where the obtained plurality of first sub data includes the logical address corresponding to the first sub data.
In the embodiment of the invention, when the target data is failed to be written into the first storage area, the main control chip writes the target data into the second storage area, the writing process further comprises the step of writing a logic address corresponding to the target data into the second storage area, the main control chip reads generated target context information from the second storage area, wherein the target context information comprises the target data and the logic address corresponding to the target data, when the main control chip splits the target context information, the logic address corresponding to the target data is also split besides the split target data, and the logic address corresponding to the target sub-data is obtained. So as to facilitate the expansion of the subsequent steps and improve the feasibility of the scheme.
Optionally, on the basis of the embodiment corresponding to fig. 2, in a third embodiment of the data processing method provided in the embodiment of the present invention, the address information of the target data includes: the first physical address is a physical address corresponding to the target data stored in the second storage area, and the second physical address is a physical address corresponding to the write failure in the first storage area;
the address information corresponding to the first subdata comprises a first physical address corresponding to the first subdata;
further comprising:
the main control chip writes a first physical address corresponding to the target data into a second storage area;
the main control chip performs data splitting processing on the target context information to obtain a plurality of first subcontext information, and the method comprises the following steps:
the main control chip performs data splitting processing on a first physical address corresponding to the target data to obtain a plurality of first physical addresses corresponding to the first subdata.
In this embodiment, when the main control chip writes the target data into the second storage area, a physical address corresponding to a write failure occurring when the target data is written into the first storage area is also written, and is used for updating the bad block table stored in the SSD, where the physical address is named as a second physical address, and in the read and generated target context information, the physical address corresponding to the target data currently stored in the second storage area is included, and the physical address is named as a first physical address. When the main control chip splits the target context information, the split target context information also has a first physical address, and the first physical addresses corresponding to the plurality of first subdata are obtained.
In the embodiment of the present invention, the address information included in the target context information further includes a first physical address and a second physical address in addition to the logical address corresponding to the target data, the second physical address is used to instruct the main control chip to update the bad block table, and the first physical address is used to split and obtain the physical address corresponding to the sub-data, so that the subsequent steps are expanded, and the feasibility of the scheme is improved.
Optionally, on the basis of the embodiment corresponding to fig. 2, in a fourth embodiment of the data processing method provided in the embodiment of the present invention, the sending, by the main control chip, the multiple pieces of first subcontext information to the first storage area, so that the first storage area stores the multiple pieces of first subcontext information includes:
the main control chip sends a write-in request to the first storage area in a target period so that the first storage area stores a first piece of subcontext information;
or the like, or, alternatively,
the main control chip sends a plurality of write requests to the first storage area in a target period so that the first storage area stores a plurality of first subcontext information.
In this embodiment, after the master control chip splits and generates the plurality of first subcontext information, the master control chip sends the plurality of first subcontext information to the first storage area, and the sending process includes: the main control chip sends a write-in request to the first storage area, wherein when one write-in request is sent, the main control chip writes one piece of first subcontext information into the first storage area, and when a plurality of write-in requests are sent, the main control chip writes a plurality of pieces of first subcontext information into the first storage area.
Since the FTL on the main control chip has the capability of processing multiple write requests simultaneously, sending multiple write requests may be sent sequentially according to a preset time interval, or may be sent simultaneously, which is not limited herein.
In the embodiment of the present invention, the method for sending a plurality of pieces of first subcontext information to a first storage area by a main control chip includes sending a write request for writing a piece of first subcontext information. The method further comprises sending a plurality of write requests for writing a plurality of first subcontext information. The realization flexibility of the scheme is improved.
Optionally, on the basis of the embodiment corresponding to fig. 2, in a fifth embodiment of the data processing method provided in the embodiment of the present invention, after the main control chip sends the plurality of pieces of first sub-context information to the first storage area, so that the first storage area stores the plurality of pieces of first sub-context information, the method further includes:
1) the main control chip judges whether the first subcontext information is successfully stored in the first storage area, wherein the first subcontext information is any one of a plurality of first subcontext information;
2) if the first subcontext information is successfully stored in the first storage area, the main control chip deletes the first subcontext information stored in the second storage area;
and repeatedly executing the step 1) and the step 2) until the main control chip deletes the plurality of first subcontext information from the first storage area.
In this embodiment, after the main control chip sends a plurality of pieces of first sub-context information to the first storage area, and the first storage area writes the received plurality of pieces of first sub-context information, the main control chip performs step 1) to determine whether the first sub-context information is successfully stored in the first storage area, where the first sub-context information is any one of the plurality of pieces of first sub-context information, and then performs step 2) to delete the first sub-context information stored in the second storage area if the first sub-context information is successfully stored in the first storage area. The main control chip repeatedly executes the step 1) and the step 2) until the main control chip deletes the plurality of first subcontext information from the second storage area.
In the embodiment of the invention, the main control chip judges whether the first subcontext information is successfully stored in the first storage area, if so, the first subcontext information stored in the second storage area is deleted until a plurality of first subcontext information are deleted. The feasibility of the scheme is improved.
Referring to fig. 3, fig. 3 is a schematic diagram of an embodiment of a data processing apparatus according to the present invention, and in a first embodiment of a data processing apparatus 20 according to the present invention, the data processing apparatus 20 includes:
the write-in module 201 is configured to, when writing of the target data into the first storage area fails, write the target data into the second storage area by the main control chip;
the reading module 202 is configured to read, by the main control chip, target context information from the second storage area, where the target context information includes target data and address information of the target data;
the error processing module 203 is configured to perform data splitting processing on the target context information by the main control chip to obtain a plurality of first sub-context information, where each first sub-context information includes first sub-data and address information corresponding to the first sub-data;
the sending module 204 is configured to send, by the main control chip, the plurality of pieces of first subcontext information to the first storage area, so that the first storage area stores the plurality of pieces of first subcontext information.
In this embodiment, the writing module 201 is configured to, when writing of the target data into the first storage area fails, write the target data into the second storage area by the main control chip; the reading module 202 is configured to read, by the main control chip, target context information from the second storage area, where the target context information includes target data and address information of the target data; the error processing module 203 is configured to perform data splitting processing on the target context information by the main control chip to obtain a plurality of first sub-context information, where each first sub-context information includes first sub-data and address information corresponding to the first sub-data; the sending module 204 is configured to send, by the main control chip, the plurality of pieces of first subcontext information to the first storage area, so that the first storage area stores the plurality of pieces of first subcontext information.
In an embodiment of the present invention, a data processing apparatus is provided, where a Flash Translation Layer (FTL) in a main control chip on an SSD receives a write instruction from a host to write target data into a flash memory chip, and when a write failure occurs, the main control chip writes the target data into a cache chip, and writes a logical address corresponding to the target data at the host. And then, the main control chip reads target context information containing target data from the cache chip, and the target context information also contains address information corresponding to the target data, wherein the address information contains a first physical address and a second physical address, the first physical address is a physical address corresponding to the target data stored in the cache chip, and the second physical address is a physical address corresponding to the write failure in the flash memory chip. Then, the main control chip performs a data splitting operation on the target context information to obtain a plurality of first sub-context information, where each first sub-context information includes first sub-data and address information corresponding to the first sub-data, the address information corresponding to the first sub-data includes a first physical address corresponding to the first sub-data, and when performing the data splitting operation on a physical address, the physical address may be intercepted according to a certain data size interval, and the intercepted physical address is a physical address corresponding to the sub-data, and generally, the data size interval is 4KB or 512B, which is not limited herein. The address information also comprises a logic address corresponding to the split target subdata, and the process of the main control chip obtaining the logic address corresponding to the target subdata comprises the step of searching the logic address corresponding to the target subdata according to a preset offset after the first physical address corresponding to the target subdata. After the main control chip performs data splitting operation on the target context information to obtain a plurality of first subcontext information, the FTL on the main control chip sends a write-in request to the flash memory chip according to the first subcontext information, the sending of the write-in request includes sending a write-in request, one write-in request includes one piece of first subcontext information and is used for writing one piece of subdata corresponding to the first subcontext information in the flash memory chip, and a plurality of write-in requests can also be sent, the plurality of write-in requests include a plurality of pieces of first subcontext information and are used for writing in the subdata corresponding to the plurality of pieces of first subcontext information in the flash memory chip. After the main control chip judges that the first subcontext information is successfully stored in the flash memory chip, the main control chip can release the space of the cache chip by deleting the corresponding first subcontext information stored in the cache chip so as to store new context information, and simultaneously avoid data errors and resource waste caused by repeated processing of the same subcontext for many times.
Alternatively, on the basis of the embodiment corresponding to fig. 3, in a second embodiment of the data processing apparatus 20 provided in the embodiment of the present invention,
the writing module 201 is further configured to write the logic address corresponding to the target data into the second storage area by the main control chip;
the error processing module 203 is further configured to perform data splitting processing on the target context information by the main control chip to obtain a plurality of first subcontext information, including:
the main control chip carries out data splitting processing on the logic address corresponding to the target data to obtain the logic addresses corresponding to the plurality of first subdata.
In the embodiment of the invention, when the target data is failed to be written into the first storage area, the main control chip writes the target data into the second storage area, the writing process further comprises the step of writing a logic address corresponding to the target data into the second storage area, the main control chip reads generated target context information from the second storage area, wherein the target context information comprises the target data and the logic address corresponding to the target data, when the main control chip splits the target context information, the logic address corresponding to the target data is also split besides the split target data, and the logic address corresponding to the target sub-data is obtained. So as to facilitate the expansion of the subsequent steps and improve the feasibility of the scheme.
Optionally, on the basis of the embodiment corresponding to fig. 3, in a third embodiment of the data processing apparatus 20 provided in the embodiment of the present invention, the address information of the target data includes: the first physical address is a physical address corresponding to the target data stored in the second storage area, and the second physical address is a physical address corresponding to the write failure in the first storage area;
the address information corresponding to the first subdata comprises a first physical address corresponding to the first subdata;
the writing module 201 is further configured to write the first physical address corresponding to the target data into the second storage area by the main control chip;
the error processing module 203 is configured to perform data splitting processing on the target context information by the main control chip to obtain multiple pieces of first subcontext information, and includes:
the error processing module 203 is specifically configured to perform data splitting processing on the first physical address corresponding to the target data by the main control chip to obtain a first physical address corresponding to the plurality of first subdata.
In the embodiment of the present invention, the address information included in the target context information further includes a first physical address and a second physical address in addition to the logical address corresponding to the target data, the second physical address is used to instruct the main control chip to update the bad block table, and the first physical address is used to split and obtain the physical address corresponding to the sub-data, so that the subsequent steps are expanded, and the feasibility of the scheme is improved.
Alternatively, on the basis of the embodiment corresponding to fig. 3, in a fourth embodiment of the data processing apparatus 20 provided in the embodiment of the present invention,
a sending module 204, further configured to send a write request to the first storage area in a target period, so that the first storage area stores one piece of the first subcontext information;
or the like, or, alternatively,
the sending module 204 is further configured to send a plurality of write requests to the first storage area in the target period, so that the first storage area stores a plurality of pieces of the first subcontext information.
In the embodiment of the present invention, the method for sending a plurality of pieces of first subcontext information to a first storage area by a main control chip includes sending a write request for writing a piece of first subcontext information. The method further comprises sending a plurality of write requests for writing a plurality of first subcontext information. The realization flexibility of the scheme is improved.
Optionally, on the basis of the embodiment corresponding to fig. 3, in a fifth embodiment of the data processing apparatus 20 provided in the embodiment of the present invention, the error processing module 203 is further configured to:
1) the main control chip judges whether the first subcontext information is successfully stored in the first storage area, wherein the first subcontext information is any one of a plurality of first subcontext information;
2) if the first subcontext information is successfully stored in the first storage area, the main control chip deletes the first subcontext information stored in the second storage area;
and repeatedly executing the step 1) and the step 2) until the main control chip deletes the plurality of first subcontext information from the first storage area.
In the embodiment of the invention, the main control chip judges whether the first subcontext information is successfully stored in the first storage area, if so, the first subcontext information stored in the second storage area is deleted until a plurality of first subcontext information are deleted. The feasibility of the scheme is improved.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (8)
1. A method of data processing, comprising:
when the target data is failed to be written into the first storage area, the main control chip writes the target data into the second storage area;
the main control chip writes the logic address corresponding to the target data into the second storage area;
the main control chip reads target context information from the second storage area, wherein the target context information comprises the target data and address information of the target data;
the main control chip carries out data splitting processing on the target context information to obtain a plurality of first sub-context information, the main control chip carries out data splitting processing on a logic address corresponding to the target data to obtain a plurality of logic addresses corresponding to the first sub-data,
each piece of first subcontext information comprises first subdata and address information corresponding to the first subdata;
the main control chip sends the plurality of pieces of first subcontext information to the first storage area, so that the first storage area stores the plurality of pieces of first subcontext information.
2. The method of claim 1, wherein the address information of the target data comprises: a first physical address and a second physical address, wherein the first physical address is a physical address corresponding to the target data stored in the second storage area, and the second physical address is a physical address corresponding to a write failure occurring in the first storage area;
the address information corresponding to the first subdata comprises a first physical address corresponding to the first subdata;
the method further comprises the following steps:
the main control chip writes a first physical address corresponding to the target data into the second storage area;
the main control chip performs data splitting processing on the target context information to obtain a plurality of first subcontext information, including:
and the main control chip carries out data splitting processing on the first physical address corresponding to the target data to obtain a plurality of first physical addresses corresponding to the first subdata.
3. The method of claim 2, wherein the sending, by the master chip, the plurality of first subcontext information to the first storage area, so that the first storage area stores the plurality of first subcontext information, comprises:
the main control chip sends a write-in request to the first storage area in a target period so that the first storage area stores the first subcontext information;
or the like, or, alternatively,
and the main control chip sends a plurality of write requests to the first storage area in the target period so that the first storage area stores a plurality of pieces of first subcontext information.
4. The method according to any one of claims 1 to 3, wherein after the master chip sends the plurality of first subcontext information to the first storage area, so that the first storage area stores the plurality of first subcontext information, the method further comprises:
1) the main control chip judges whether first subcontext information is successfully stored in the first storage area, wherein the first subcontext information is any one of the plurality of first subcontext information;
2) if the first subcontext information is successfully stored in the first storage area, the main control chip deletes the first subcontext information stored in the second storage area;
and repeatedly executing the step 1) and the step 2) until the main control chip deletes the plurality of pieces of first subcontext information from the first storage area.
5. A data processing apparatus, characterized in that,
the write-in module is used for writing the target data into a second storage area by the main control chip when the target data fails to be written into the first storage area;
the writing module is further configured to write the logical address corresponding to the target data into the second storage area;
a reading module, configured to read, by the master control chip, target context information from the second storage area, where the target context information includes the target data and address information of the target data;
the error processing module is used for the main control chip to perform data splitting processing on the target context information to obtain a plurality of pieces of first sub-context information, and the main control chip to perform data splitting processing on a logic address corresponding to the target data to obtain a plurality of logic addresses corresponding to first sub-data, wherein each piece of first sub-context information comprises first sub-data and address information corresponding to the first sub-data;
a sending module, configured to send, by the master control chip, the plurality of pieces of first subcontext information to the first storage area, so that the first storage area stores the plurality of pieces of first subcontext information.
6. The data processing apparatus of claim 5, wherein the address information of the target data comprises: a first physical address and a second physical address, wherein the first physical address is a physical address corresponding to the target data stored in the second storage area, and the second physical address is a physical address corresponding to a write failure occurring in the first storage area;
the address information corresponding to the first subdata comprises a first physical address corresponding to the first subdata;
the write-in module is further configured to write a first physical address corresponding to the target data into the second storage area by the main control chip;
the error processing module is configured to perform data splitting processing on the target context information by the main control chip to obtain a plurality of first subcontext information, and includes:
the error processing module is specifically configured to perform data splitting processing on the first physical address corresponding to the target data by the main control chip to obtain a first physical address corresponding to the plurality of first subdata.
7. The data processing apparatus of claim 6,
the sending module is further configured to send a write request to the first storage area in a target period, so that the first storage area stores one piece of the first subcontext information;
or the like, or, alternatively,
the sending module is further configured to send a plurality of write requests to the first storage area in the target period, so that the first storage area stores a plurality of pieces of the first subcontext information.
8. The data processing apparatus according to any one of claims 5 to 7,
the error processing module is further configured to:
1) the main control chip judges whether first subcontext information is successfully stored in the first storage area, wherein the first subcontext information is any one of the plurality of first subcontext information;
2) if the first subcontext information is successfully stored in the first storage area, the main control chip deletes the first subcontext information stored in the second storage area;
and repeatedly executing the step 1) and the step 2) until the main control chip deletes the plurality of pieces of first subcontext information from the first storage area.
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