CN109002265A - A kind of method and relevant apparatus of data processing - Google Patents
A kind of method and relevant apparatus of data processing Download PDFInfo
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- CN109002265A CN109002265A CN201810837094.6A CN201810837094A CN109002265A CN 109002265 A CN109002265 A CN 109002265A CN 201810837094 A CN201810837094 A CN 201810837094A CN 109002265 A CN109002265 A CN 109002265A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
Abstract
The embodiment of the invention discloses a kind of methods of data processing, comprising: when the failure of the first storage region is written in target data, target data is written to the second storage region main control chip；Main control chip reads target context information from the second storage region；Main control chip carries out data deconsolidation process to target context information, to obtain the multiple first sub- contextual informations；Main control chip sends multiple first sub- contextual informations to the first storage region, so that the first storage region stores multiple first sub- contextual informations.The embodiment of the invention also discloses a kind of data processing equipments.It provides a method, is realized when there is write error in the embodiment of the present invention, data can be handled, data are successfully stored into flash chip, guarantee the integrality of user storage data.
Description
Technical field
The present invention relates to technical field of data processing more particularly to the methods and relevant apparatus of a kind of data processing.
Background technique
With the development and extensive use of the technologies such as internet, cloud computing, Internet of Things and big data, all need all the time
Mass data is handled and stored, therefore, more stringent requirements are proposed to the performance of storage system.And solid state hard disk
(Solid State Drives, SSD) is widely used because it has the characteristics that read or write speed is fast and low energy consumption.
Important component part right and wrong type (Nand Flash) particle in SSD, Nand Flash particle have capacity
Greatly, the characteristics such as fast are written, but have the shortcomings that storage performance is unstable and the service life is relatively short, are grasped in the read-write of SSD
In work, the read-write error as caused by Nand Flash particle is difficult to avoid that.Once write error has occurred, it is corresponding not doing
Data can be lost in the case where processing, to bring irremediable loss to user.
Summary of the invention
The embodiment of the invention provides a kind of method of data processing and relevant apparatus, realize when write error occurs
When, the rewrite operation to data are wrongly write reduces the probability of loss of data.
In view of this, first aspect present invention provides a kind of method of data processing, comprising:
When the failure of the first storage region is written in target data, the target data is written to the second storage main control chip
Region；
The main control chip reads target context information, the target context information from second storage region
Address information including the target data and the target data；
The main control chip carries out data deconsolidation process to the target context information, to obtain multiple first sons up and down
Literary information, wherein each first sub- contextual information includes address corresponding to the first subdata and first subdata
Information；
The main control chip sends the multiple first sub- contextual information to first storage region, so that described the
One storage region stores the multiple first sub- contextual information.
In conjunction with the embodiment of the present invention in a first aspect, in the first possible implementation of the first aspect, described
Address information corresponding to one subdata includes logical address corresponding to first subdata；
The method also includes:
Second storage region is written in the corresponding logical address of the target data by the main control chip；
The main control chip carries out data deconsolidation process to the target context information, to obtain multiple first sons up and down
Literary information, comprising:
The main control chip carries out data deconsolidation process to the corresponding logical address of the target data, to obtain multiple the
Logical address corresponding to one subdata.
In conjunction with the embodiment of the present invention in a first aspect, in the second possible implementation of the first aspect, the mesh
The address information for marking data includes: the first physical address and the second physical address, wherein first physical address is storage
Physical address corresponding to the target data described in second storage region, second physical address are deposited for described first
Occurs the corresponding physical address of write-in failure in storage area domain；
Address information corresponding to first subdata includes the first physical address corresponding to first subdata；
The method also includes:
Second storage region is written in corresponding first physical address of the target data by the main control chip；
The main control chip carries out data deconsolidation process to the target context information, to obtain multiple first sons up and down
Literary information, comprising:
The main control chip the first physical address corresponding to the target data carries out data deconsolidation process, more to obtain
First physical address corresponding to a first subdata.
In conjunction with second of possible implementation of the first aspect of the embodiment of the present invention, the first party of the embodiment of the present invention
In the third possible implementation in face, so that first storage region stores the multiple first sub- contextual information,
Include:
The main control chip sends a write request to first storage region in target period, so that described the
One storage region stores a first sub- contextual information；
Or,
The main control chip sends multiple write requests to first storage region in the target period, so that institute
It states the first storage region and stores multiple first sub- contextual informations.
In conjunction with the embodiment of the present invention first aspect to first aspect any one of the third possible implementation
Implementation, in the 4th kind of possible implementation of the first aspect of the embodiment of the present invention, which is characterized in that the master control core
Piece sends the multiple first sub- contextual information to first storage region, so that described in first storage region storage
After multiple first sub- contextual informations, the method also includes:
1) main control chip judges whether the first sub- contextual information stores successfully in first storage region,
In, the first sub- contextual information is any one information in the multiple first sub- contextual information；
2) if the described first sub- contextual information stores successfully in first storage region, the main control chip
Delete the described first sub- contextual information for being stored in second storage region；
Step 1) and step 2) are repeated, until the main control chip is the multiple from first storage region deletion
First sub- contextual information.
Second aspect of the present invention provides a kind of data processing equipment, and the reading data device includes:
Writing module, for when the failure of the first storage region is written in target data, main control chip to be by the target data
It is written to the second storage region；
Read module reads target context information for the main control chip from second storage region, described
Target context information includes the address information of the target data and the target data；
Error handling module carries out data deconsolidation process to the target context information for the main control chip, with
Obtain the multiple first sub- contextual informations, wherein each first sub- contextual information includes the first subdata and described first
Address information corresponding to subdata；
Sending module sends the multiple first sub- context letter to first storage region for the main control chip
Breath, so that first storage region stores the multiple first sub- contextual information.
One is provided in the first possible embodiment of second aspect in conjunction with the second aspect of the embodiment of the present invention
Kind data processing equipment, comprising:
Writing module is also used to the main control chip and deposits the corresponding logical address write-in described second of the target data
Storage area domain；
Error handling module is also used to the main control chip and carries out data deconsolidation process to the target context information,
To obtain the multiple first sub- contextual informations, comprising:
Main control chip carries out data deconsolidation process to the corresponding logical address of the target data, to obtain multiple first sons
Logical address corresponding to data.
In conjunction with the possible embodiment of second aspect of the embodiment of the present invention, the possible embodiment of second of second aspect
In, provide a kind of data processing equipment, comprising:
The address information of the target data includes: the first physical address and the second physical address, wherein described first
Physical address is to be stored in physical address corresponding to target data described in second storage region, and described second physically
Location is to occur the corresponding physical address of write-in failure in first storage region；
Address information corresponding to first subdata includes the first physical address corresponding to first subdata；
Writing module is also used to the main control chip for the target data corresponding first physical address write-in described the
Two storage regions；
Error handling module carries out data deconsolidation process to the target context information for the main control chip, with
Obtain the multiple first sub- contextual informations, comprising:
Error handling module is specifically used for the main control chip the first physical address corresponding to the target data and carries out
Data deconsolidation process, to obtain the first physical address corresponding to multiple first subdatas.
In conjunction with second of possible embodiment of the second aspect of the embodiment of the present invention, the third of second aspect is possible
In embodiment, a kind of data processing equipment is provided, comprising:
Sending module is also used in target period send a write request to first storage region, so that institute
It states the first storage region and stores a first sub- contextual information；
Or,
Sending module is also used in the target period send multiple write requests to first storage region, with
First storage region is set to store multiple first sub- contextual informations.
In conjunction with the embodiment of the present invention second aspect to second aspect any one of the third possible implementation
Implementation, data processing equipment described in the 4th kind of possible implementation of the second aspect of the embodiment of the present invention, comprising:
Error handling module is also used to:
1) main control chip judges whether the first sub- contextual information stores successfully in first storage region,
In, the first sub- contextual information is any one information in the multiple first sub- contextual information；
2) if the described first sub- contextual information stores successfully in first storage region, the main control chip
Delete the described first sub- contextual information for being stored in second storage region；
Step 1) and step 2) are repeated, until the main control chip is the multiple from first storage region deletion
First sub- contextual information.
As can be seen from the above technical solutions, the embodiment of the present invention has the advantage that
In the embodiment of the present invention, a kind of method of data processing is provided, runs on the firmware on SSD main control chip,
Occur to handle data when write error, data are successfully stored into flash chip, guarantees user's storage
The integrality of data.
Detailed description of the invention
Fig. 1 is the schematic diagram of the SSD of the method for data processing in the embodiment of the present invention；
Fig. 2 is one embodiment schematic diagram of the method for data processing in the embodiment of the present invention；
Fig. 3 is one embodiment schematic diagram of data processing equipment in the embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those skilled in the art's every other implementation obtained without creative efforts
Example, shall fall within the protection scope of the present invention.
Description and claims of this specification and term " first ", " second ", " third ", " in above-mentioned attached drawing
The (if present)s such as four " are to be used to distinguish similar objects, without being used to describe a particular order or precedence order.It should manage
The data that solution uses in this way are interchangeable under appropriate circumstances, so that the embodiments described herein can be in addition to illustrating herein
Or the sequence other than the content of description is implemented.In addition, term " includes " and " having " and their any deformation, it is intended that
Cover it is non-exclusive include, for example, containing the process, method, system, product or equipment of a series of steps or units need not limit
In step or unit those of is clearly listed, but may include be not clearly listed or for these process, methods, produce
The other step or units of product or equipment inherently.
The embodiment of the invention provides a kind of method of data processing and relevant apparatus, realize when write error occurs
When, the rewrite operation to data are wrongly write reduces the probability of loss of data.
It should be understood that present invention is mainly applied to the Data processing of solid state hard disk (solid state drives, SSD),
Wherein the flash type of SSD be with NOT-AND flash (not and flash, Nand Flash), in order to make it easy to understand, please referring to figure
1, Fig. 1 is the schematic diagram of the SSD of the method for data processing in the embodiment of the present invention, and the embodiment of the present invention is the number applied to SSD
According to the method for processing, explanation is unfolded below with reference to Fig. 1.
As shown in Figure 1, three parts can be divided into SSD, respectively main control chip, with NOT-AND flash and cache chip,
Wherein, main control chip exists and host side on main control chip for running the operational order including the firmware of SSD
(host) connected interface；With NOT-AND flash, wherein in NOT-AND flash include two parts: logical execution units (logical
Unit number, LUN) for handling the order that main control chip issues, and read on flash chip according to order, be written or
Person wipes target data, and there are multiple LUN, typically 4 or 8 on a flash chip, these LUN can be ordered with parallel processing
It enables, is not construed as limiting herein.Flash chip is for storing target data, and wherein flash chip is Nand type flash memory, according to electronics list
The difference of first density, Nand type flash memory are further divided into single-layer type storage unit (single-level cell, SLC), multiple field
Storage unit (multi-level cell, MLC) and three-layer type storage unit (trinary-level cell, TLC), herein
The type of Nand type flash memory is not limited, in SSD, generally comprises the battle array being made of 8,16 or 32 pieces of Nand type flash chips
Column.Cache chip, for storing the data of the operational order run on main control chip institute temporary needs, the type master of cache chip
To be dynamic random access memory (dynamic random access memory, DRAM), or static random is deposited
Access to memory (static random access memory, SRAM) is herein without limitation.In Nand Flash type flash memory,
What storing data relied on is 0/1 change realization of unit (cell), in write operation, modifies the 0 or 1 of corresponding units,
Cell is the erasable reading unit of minimum operation, and a corresponding floating transistor can store 1bit or more bit data, Nand
In Flash cake core, the unit of minimum write-in is page (page), and general size is 4 kilobytes (kilobyte, KB) or 512
Byte (byte, B), herein without limitation, minimum erasing unit is block (block), and the block corresponding to SSD hardware end is known as physics
Block (physical block), data, which are written, in SSD is written in the mode of super page (super page, superPage), one
SuperPage is distributed on different physical block.
As shown in Figure 1, flash translation layer (FTL) (flash translation layer, FTL) connects in main control chip on SSD
Target data is written in flash chip the write instruction for receiving host side, and when write-in failure occurs, main control chip is by number of targets
According to write-in into cache chip, while the also target data being written is in the corresponding logical address of host side.Then, main control chip
Reading includes the target context information of target data from cache chip, further comprises target in target context information
The corresponding address information of data, wherein include the first physical address and the second physical address, the first physics in address information
Address is to be stored in physical address corresponding to target data in cache chip, and the second physical address is to write in flash chip
Enter unsuccessfully corresponding physical address.Then, main control chip carries out data fractured operation to target context information, has obtained more
A first sub- contextual information, wherein each first sub- contextual information includes that the first subdata and the first subdata institute are right
The address information answered, address information corresponding to the first subdata includes the first physical address corresponding to the first subdata, right
When physical address carries out data fractured operation, size of data interval that can be certain according to intercepts physical address, the object of interception
Managing address is physical address corresponding to subdata, is divided into 4KB or 512B between the general size of data, herein with no restrictions.Ground
It further include the corresponding logical address of target subdata split in the information of location, main control chip obtains that target subdata is corresponding to patrol
After the process of volume address is included in corresponding first physical address of corresponding target subdata, target is searched according to preset offset
The corresponding logical address of subdata.Main control chip is carrying out data fractured operation to target context information, obtains multiple first
After sub- contextual information, the FTL on main control chip sends write request to flash chip according to the first sub- contextual information, sends
Write request includes sending a write request, includes a first sub- contextual information in a write request, for dodging
It deposits and the corresponding subdata of a first sub- contextual information is written in chip, multiple write requests, multiple write-ins can also be sent
It include the multiple first sub- contextual informations in request, it is corresponding for the multiple first sub- contextual informations to be written in flash chip
Subdata.After main control chip judges that the first sub- contextual information stores successfully in flash chip, main control chip can pass through
Delete the sub- contextual information of correspondence first that stores in cache chip, discharge the space of cache chip, so as to store it is new up and down
Literary information, while same sub- context being avoided to handle by multiplicating, cause the waste of error in data and resource.
The method of data processing in the present invention is explained below, referring to Fig. 2, in the embodiment of the present invention, at data
One embodiment schematic diagram of the method for reason, comprising:
101, target data is written to the second storage region main control chip；
In the present embodiment, target data is written the write instruction for running on the firmware receiving host end of SSD main control chip
In flash chip, flash chip is named as the first storage region, when the failure of the first storage region is written in target data, master control
Target data is written into cache chip chip, and cache chip is named as the second storage region.
102, main control chip reads target context information from the second storage region；
In the present embodiment, the firmware for running on SSD main control chip reads target context information from the second storage region,
Target context information includes target data and the corresponding address information of target data.
103, main control chip carries out data deconsolidation process to target context information；
In the present embodiment, the firmware for running on SSD main control chip carries out data to the target context information read and tears open
Point processing, obtains the multiple first sub- contextual informations after fractionation, include the first subdata and the in the first sub- contextual information
Address information corresponding to one subdata.
Wherein, target data is subjected to deconsolidation process according to 4KB or 512B size of data, obtained subdata is named as the
Sub- contextual information comprising the first subdata is named as the first sub- contextual information by one subdata.
104, main control chip sends multiple first sub- contextual informations to the first storage region.
In the present embodiment, the firmware for running on SSD main control chip sends write request to the FTL for running on SSD main control chip,
After the write request that FTL processing receives, main control chip sends multiple first sub- contextual informations to the first storage region, so that the
One storage region stores multiple first sub- contextual informations.
Wherein, FTL avoids the Block that cannot be stored in the first storage region according to preset bad block table, carries out data
Write operation, bad block table are preset in SSD by SSD production firm, for main control chip calling, bad block table that there are modes is general
To be marked in the homepage of Block or endpage, when occurring read error or write error in use process, bad block can be updated
Table, update mode can also can be one array of formulation to be marked in the homepage for the Block for mistake occur or endpage,
There is modifying when an error occurs to corresponding bit with the one-to-one bit of Block (bit) in array, such as just
The bit is 0 when often, and when mistake is revised as 1, is not construed as limiting herein to mode existing for bad block table and mark mode.
In the embodiment of the present invention, a kind of method of data processing is provided, the firmware for running on SSD main control chip first connects
Target data is written in flash chip the write instruction for receiving host side, and flash chip is named as the first storage region, works as mesh
When marking data write-in the first storage region failure, target data is written into cache chip main control chip, and cache chip is ordered
Entitled second storage region.Secondly, the firmware for running on SSD main control chip reads target context letter from the second storage region
Breath, target context information includes target data and the corresponding address information of target data.Again, SSD master control core is run on
The firmware of piece carries out data deconsolidation process to the target context information read, and the multiple first sub- context letters are obtained after fractionation
It ceases, includes address information corresponding to the first subdata and the first subdata in the first sub- contextual information.Again, it runs on
The firmware of SSD main control chip sends write request to the FTL for running on SSD main control chip, after FTL handles the write request received,
Main control chip sends multiple first sub- contextual informations to the first storage region, so that multiple first sons of the first storage region storage
Contextual information.By the above-mentioned means, realizing the rewrite operation when write error occurs, to data are wrongly write, data are reduced
The probability of loss.
Optionally, on the basis of Fig. 2 corresponding embodiment, the method for second of data processing provided in an embodiment of the present invention
Embodiment in, address information corresponding to the first subdata includes logical address corresponding to the first subdata；Further include:
The second storage region is written in the corresponding logical address of target data by main control chip；
Main control chip carries out data deconsolidation process to target context information, to obtain the multiple first sub- contextual informations,
Include:
Main control chip carries out data deconsolidation process to the corresponding logical address of target data, to obtain multiple first subdatas
Corresponding logical address.
It further include by number of targets during the second storage region is written in target data by main control chip in the present embodiment
The second storage region is written according to corresponding logical address, main control chip carries out target context information in data deconsolidation process,
Further include carrying out data deconsolidation process to the corresponding logical address of target data, includes first in obtained multiple first subdatas
The corresponding logical address of subdata.
In the embodiment of the present invention, when the failure of the first storage region is written in target data, main control chip writes target data
Enter the second storage region, which further includes that the second storage region, master control is written in the corresponding logical address of target data
Chip includes that target data and target data are corresponding from the target context information for reading generation in the second storage region
Logical address also split target other than target data splitting when main control chip splits target context information
The corresponding logical address of data has obtained the corresponding logical address of target subdata.In order to the expansion of subsequent step, promotion side
The feasibility of case.
Optionally, on the basis of above-mentioned Fig. 2 corresponding embodiment, the method for data processing provided in an embodiment of the present invention
Third embodiment in, the address information of target data includes: the first physical address and the second physical address, wherein
One physical address is to be stored in physical address corresponding to target data in the second storage region, and the second physical address is deposited for first
Occurs the corresponding physical address of write-in failure in storage area domain；
Address information corresponding to first subdata includes the first physical address corresponding to the first subdata；
Further include:
The second storage region is written in corresponding first physical address of target data by main control chip；
Main control chip carries out data deconsolidation process to target context information, to obtain the multiple first sub- contextual informations,
Include:
Main control chip the first physical address corresponding to target data carries out data deconsolidation process, to obtain multiple first sons
First physical address corresponding to data.
In the present embodiment, when the second storage region is written in target data by main control chip, it is also written with target data write-in
Occur the corresponding physical address of write-in failure, for updating storage the bad block table in SSD, the object in first storage region
Reason address is named as the second physical address, and in reading the target context information generated, it is currently stored to contain target data
The corresponding physical address in the second storage region, the physical address are named as the first physical address.When main control chip is to target
When contextual information is split, also the first physical address of fractionation has been obtained first corresponding to multiple first subdatas
Physical address.
In the embodiment of the present invention, the address information for including in target context information is in addition to target data is corresponding logically
It also include the first physical address and the second physical address, it is bad that the second physical address is used to indicate main control chip update outside location
Block table, the first physical address obtains the corresponding physical address of subdata for splitting, so as to the expansion of subsequent step, lifting scheme
Feasibility.
Optionally, on the basis of above-mentioned Fig. 2 corresponding embodiment, the method for data processing provided in an embodiment of the present invention
The 4th embodiment in, main control chip sends multiple first sub- contextual informations to the first storage region, so that the first storage
Region stores multiple first sub- contextual informations, comprising:
Main control chip sends a write request to the first storage region in target period, so that the first storage region is deposited
Store up a first sub- contextual information；
Or,
Main control chip sends multiple write requests to the first storage region in target period, so that the first storage region is deposited
Store up the multiple first sub- contextual informations.
In the present embodiment, main control chip is sent out after splitting the multiple first sub- contextual informations of generation to the first storage region
The multiple first sub- contextual informations are sent, which includes: main control chip to the first storage region transmission write request, wherein
When sending a write request, a first sub- contextual information is written to the first storage region in main control chip, multiple when sending
When write request, multiple first sub- contextual informations are written to the first storage region in main control chip.
Wherein, since the FTL on main control chip has while handling the ability of multiple write requests, multiple write is sent
Entering request can successively send according to prefixed time interval, can also send, be not construed as limiting simultaneously herein.
In the embodiment of the present invention, the method that main control chip sends the multiple first sub- contextual informations to the first storage region,
Including sending a write request, wherein a first sub- contextual information is written.It further include sending multiple write requests,
The multiple first sub- contextual informations are written.Improve the realization flexibility of scheme.
Optionally, on the basis of above-mentioned Fig. 2 corresponding embodiment, the method for data processing provided in an embodiment of the present invention
The 5th embodiment in, main control chip sends multiple first sub- contextual informations to the first storage region, so that the first storage
After region stores multiple first sub- contextual informations, method further include:
1) main control chip judges whether the first sub- contextual information stores successfully in the first storage region, wherein first
Sub- contextual information is any one information in the multiple first sub- contextual informations；
If 2) the first sub- contextual information has stored in the first storage region successfully, main control chip deletion is stored in the
The sub- contextual information of the first of two storage regions；
Step 1) and step 2) are repeated, until main control chip deletes multiple first sub- contexts from the first storage region
Information.
In the present embodiment, multiple first sub- contextual informations, the first storage are sent to the first storage region in main control chip
Region executes after the receive multiple first sub- contextual information write-ins step 1) main control chip and judges the first sub- context letter
Breath whether store in the first storage region successfully, wherein in the first sub- contextual information be the multiple first sub- contextual informations
In any one information, if then execute the sub- contextual information of step 2) first stored in the first storage region successfully,
Then main control chip deletes the first sub- contextual information for being stored in the second storage region.Main control chip repeats step 1) and step
It is rapid 2) until until main control chip deletes multiple first sub- contextual informations from the second storage region.
In the embodiment of the present invention, main control chip judge the first sub- contextual information whether in the first storage region storage at
Function deletes the first sub- contextual information for being stored in the second storage region if success, until deleting multiple first sub- contexts
Information, by the above method, main control chip can be stored in second by deleting in the case where storing the successful situation of target subdata
Succeeded the sub- context of target stored in storage region, the memory space of the second storage region is discharged, to store new number
According to.Improve the feasibility of scheme.
Data processing equipment in the present invention is described in detail below, referring to Fig. 3, Fig. 3 is in the embodiment of the present invention
One embodiment schematic diagram of data processing equipment, one embodiment of data processing equipment 20 provided in an embodiment of the present invention
In, data processing equipment 20 includes:
Writing module 201, for when the failure of the first storage region is written in target data, main control chip to write target data
Enter to the second storage region；
Read module 202 reads target context information, target context for main control chip from the second storage region
Information includes the address information of target data and target data；
Error handling module 203 carries out data deconsolidation process to target context information for main control chip, more to obtain
A first sub- contextual information, wherein each first sub- contextual information includes that the first subdata and the first subdata institute are right
The address information answered；
Sending module 204 sends multiple first sub- contextual informations to the first storage region for main control chip, so that the
One storage region stores multiple first sub- contextual informations.
In the present embodiment, writing module 201 is used for when the failure of the first storage region is written in target data, main control chip
Target data is written to the second storage region；Read module 202 reads target from the second storage region for main control chip
Contextual information, target context information include the address information of target data and target data；Error handling module 203,
Data deconsolidation process is carried out to target context information for main control chip, to obtain the multiple first sub- contextual informations, wherein
Each first sub- contextual information includes address information corresponding to the first subdata and the first subdata；Sending module 204,
Multiple first sub- contextual informations are sent to the first storage region for main control chip, so that the first storage region storage multiple the
One sub- contextual information.
In the embodiment of the present invention, a kind of data processing equipment is provided, firstly, flash memory is converted in the main control chip on SSD
Target data is written in flash chip the write instruction at layer receiving host end (flash translation layer, FTL),
When write-in failure occurs, target data is written into cache chip main control chip, while what is be written exists there are also target data
The corresponding logical address of host side.Then, main control chip read from cache chip include target data target context
Information further comprises the corresponding address information of target data in target context information, wherein includes in address information
One physical address and the second physical address, the first physical address are to be stored in physics corresponding to target data in cache chip
Address, the second physical address are to occur the corresponding physical address of write-in failure in flash chip.Then, main control chip is to target
Contextual information carries out data fractured operation, has obtained the multiple first sub- contextual informations, wherein each first sub- context letter
Breath includes address information corresponding to the first subdata and the first subdata, and address information corresponding to the first subdata includes
First physical address corresponding to first subdata can be certain according to when carrying out data fractured operation to physical address
Size of data interval intercepts physical address, and the physical address of interception is physical address corresponding to subdata, and the general data are big
Closely-spaced is 4KB or 512B, herein with no restrictions.In address information, further include split target subdata it is corresponding logically
Location, the process that main control chip obtains the corresponding logical address of target subdata are included in corresponding first object of corresponding target subdata
After managing address, the corresponding logical address of target subdata is searched according to preset offset.Main control chip is to target context
Information carries out data fractured operation, and after obtaining the multiple first sub- contextual informations, the FTL on main control chip is upper and lower according to the first son
Literary information sends write request to flash chip, and sending write request includes sending a write request, in a write request
Including a first sub- contextual information, for the corresponding subnumber of a first sub- contextual information to be written in flash chip
According to can also send multiple write requests, include the multiple first sub- contextual informations in multiple write requests, in flash memory core
The corresponding subdata of the multiple first sub- contextual informations is written in piece.When main control chip judges the first sub- contextual information in flash memory
After storing successfully in chip, main control chip can be released by deleting the sub- contextual information of correspondence first stored in cache chip
The space of cache chip is put, to store new contextual information, while avoiding same sub- context by multiplicating
Reason, causes the waste of error in data and resource.
Optionally, on the basis of above-mentioned Fig. 3 corresponding embodiment, data processing equipment 20 provided in an embodiment of the present invention
Second embodiment in,
Writing module 201 is also used to main control chip for the corresponding logical address of target data and the second storage region is written；
Error handling module 203 is also used to main control chip and carries out data deconsolidation process to target context information, to obtain
Multiple first sub- contextual informations, comprising:
Main control chip carries out data deconsolidation process to the corresponding logical address of target data, to obtain multiple first subdatas
Corresponding logical address.
In the embodiment of the present invention, when the failure of the first storage region is written in target data, main control chip writes target data
Enter the second storage region, which further includes that the second storage region, master control is written in the corresponding logical address of target data
Chip includes that target data and target data are corresponding from the target context information for reading generation in the second storage region
Logical address also split target other than target data splitting when main control chip splits target context information
The corresponding logical address of data has obtained the corresponding logical address of target subdata.In order to the expansion of subsequent step, promotion side
The feasibility of case.
Optionally, on the basis of above-mentioned Fig. 3 corresponding embodiment, data processing equipment 20 provided in an embodiment of the present invention
Third embodiment in, the address information of target data includes: the first physical address and the second physical address, wherein
One physical address is to be stored in physical address corresponding to target data in the second storage region, and the second physical address is deposited for first
Occurs the corresponding physical address of write-in failure in storage area domain；
Address information corresponding to first subdata includes the first physical address corresponding to the first subdata；
Writing module 201 is also used to main control chip for corresponding first physical address of target data and the second memory block is written
Domain；
Error handling module 203 carries out data deconsolidation process to target context information for main control chip, more to obtain
A first sub- contextual information, comprising:
Error handling module 203 is specifically used for main control chip the first physical address corresponding to target data and carries out data
Deconsolidation process, to obtain the first physical address corresponding to multiple first subdatas.
In the embodiment of the present invention, the address information for including in target context information is in addition to target data is corresponding logically
It also include the first physical address and the second physical address, it is bad that the second physical address is used to indicate main control chip update outside location
Block table, the first physical address obtains the corresponding physical address of subdata for splitting, so as to the expansion of subsequent step, lifting scheme
Feasibility.
Optionally, on the basis of above-mentioned Fig. 3 corresponding embodiment, data processing equipment 20 provided in an embodiment of the present invention
The 4th embodiment in,
Sending module 204 is also used in target period send a write request to first storage region, so that
First storage region stores a first sub- contextual information；
Or,
Sending module 204 is also used in the target period send multiple write requests to first storage region,
So that first storage region stores multiple first sub- contextual informations.
In the embodiment of the present invention, the method that main control chip sends the multiple first sub- contextual informations to the first storage region,
Including sending a write request, wherein a first sub- contextual information is written.It further include sending multiple write requests,
The multiple first sub- contextual informations are written.Improve the realization flexibility of scheme.
Optionally, on the basis of above-mentioned Fig. 3 corresponding embodiment, data processing equipment 20 provided in an embodiment of the present invention
The 5th embodiment in, error handling module 203 is also used to:
1) main control chip judges whether the first sub- contextual information stores successfully in the first storage region, wherein first
Sub- contextual information is any one information in the multiple first sub- contextual informations；
If 2) the first sub- contextual information has stored in the first storage region successfully, main control chip deletion is stored in the
The sub- contextual information of the first of two storage regions；
Step 1) and step 2) are repeated, until main control chip deletes multiple first sub- contexts from the first storage region
Information.
In the embodiment of the present invention, main control chip judge the first sub- contextual information whether in the first storage region storage at
Function deletes the first sub- contextual information for being stored in the second storage region if success, until deleting multiple first sub- contexts
Information, by the above method, main control chip can be stored in second by deleting in the case where storing the successful situation of target subdata
Succeeded the sub- context of target stored in storage region, the memory space of the second storage region is discharged, to store new number
According to.Improve the feasibility of scheme.
It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description,
The specific work process of device and unit, can refer to corresponding processes in the foregoing method embodiment, and details are not described herein.
In several embodiments provided by the present invention, it should be understood that disclosed system, device and method can be with
It realizes by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the unit
It divides, only a kind of logical function partition, there may be another division manner in actual implementation, such as multiple units or components
It can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, it is shown or
The mutual coupling, direct-coupling or communication connection discussed can be through some interfaces, the indirect coupling of device or unit
It closes or communicates to connect, can be electrical property, mechanical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
In network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme
's.
It, can also be in addition, the functional units in various embodiments of the present invention may be integrated into one processing unit
It is that each unit physically exists alone, can also be integrated in one unit with two or more units.Above-mentioned integrated list
Member both can take the form of hardware realization, can also realize in the form of software functional units.
If the integrated unit is realized in the form of SFU software functional unit and sells or use as independent product
When, it can store in a computer readable storage medium.Based on this understanding, technical solution of the present invention is substantially
The all or part of the part that contributes to existing technology or the technical solution can be in the form of software products in other words
It embodies, which is stored in a storage medium, including some instructions are used so that a computer
Equipment (can be personal computer, server or the network equipment etc.) executes the complete of each embodiment the method for the present invention
Portion or part steps.And storage medium above-mentioned include: USB flash disk, mobile hard disk, read-only memory (read-only memory,
ROM), random access memory (random access memory, RAM), magnetic or disk etc. are various can store program
The medium of code.
The above, the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although referring to before
Stating embodiment, invention is explained in detail, those skilled in the art should understand that: it still can be to preceding
Technical solution documented by each embodiment is stated to modify or equivalent replacement of some of the technical features；And these
It modifies or replaces, the spirit and scope for technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution.
Claims (10)
1. a kind of method of data processing characterized by comprising
When the failure of the first storage region is written in target data, the target data is written to the second memory block main control chip
Domain；
The main control chip reads target context information from second storage region, and the target context information includes
The address information of the target data and the target data；
The main control chip carries out data deconsolidation process to the target context information, to obtain the multiple first sub- context letters
Breath, wherein each first sub- contextual information includes address information corresponding to the first subdata and first subdata；
The main control chip sends the multiple first sub- contextual information to first storage region, so that described first deposits
Storage area domain stores the multiple first sub- contextual information.
2. the method according to claim 1, wherein address information corresponding to first subdata includes institute
State logical address corresponding to the first subdata；
The method also includes:
Second storage region is written in the corresponding logical address of the target data by the main control chip；
The main control chip carries out data deconsolidation process to the target context information, to obtain the multiple first sub- context letters
Breath, comprising:
The main control chip carries out data deconsolidation process to the corresponding logical address of the target data, to obtain multiple first sons
Logical address corresponding to data.
3. the method according to claim 1, wherein the address information of the target data includes: the first physics
Address and the second physical address, wherein first physical address is to be stored in target described in second storage region
Physical address corresponding to data, second physical address are to occur corresponding to write-in failure in first storage region
Physical address；
Address information corresponding to first subdata includes the first physical address corresponding to first subdata；
The method also includes:
Second storage region is written in corresponding first physical address of the target data by the main control chip；
The main control chip carries out data deconsolidation process to the target context information, to obtain the multiple first sub- context letters
Breath, comprising:
Corresponding to the target data the first physical address of the main control chip carries out data deconsolidation process, to obtain multiple the
First physical address corresponding to one subdata.
4. according to the method described in claim 3, it is characterized in that, the main control chip sends institute to first storage region
The multiple first sub- contextual informations are stated, so that first storage region stores the multiple first sub- contextual information, comprising:
The main control chip sends a write request to first storage region in target period, so that described first deposits
Storage area domain stores a first sub- contextual information；
Or,
The main control chip sends multiple write requests to first storage region in the target period, so that described the
One storage region stores multiple first sub- contextual informations.
5. method according to claim 1 to 4, which is characterized in that the main control chip is deposited to described first
Storage area domain sends the multiple first sub- contextual information, so that the multiple first son of first storage region storage is up and down
After literary information, the method also includes:
1) main control chip judges whether the first sub- contextual information stores successfully in first storage region, wherein
The first sub- contextual information is any one information in the multiple first sub- contextual information；
If 2) the described first sub- contextual information stores successfully in first storage region, the main control chip is deleted
It is stored in the described first sub- contextual information of second storage region；
Step 1) and step 2) are repeated, until the main control chip deletes the multiple first from first storage region
Sub- contextual information.
6. a kind of data processing equipment, which is characterized in that
Writing module, for when the failure of the first storage region is written in target data, the target data to be written main control chip
To the second storage region；
Read module reads target context information, the target for the main control chip from second storage region
Contextual information includes the address information of the target data and the target data；
Error handling module carries out data deconsolidation process to the target context information for the main control chip, to obtain
Multiple first sub- contextual informations, wherein each first sub- contextual information includes the first subdata and first subnumber
According to corresponding address information；
Sending module sends the multiple first sub- contextual information to first storage region for the main control chip,
So that first storage region stores the multiple first sub- contextual information.
7. data processing equipment according to claim 6, which is characterized in that
For the main control chip second memory block is written in the corresponding logical address of the target data by writing module
Domain；
Error handling module is also used to the main control chip and carries out data deconsolidation process to the target context information, with
To the multiple first sub- contextual informations, comprising:
The main control chip carries out data deconsolidation process to the corresponding logical address of the target data, to obtain multiple first sons
Logical address corresponding to data.
8. data processing equipment according to claim 6, which is characterized in that the address information of the target data includes:
First physical address and the second physical address, wherein first physical address is to be stored in second storage region
Physical address corresponding to the target data, second physical address are to occur write-in failure in first storage region
Corresponding physical address；
Address information corresponding to first subdata includes the first physical address corresponding to first subdata；
Writing module is also used to the main control chip and deposits the corresponding first physical address write-in described second of the target data
Storage area domain；
Error handling module carries out data deconsolidation process to the target context information for the main control chip, to obtain
Multiple first sub- contextual informations, comprising:
Error handling module is specifically used for the main control chip the first physical address corresponding to the target data and carries out data
Deconsolidation process, to obtain the first physical address corresponding to multiple first subdatas.
9. data processing equipment according to claim 8, which is characterized in that
Sending module is also used in target period send a write request to first storage region, so that described the
One storage region stores a first sub- contextual information；
Or,
Sending module is also used in the target period send multiple write requests to first storage region, so that institute
It states the first storage region and stores multiple first sub- contextual informations.
10. data processing equipment according to any one of claims 6 to 9, which is characterized in that
Error handling module is also used to:
1) main control chip judges whether the first sub- contextual information stores successfully in first storage region, wherein
The first sub- contextual information is any one information in the multiple first sub- contextual information；
If 2) the described first sub- contextual information stores successfully in first storage region, the main control chip is deleted
It is stored in the described first sub- contextual information of second storage region；
Step 1) and step 2) are repeated, until the main control chip deletes the multiple first from first storage region
Sub- contextual information.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114296639A (en) * | 2021-12-10 | 2022-04-08 | 深圳大普微电子科技有限公司 | Command processing method and flash memory device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102298555A (en) * | 2011-08-22 | 2011-12-28 | 宜兴市华星特种陶瓷科技有限公司 | Modular flash management system based on Not AND (NAND) technology |
| US20140189214A1 (en) * | 2013-01-03 | 2014-07-03 | International Business Machines Corporation | False power failure alert impact mitigation |
| CN107102821A (en) * | 2017-04-21 | 2017-08-29 | 济南浪潮高新科技投资发展有限公司 | A kind of NAND FLASH arrays write the processing method of failure |
| CN107247563A (en) * | 2017-07-06 | 2017-10-13 | 济南浪潮高新科技投资发展有限公司 | A kind of block message mark implementation method of NAND FLASH chips |
| CN107562649A (en) * | 2016-06-30 | 2018-01-09 | 爱思开海力士有限公司 | Accumulator system and its operating method |
-
2018
- 2018-07-26 CN CN201810837094.6A patent/CN109002265B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102298555A (en) * | 2011-08-22 | 2011-12-28 | 宜兴市华星特种陶瓷科技有限公司 | Modular flash management system based on Not AND (NAND) technology |
| US20140189214A1 (en) * | 2013-01-03 | 2014-07-03 | International Business Machines Corporation | False power failure alert impact mitigation |
| CN107562649A (en) * | 2016-06-30 | 2018-01-09 | 爱思开海力士有限公司 | Accumulator system and its operating method |
| CN107102821A (en) * | 2017-04-21 | 2017-08-29 | 济南浪潮高新科技投资发展有限公司 | A kind of NAND FLASH arrays write the processing method of failure |
| CN107247563A (en) * | 2017-07-06 | 2017-10-13 | 济南浪潮高新科技投资发展有限公司 | A kind of block message mark implementation method of NAND FLASH chips |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114296639A (en) * | 2021-12-10 | 2022-04-08 | 深圳大普微电子科技有限公司 | Command processing method and flash memory device |
| CN114296639B (en) * | 2021-12-10 | 2024-02-20 | 深圳大普微电子科技有限公司 | Command processing method and flash memory device |
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