JPH0827621B2 - Electronic musical instrument - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic musical instrument in which control elements for tone generation modes such as tone color effects and rhythm effects are automatically set, and the control elements for tone generation modes can be arbitrarily set.

[0002]

2. Description of the Related Art An electronic musical instrument adapted to be automatically played is provided with a musical score data storage means for storing the musical performance information, and the musical score data storage means comprises pitch data and note length data. It is conceivable to store the note data in the note sequence.

That is, from this musical score data storage means,
The note data is read at a time interval corresponding to the note length, a tone generator signal with a tone pitch corresponding to the tone pitch data included in the read note data is generated, and this tone generator signal is appropriately formed as a tone to produce a performance sound. Make it sound. In this case, an automatic rhythm playing device is also appropriately attached, and the note length is measured by the tempo clock signal.

In such an automatic performance device, a performance sound corresponding to a note expressed in a musical score is automatically generated, and the timbre effect of this performance sound and the effects such as vibrato and tremolo are also produced. Etc. are set and controlled based on the operator's intention, and the operator selectively sets the rhythm type, start control, tempo control, etc. in the automatic rhythm playing device.

The performer using the automatic performance device needs to listen not only as music but also as a model performer. For this purpose, musical tone formation and generation modes such as model tone setting are automatically detected. Is important to be set to. In addition, it is very important to learn the musical performance expression style by arbitrarily changing the musical sound generation mode in order to learn musical instrument performance and also to acquire musical sense.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and not only can an automatic performance sound be obtained in an exemplary state such as a tone generation mode, but the generation mode can be further improved. The present invention aims to provide an electronic musical instrument that can be appropriately arranged so that music lessons and the like can be effectively performed.

[0007]

An electronic musical instrument according to the present invention further comprises an operator for setting musical tone control data, a means for reading musical note data and musical tone control data from a memory means for storing musical tone control data, and a means for reading the musical note data and musical tone control data. A storage means for storing the note data and the musical tone control data read by the reading means is provided, and the note data is sequentially read from these storage means and supplied to the musical tone forming means for automatic performance. Further, a manual musical tone forming means for generating a manual musical tone signal is provided, and the musical tone generating modes of the automatic musical tone signal and the manual musical tone signal are controlled based on the storage data of the control data storage means. The stored data in the control data storage means is rewritten and set by the operator.

[0008]

In the electronic musical instrument constructed as described above, a musical tone signal for automatic performance is formed based on the stored note data and musical tone control data, and a musical tone corresponding to a manual operation is also generated. Will be done. And
The control data of these musical tones is basically stored, but this musical tone control data is arbitrarily rewritten by the operation of the operator, and the musical tone performance based on the rewritten control data is reproduced. Done. That is,
Not only the musical tone generation mode of the automatic performance sound as a model,
Even the generation mode of the manual performance tone is set together with the generation mode of the automatic performance tone. Therefore, it is possible to perform a manual performance that matches the model automatic performance and effectively practice the performance.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. First, the basic configuration will be described with reference to FIG. 1. The storage means A for storing preset note data and tone control data is provided, and the data stored in this storage means is read by the reading means B and controlled. The data is stored in the control data storage means C, and the note data is supplied to the automatic performance tone forming means D to form an automatic performance tone signal. The data generated by the manual performance operator E is supplied to the manual musical tone forming means F. The automatic musical tone forming means D and the manual musical tone forming means F are controlled by the control data storage means C. It is controlled by the control means G to which data is supplied. Then, the control data of the control data storage means C can be appropriately rewritten by the control data setting operator H.

2 to 3 show a concrete circuit configuration of such an automatic performance device. Performance information composed of note data and control data for performing an automatic performance is stored in an external storage device. The memory is set. And
An external storage device is selected according to the piece of music to be played, and the stored performance information is read and used.

The external storage device is composed of, for example, a musical score 11 on which the musical score of the stored music is drawn, and a recording unit 12 such as a magnetic tape is set at the lower edge of the musical score 11, for example. Performance information is digitized and recorded in the recording unit 12.

The musical score 11 on which the performance information is recorded is used, for example, as a musical score stand of an electronic musical instrument cabinet, and the recording unit 12 is scanned by a magnetic head in correspondence with the musical score stand. Reader 13 for reading recorded performance information
Is set. It is effective that the recorded performance information of the recording unit 12 is read while the musical score 11 is placed on the music stand.

The form of the performance information recorded in the recording unit 12 is
For example, as shown in FIG. 5, the musical tone control data is first set. The tone control data is composed of, for example, m bits, and first and second data (Data 1 and Data 2) are serially arranged and set following the control data. Here, as the first data, note data consisting of pitches and note lengths expressing a melody is set in a note sequence.

Then, the song ends (FIN
ISH) code is recorded, and is further connected to the second data via a delimiter code. This second data expresses an accompaniment note, and is composed of note data that is a combination of pitch data (root note data) corresponding to the root note of a chord and note length data, and this note data is generated. They are arranged in series in sequence and end with a delimiter code.

The performance information read by the reader 13 is R
It is written in the front data memory 14 such as AM. That is, when the musical score 11 is loaded into the reader 13, the writing control circuit 15 is instructed to
A write command WT is given from 15 to the front data memory 14.

At the same time, address data is generated from the write control circuit 15, and this address data is sent to the selector 16
Is given to the data memory 14 as an address command. At this time, the selector 16 is instructed to select the address data from the control circuit 15 in response to the state in which the write control circuit 15 issues the write command WT.

Then, the recording data of the recording section 12 of the musical score 11 is read by the reader 13, sequentially addressed in the state shown in FIG. 5, and written in the front data memory 14. This data reading operation is ended when the delimiter code following the second data is detected.

The performance information stored in the pre-data memory 14 is set in the state of serial bits, and the read information is read through the gate circuit 17 to convert the serial bits into parallel bits. 3 S / P conversion circuits 18, 19, 20
Supply to. In this case, the first conversion circuit 18 corresponds to the first data corresponding to the melody, the second conversion circuit 19 corresponds to the second data corresponding to the accompaniment sound, and the third conversion circuit 20 corresponds to the second data. Corresponds to tone control data.

The first and second S / P conversion circuits 18 and
The parallel-converted data from 19 are supplied to the score data memories 21 and 22, respectively, and are also guided to the delimiter code detection circuits 23 and 24, where they are followed by the delimiter code D1 and the second data. Separator code D2
Are detected respectively.

The musical score data memories 21 and 22 are addressed by the address generating circuits 25 and 26, respectively, and are controlled to be written (WRITE) or read. The delimiter code detection signals D1 and D, respectively.
The first data (melody part) set to the write or read state by the mode control circuit 27 supplied with 2 and read from the front data memory 14 is stored in the score data memory 21 as the second data (accompaniment data). Parts) are written and stored in the score data memory 22.

For example, for the score data memory 21,
As shown in FIG. 6A, note data composed of a combination of pitch data and note length data is stored and set in order of address. In this case, the rest note is also stored and set as one of the pitch data in combination with the (all 0) note length data, and the end code (FINISH) of the song is stored and set.
These note data are read out in an address sequence.

Also in the musical score data memory 22, as shown in FIG. 6B, a combination of pitch data and note length data corresponding to a root note indicating a chord is stored in order of address. There is.

The musical score data memory 21 and
The pitch data part of the read note data from each 22 is supplied to the automatic performance sound forming circuit 29, and the note length data part is supplied to the read control circuits 30 and 31, respectively.

The automatic performance tone forming circuit 28 generates a tone signal having a pitch corresponding to the supplied pitch data, and the automatic accompaniment tone forming circuit 29 determines this pitch based on the supplied pitch data. A chord chord component sound as a root sound and a tone signal of a bass sound are generated. Then, these generated tone signals are supplied to the speaker 33 via the amplifier 32,
Be pronounced as a performance sound.

The read control circuits 30 and 31 respectively count and measure the time corresponding to the code length data, generate a code length match signal when the code length of time elapses from the time of input, and generate the code length matching signals respectively. And supply to 26.

In addition, the output data from the musical score data memory 21 is monitored by the end detection circuit 34, and the end code (F
When INISH) is read, these are detected, and this detection signal is supplied to the mode control circuit 27. The pitch data read from the musical score data memory 21 is recorded on the keyboard 35.
The key depression display circuit 36 for selectively instructing each key is displayed and controlled, and the key to be depressed is instructed corresponding to the pitch data to assist the performance practice.

From the key switch circuit 35a corresponding to the keyboard 35, the keying data corresponding to the key depression operation is obtained, and the tone forming circuit 37 obtains the tone signal corresponding to the key operation. Is supplied to the speaker 33 via the amplifier 32 and is sounded as a performance sound.

A start switch 30 and a repeat switch 39 are attached to the mode control circuit 27, and a start command (STRT) and a repeat command (REP) are input corresponding to the operation of the switches 38 and 39, respectively. .

The mode control circuit 27 controls the mode such as reading and writing of performance information and read-out automatic performance. For convenience of explanation of the signal system, the front data memory 14, the musical score data memories 21 and 22 will be described below. In connection with the corresponding signal description, these memories 14, 21,
22 are tentatively referred to as RAM1, RAM2, and RAM3, respectively.

The mode control circuit 27 first issues a RAM1 address counter clear command to the front data memory 14 system, and resets the address counter 40. The address counter 40 is counted by the clock φ, and the address data corresponding to the count value is supplied to the front data memory 14 via the selector 16. Further, the count value of the address counter 40 is supplied to a decoder 41 for detecting the bit number m of the control data, and when the address m is detected, a detection signal (PDEND) is generated from the decoder 41 and the AND circuit 42 is used. It is supplied to the mode control circuit 27. The pre-data command signal from the mode control circuit 27 is supplied to the AND circuit 42 as a gate signal.

Address reset signal ADR is generated from mode control circuit 27, and address generation circuits 25 and 26 are generated.
To the musical score data memories 21 and 22 and a write command / WT is given to the musical score data memories 21 and 22.

Then, chip enable signals MCE2 and MCE3 are further generated for the data memories 21 and 22, respectively, and chip enable commands / CE are given respectively. Corresponding to this chip enable, mode control circuit
Write signals of RAM2 and RAM3 are generated from 27,
The address generation circuits 25 and 26 are set to the data write command state W, and a clear command is generated to control both the address generation circuits 25 and 26 to clear.

FIG. 7 shows a concrete configuration example of the address generation circuit 25, which is provided with an address counter 43. The maximum count value of this counter 43 is set in correspondence with the maximum address of the corresponding memory 21, and when the maximum count value (MAX count) is reached, a signal ACTO is generated and supplied to the mode control circuit 27. become. Then, this count value information is output as address data.

The counter 43 is reset by the signal ADR,
The output signal of the OR circuit 44 makes it possible to increment the count, and the OR circuit 44 is supplied with the code length coincidence signal from the read control circuit 30 and the signals from the AND circuits 45 and 46.

The clear signals (RA
M2, RAM3) and a write command (RAM2) are respectively supplied as gate signals, and the clock .phi. And a signal obtained by appropriately dividing the clock .phi. Continuously increment each.

A clear signal (RAM2
, RAM3) R occurs at high speed by clock φ when generated
Since "0" is written to AM2, this RAM2 will be substantially cleared. When a write command (RAM2) is generated, serial serial data from the front data memory 14 is converted into parallel data by the S / P conversion circuit 18, and this parallel data is written in RAM2 by a signal obtained by dividing the clock φ. Be done.

The address generating circuit 26 is also constructed in the same manner as described above. In this case, the output circuit of the signal ACTO is not particularly provided, and the code length coincidence signal is obtained from the read control circuit 31.

FIG. 8 shows a concrete configuration of the mode control circuit 27, which is provided with a flip-flop circuit 47 for setting a play mode (PLAY) of automatic performance and a trigger flip-flop 48 for setting a repeat mode. When the set play or repeat mode is set, the display lamps 49 and 50 are turned on.

The start signal RTRT corresponding to the operation of the start switch 38 is supplied to the differentiating circuit 51,
A differential pulse-shaped start signal ΔSTRT is generated, and this signal resets the flip-flop circuit 47 via the OR circuit 52 and further resets the trigger flip-flop 48. Then, the flip-flop circuit 47 generates a play mode command signal PLAY when set.

The OR circuit 52 is supplied with an end signal FINISH, which is a trigger flip-flop.
It is supplied to the AND circuit 53 to which a gate signal is given when 48 is set. The output signal from the AND circuit 53 is supplied as a preset load command LD to the preset counter 55 via the delay circuit 54 which is a delayed flip-flop driven by the clock φ.

The preset counter 55 has a start signal Δ
It is reset and initialized by STRT, and is configured by a 3-bit binary counter, and is preset to "100" by 3 bits in response to the preset load command LD.

The 3-bit output count data "Q1, Q2, Q3" from the counter 55 is supplied to the decoder 56, and "0""1""2""3" corresponding to this count data.
An output signal is generated on the output signal line of "4".

The output lines corresponding to the count values "0" to "4" of the decoder 55 are cleared (R
AM2, RAM3) command, pre-data, writing (WR
ITE) RAM2 and RAM3 signals respectively corresponding to the respective outputs "1" to generate the corresponding command signals.

The output signals of the "1", "2" and "3" lines of the decoder 56 are detected by the OR circuit 57, and the signal MCL is output.
As a gate signal to the gate circuit 17 to which the read data from the pre-data memory 14 is supplied. Furthermore, "0", "2" and "3" lines, "0"
The NOR circuits 58, 59, and 60 detect the state where no output is present on the "2" line and the "0" or "3" line, respectively, so that the output signals of the signals MWT, MCE2, and MCE3 are obtained. When the decoder 56 obtains the count value "4", the differentiating circuit 61 detects this and gives a set command to the flip-flop circuit 47.

Then, the count value "0" of the decoder 56 is further added.
The output signal of is supplied to the AND circuit 62 together with the input signal ACTO, and the output signal from this AND circuit 62 is RA
It is taken out as an M1 clear signal and the address counter 40 is reset.

The output signal from the AND circuit 62, the star and the signal ΔSTRT, and the signal PDEN which is further input.
The presence of any one of D, D1 END, D2 END, and FINISH is detected by the OR circuit 63, and the output signal from the AND circuit 62, the signals PDEND, D1END, D2 END, and FI.
The presence of either NISH is detected by the OR circuit 64. The output signal from the OR circuit 63 is taken out as a signal ADR, and the output signal from the OR circuit 64 is a preset counter 55.
Is supplied as a count signal to the.

The trigger input terminal T of the trigger flip-flop 48 is supplied with the repeat signal REP obtained in response to the operation of the repeat switch 39. And
The trigger flip-flop 48 is controlled to be inverted.

The start signal ΔSTRT from the mode control circuit 27 is supplied to the control register circuit 65. The control register 65 is supplied with the parallel data from the third S / P conversion circuit 20, and stores and holds the parallel data. in this case,
The S / P conversion circuit 20 has a PD obtained from the AND circuit 42.
The END signal is supplied, and the bit parallel conversion operation is stopped corresponding to the output signal from the decoder 41 when the address count value of the address counter 40 becomes m.

That is, for the control register circuit 65, m bits from the beginning of the data stored in the front data memory 14,
That is, the control data section is stored in the register circuit 65.

That is, m pieces of setting information used for controlling the generation of musical tones are stored and set in the control register circuit 65, and setting switches corresponding to these m pieces of setting information are set on the panel surface of the electronic musical instrument. The switch circuit group 66 configured by is set. Each switch of the switch circuit group 66 is provided with a display lamp group for instructing a setting state corresponding to the switch, and the lamp group is selectively turned on and displayed by the storage control data of the control register circuit 65.

In this case, the setting storage information of the control register circuit 65 can be selectively rewritten and controlled by the switch circuit group 66. Then, the control data stored and held in the control register circuit 65 is supplied to the automatic performance sound forming circuit 28, the automatic accompaniment sound forming circuit 29 and the musical sound forming circuit 37, and the tone color, the modulation effect and the like of the musical sound to be produced are generated. Set.

Further, the control data relating to the rhythm performance of the control register circuit 65, that is, the control data such as the rhythm type and the rhythm sync start, is stored in the rhythm pattern memory.
Supply to 67. The rhythm pattern memory 67 is supplied with binary count data from a counter 69 that counts the tempo clock signal TCL from the tempo oscillator 68. The bit data forming the binary count data is combined to obtain control data. Generate a rhythm pattern signal of the type specified in. This rhythm pattern signal drives the rhythm tone generator circuit 70 to obtain an automatic rhythm performance tone generator signal, and this tone generator signal is supplied to the amplifier 32.
It is sounded as an automatic rhythm performance sound from the speaker 33.

Here, the tempo clock signal from the oscillator 68 is supplied to the read control circuits 30 and 31 and is used as a clock signal for counting and measuring the note length, and the output pattern signal of the rhythm pattern memory 67. Then, the accompaniment sound forming circuit 29 is controlled so that the accompaniment music sound signals such as chord chords and bass sounds are expressed in correspondence with the rhythm pattern. In addition, the automatic performance sound and accompaniment sound forming circuit 28,
A signal PLAY is supplied from the mode control circuit 27 to 29, the key press display circuit 36, the read control circuits 30 and 31, and the counter 69 to instruct the automatic performance operation mode.

FIGS. 9 and 10 show a concrete example of the configuration of the control register 65 section. First, the S / P conversion circuit 20 section of the input section is in the serial bit state taken out through the gate circuit 17. An m-bit shift register 71 to which the read data from the front data memory 14 is supplied is provided.

That is, when the m-bit control data is read from the front register 14, the control data is stored in each digit of the shift register 71. This shift register 71
The control data stored in each digit of 1-bit is supplied in parallel to the latch circuit 72, which is generated when the m-bit control data is read from the front register 14. A latch command is given by the signal PDEND, and the control data is latched and stored in the latch circuit 72 in the parallel bit state.

Then, this latched control data is
One-shot circuit 73 driven by signal PDEND
Is taken out through the gate circuit 74, which is gate-controlled by the pulse signal from, and supplied to the control register circuit 65.

The control register 65 is the first to fourth registers.
It is divided into 75, 76, 77 and 78. And, for example, the first
The register 75 corresponds to control data such as rhythm start, tremolo for upper keyboard and lower keyboard, vibrato, rhythm sync start, and the like, and includes a first switch circuit group 66a composed of switch circuits corresponding to the respective data. Each of the switch circuits forming the switch circuit group 66a is, for example, push-on and push-off.

The second register 76, the third register 77, and the fourth register 78 are used for a rhythm select switch circuit group 66b, an upper / lower keyboard tone color preset switch circuit group, and a mode for obtaining a base chord of an automatic accompaniment tone (single finger). , Full-fingers, etc.) selection switch circuits, which correspond to these control data, respectively.

The second to fourth registers 76-
In the 78 switch circuit group, a switch circuit group exists for each control data, and when one of the switch circuit groups is set and operated, the other switch circuit groups are all released. I am configuring. Here, the second to fourth registers 76 to 78 have the same configuration, and the internal configuration is represented by the register 76 as a representative.

First, in the first register 75, a plurality of control data set by the switch circuit group 66a are supplied to the multiplexer 79 which is taken out in parallel. The multiplexer 79 is controlled by the count signal from the counter 80, and the plurality of setting control data are sequentially taken out and supplied to the shift register 81.

Here, when the number of control data set in the switch circuit group 66a is P, this data is composed of 1-bit data representing ON and OFF, respectively, and the shift register 81 is composed of P digits. . The output bit data from the shift register 81 is inverted by the inverter 82 and supplied to the AND circuit 83 together with the output bit data from the multiplexer 79.

From this ant circuit 83, a switch circuit group
When a certain switch circuit in 66a is switched to the ON state, an output signal of logic "1" is obtained at the output timing of the data corresponding to the switched switch circuit.

The output signal from the multiplexer 79 is inverted by the inverter 84 and supplied to the AND circuit 85 together with the output signal from the shift register 81. From the AND circuit 85, a switch in the switch circuit group 66a is turned off. When switched to the state, the output signal of logic "1" is obtained at the output timing of the data corresponding to the switched switch circuit.

The output signals from the AND circuits 83 and 85 are supplied to the demultiplexers 86a and 86b controlled by the counter 80, respectively, and are returned to the parallel bit data. OR circuit
87a, 87b, ... And 88a, 88b ,.

The OR circuits 87a, 87b, ... Are gate circuits.
Of the m-bit control data obtained from 74, the P-bit control data corresponding to the first register 75 is supplied. Output signals from the OR circuits 87a, 87b, ... Are supplied to set terminals of flip-flop circuits 89a, 89b ,.

Further, a star and a signal ΔSTRT are supplied to the OR circuits 89a, 89b, ...
The output signals from 89a, 89b, ... Are supplied to the reset terminals of the flip-flop circuits 89a, 89b ,.

That is, when the start signal ΔSTRT is generated from the mode control circuit 27, all the flip-flop circuits 89a, 89b, ... Are reset and initialized.
After that, the flip-flop circuits 89a, 89b, ... With the control data corresponding to the first register 75 from the S / P conversion circuit 20.
Is selectively set to store and hold the control data. P-bit output control data is obtained according to the set or reset state of the flip-flop circuits 89a, 89b, ....

In this state, the switch circuit group on the panel surface
When a switch operation is performed at 66a, an output signal is obtained from the AND circuit 83 in the ON state and an output signal from the AND circuit 85 in the OFF state, and the flip-flop circuits 89a, 89b,
The memory by ... will be rewritten according to the new switch operation.

Reference numeral 90 is a lamp group provided corresponding to each switch of the switch circuit group 66a, and lighting is controlled according to the set or reset state of the flip-flop circuits 89a, 89b, ..., And the state of the control data at that time Will be displayed.

In the second register 76, the bit data corresponding to the setting state of each switch circuit of the switch circuit group 66b is sequentially taken out by the multiplexer 91 controlled by the counter 80 and supplied to the shift register 92. The shift register 92 is configured to have a bit number q of control data for the second register 76, and its output bit data is supplied to the AND circuit 94 together with the output data from the multiplexer 91 via the inverter 93.

In other words, the AND circuit 94 generates an output signal at the control data timing corresponding to the switch when any switch of the switch circuit group 66b is operated. The output from the AND circuit 94 The signals are timing-distributed by the multiplexer 95, and the OR circuit 96a
, 96b, ...

The OR circuits 96a, 96b, ...
The q-bit control data corresponding to the second register 76 from the conversion circuit 20 is distributed and supplied.
The output data from a, 96b, ... Is supplied to the latch circuit 97. When an output occurs in any of the OR circuits 96a and 96b, the latch circuit 97 detects the output by the OR circuit 98 and gives a latch command. Then, the storage control data of the latch circuit 97 is taken out as control data, and the lamp group 99 corresponding to the switch circuit group 66b is display-controlled.

That is, from the S / P conversion circuit 20 to the second
For the register 76 of
A control command for selecting and specifying one of q types of control contents is input.

For example, when a control target corresponding to the OR circuit 96a is selected, only the bits distributed to the OR circuit 96a are set to "1" and all other bits are set to "0". Control data is input, and the q-bit data is latched and stored in the latch circuit 97 in correspondence with the OR circuit 98 that detects the data "1".

When one switch in the switch circuit group 66b is operated in this state, the signal "1" is given from the demultiplexer 95 to the OR circuit 96b corresponding to the operated switch, and the OR circuit 96b is supplied. In response to the output 98, the control data in which the portion corresponding to the OR circuit 96b becomes "1" is written in the latch circuit 97. That is, the contents of the control data can be rewritten by the switch circuit group 66b, and the contents of the data stored in the latch circuit 97 are displayed by the lamp group 99.

Registers 77 and 78 are respectively constructed in the same manner as register 76, and r-bit control data and s-bit control data are set respectively.

In the electronic musical instrument constructed as described above, first, the musical score, which is an external storage device, is set prior to its automatic performance.
11 is set in the reader 13. When the musical score 11 is set in this manner, the reader 13 scans the recording section 12 set on the musical score 11 and starts reading the recorded performance data. At the same time, a command is given to the write control circuit 15, a write command WT is given from this circuit to the pre-data memory 14, and a select command is given to the selector 16 so that the address data generated by the write control circuit 15 is transferred to the pre-data memory 14. The performance data as shown in FIG. 5 read by the reader 13 is written in the pre-data memory 14 in the address order as it is. This completes the preparation for automatic performance.

When the start switch 38 is operated in such a ready state, the mode control circuit 28 generates a star and a signal ΔSTRT. This signal is supplied to the control register circuit 25, the mode control circuit 27 resets the flip-flop circuit 47 and the trigger flip-flop 48, and further, the signal ADR is generated via the OR circuit 63. That is, a reset command is given to the address generation circuits 25 and 26 corresponding to the musical score data memories 21 and 22 to initialize them.

In the mode control circuit 27, the preset counter 55 is reset with the generation of the star and the signal ΔSTRT, and its outputs Q1, Q2, Q3 are "000".
Becomes "1" on the line corresponding to "0" of the decoder 56.
Signal is generated, and a clear command for RAM2 and RAM3 is generated.

At this time, the output signal M from the NOR circuits 58 to 60
WT, NCE2, and MCE3 are "0", and the score data memories 21 and 22 are both in the write state and the chip enable state.

When a clear command is given to the address generation circuits 25 and 26, as is apparent from FIG. 7, the address counter 43 reset by the signal ADR starts to advance by the clock φ and is set to the write state. Further, an address command to be sequentially stepped is given to the musical score data memories 21 and 22.

At this time, since the gate circuit 17 of the output circuit of the front data memory 14 is closed, the input data to the score data memories 21 and 22 are all "0", and the storage of the score data memories 21 and 22 is made. All data is "0"
And will be cleared. When the count value of the address counter 43 of the address generation circuit 25 reaches the maximum value, the signal A
A CTO is generated, and a signal is given to the AND circuit 62 in the mode control circuit 27.

At this time, since the “0” line of the decoder 56 is “1”, the signal ACTO from the AND circuit 62 is output.
An output signal is obtained in response to this, a RAM1 clear signal is generated, and the address counter 40 is reset and initialized.

At the same time, the output signal of the AND circuit 62 is the OR circuit.
It is taken out as a signal ADR via 62, and the address generating circuits 25 and 26 are reset and initialized.
The preset counter 55 is incremented by 1 via 64.

When the preset counter 55 is incremented, an output signal of the line "1" of the decoder 56 is generated, pre-data is generated and a gate signal is given to the AND circuit 42, and a signal MCL is generated. Then, the gate of the gate circuit 17 is opened.

At this time, as described above, the address counter 40 is reset and initialized, and then is incremented by the clock φ, and the selector 16 reads the external data from the write control circuit 15. Address counter 40 because no select command for
The front data memory 14 is sequentially addressed from the top address.

At this time, since the data memory 14 is not in the reading state, it is in the reading state, and the previously stored performance sound data is sequentially read from the beginning, and the S / P conversion circuit is read through the gate circuit 17. 18 to 20 are supplied in parallel. However, since the musical score data memories 21 and 22 are not in the writing mode, the output data of the S / P conversion circuits 18 and 19 do not act.

The control data of m bits from the beginning read from the front data memory 14 is the S / P conversion circuit as it is.
When the m-bit data output is completed, the m-bit detection signal is obtained by the decoder 41, and the signal PDEND is taken out through the AND circuit 42 to which the gate signal is applied. And is supplied to the mode control circuit 27 and the S / P conversion circuit 20.

In the S / P conversion circuit 20, as is apparent from FIGS. 9 and 10, the latch command is given to the latch circuit 72 by the signal PDEND, and the control written in the m-bit shift register 71 is performed. Latch data,
It is distributed to the first to fourth registers 75 to 78 through the gate circuit 74 and stored and held as described above.

In the mode control circuit 27, the output signal is generated from the OR circuits 63 and 64 by the input signal PDEND, and the signal ADR is generated to generate the address circuit.
When the reset of 25 and 26 is confirmed, the preset counter 55 is incremented, and the output signal is generated on the "2" line of the decoder 26.

When an output signal is generated on the "2" line of the decoder 56, the output signals of the NOR circuits 58 and 59 become "0", and a write command (WRITE RAM2) is generated. That is, the musical score data memory 21 is set to the written state, and the address of the address generating circuit 25 is incremented by the clock φ.

Therefore, the first data read out from the pre-data memory 14 via the gate circuit 17 following the control data has the format shown in FIG. 6A via the S / P conversion circuit 18. Is written in the musical score data memory 21 with. Then, the first data is the end code (FI
(NISH) is written in the data memory 21, the delimiter code is then output from the S / P conversion circuit 18, which is detected by the delimiter code detection circuit 23, and the detection signal D1
END is generated.

The delimiter detection signal D1 END causes the mode control circuit 27 to generate the signal ADR, increments the preset counter 55, and outputs the signal to the "3" line of the decoder 56. Therefore, the writing state to the musical score data memory 21 is stopped and the reset of the address generating circuits 25 and 26 is confirmed.

Then, the musical score data memory 22 is set to the write operation state, the write command (WRITE RAM3) is supplied to the address generating circuit 26, and the address is advanced in the clot φ.

That is, the second data read from the front data memory 14 through the gate circuit 17 is written in the score data memory 22 in the format shown in FIG. The detection signal D2 END is obtained from the delimiter code detection circuit 24 upon completion of the writing of the data.

The delimiter detection signal D2 END is supplied to the mode control circuit 27, which generates a signal ADR to reset the address generation circuits 25 and 26 for initialization and to advance the preset counter 55 to advance the decoder 56. The output signal is generated on the line "4".

Therefore, the signal MCL is cut off, the gate of the gate circuit 17 is closed, and the data read operation from the pre-data memory 14 is completed. In this state, the output signals from the NOR circuits 58 to 60 of the mode control circuit 27 are all "1", and the musical score data memories 21 and 22 are set to the read state.

When a signal rises on the line "4" of the decoder 56, a differentiation pulse is generated from the differentiation circuit 61 and the flip-flop circuit 47 is set. Therefore, the play operation command PLAY is generated and the lamp 49 displays the play state.

This operation command PLAY is generated by the automatic performance sound and automatic accompaniment sound forming circuits 28, 29, the read control circuits 30, 31,
The counter 69 is set to the operating state. In the read control circuits 30 and 31, first, the address generation circuits 25 and 26 are incremented by one so that the note data of the leading address is read from the score data memories 21 and 22, respectively. To be done.

That is, the automatic performance tone forming circuit 28 generates a tone signal corresponding to the pitch data of the note data read from the score data memory 21. Also, the accompaniment sound forming circuit
At 29, based on the root note data of the note data read out from the musical score data memory 22, a chord chord and a musical tone signal of a bass note are formed.

In this case, the rhythm pattern signal from the rhythm pattern memory 67 based on the count signal from the counter 69 to which the operation is instructed causes the tone signals of the chord chord and the bass tone to be interrupted, and the accompaniment tone signal is the performance tone. Forming circuit
It is supplied to the amplifier 32 together with the tone signal from 28 and is generated as an automatic performance tone. At the same time, the rhythm tone generator circuit 70 is driven by the output pattern signal from the rhythm pattern memory 67, and an automatic performance accompanied by a rhythm performance is expressed.

In this case, the control data from the control register circuit 65 is the automatic performance sound forming circuit 28, the automatic accompaniment sound forming circuit.
It is distributed to 29, and the generation mode of the melody playing sound and the accompaniment sound is determined by this control data. Further, the mode of the rhythm pattern signal generated from the rhythm pattern memory 67 is also selected and set by the control data from the control register circuit 65.

The note data output from the musical score data memory 21 is also supplied to the key pressing display device 36, and the operation key corresponding to this note data is indicated and displayed on the keyboard 35. Therefore, the trainee can perform the automatically performed performance on the keyboard 35 by manually operating the designated key, and based on the pitch data from the key switch circuit 35a accompanying the operation of this key. A tone signal is generated in the tone forming circuit 37.

That is, a manual performance practice musical tone signal is obtained from the musical tone forming circuit 37 by using the automatic performance tone information from the automatic performance tone forming circuit 28 as a model performance source, and an effective manual keyboard performance practice is executed. become able to.

In this case, if the musical tone signal level output from the automatic musical tone generating circuit 28 is cut off or reduced, the musical tone of the manual performance can be clearly expressed and effective musical performance can be practiced.

In such a playing state, the note length data included in the note data read from the score data memories 21 and 22 are stored in the read control circuits 30 and 31, respectively. In the read control circuits 30 and 31, the tempo oscillator 68
Counting the tempo clock signal TCL from, and measuring the passage of time corresponding to the stored note length data respectively. When the time corresponding to the stored note length data has elapsed since the reading of the note data, A step command is given to the corresponding address generation circuits 25 and 26, and the address counter 43 is stepped to the score data memory 2 respectively.
Read the note data of the next address from 1 and 22.

That is, the note data is sequentially read from the score data memories 21 and 22 at time intervals corresponding to the note length data included in the note data, and the automatic performance is continued.

When the automatic performance is completed,
The end code (FINISH) is read from the musical score data memory 21, and this is detected by the end code detecting circuit 34. This end detection signal FINISH is used in the mode control circuit.
27, and resets the flip-flop circuit 47 via the OR circuit 52.

At the same time, this signal is taken out through the OR circuits 63 and 64, the address generation circuits 25 and 26 are reset and initialized, and the preset counter 55 is stepped up to the line "5" of the decoder 56. After the output signal is generated, the automatic performance operation is completed.

When the repeat switch 39 is operated in the automatic performance state, a trigger command is given to the trigger flip-flop 48 in the reset state, and the trigger command is inverted and set. Then, the repeat display lamp 50 is turned on and a gate signal is given to the AND circuit 53.

In such a state, the end detection signal FINISH
Is generated, the automatic performance stop operation is executed as described above, and at the same time, an output signal is generated from the AND circuit 53.
It is supplied to 55 as a preset load signal LD.

Since the preset data of "100" is combined with the preset counter 55 by the binary information, the count data of the counter 55 is set to "100" by the preset command and the line of "4" of the decoder 56 is displayed. An output signal is generated. Therefore, the automatic performance mode is set again.

In this case, since the end detection signal FINISH is generated and the preset instruction is given to the preset counter 55 with a delay of one clock signal φ, the signal ADR from the OR circuit 63 causes the address generation circuits 25 and 26 to generate The reset operation is performed. Further, the signal from the OR circuit 64 advances the preset counter 55 to generate an output signal on the line "5" of the decoder 56.

Therefore, in the preset operation, the decoder 56
As the signal rises to the line "4", the stored data in the musical score data memories 21 and 22 are read again from the head address, and the automatic performance is repeated again.
In this repeat play mode, the repeat switch 39 is operated again to trigger the trigger flip-flop 48 of the mode control circuit 27.
It is ended by reversing and resetting.

That is, in such an automatic performance,
Based on the control data stored and set in the control register circuit 65, an automatic performance sound having a specified tone generation mode can be obtained.
The control register circuit 65 is capable of storing and setting control data recorded and set in an external storage device together with performance information such as melody and accompaniment sound. Is obtained.

However, in the actual automatic performance, it is required to change the tone generation effect such as tone color and effect, and to learn the relation between the musical composition and the tone generation aspect, it is optional. It is required to change and control the tone generation mode.

In such a case, it can be freely changed by operating the switch corresponding to the controlled object of the switch circuit group 66 installed on the panel surface. That is,
As shown in FIGS. 9 and 10, at the beginning of the start control, the control data obtained via the S / P conversion circuit 20 is stored and set. By operating switches such as 66a and 66b, the stored contents are changed, and an arbitrary musical tone generation mode is selectively set.

[0118]

As described above, according to the electronic musical instrument of the present invention, not only the model of automatic musical tone generation as a model but also the pattern of musical tone generation in manual performance can be set at the same time. It is possible to perform a manual performance that matches with. Therefore, when practicing the manual performance imitating the model performance, the musical sounds of the automatic performance side and the manual performance side always match, so that there is no discomfort and a more effective performance of the practice practice can be exhibited. Further, even when the control data is rewritten, the musical tone generation mode of both the automatic performance sound and the manual performance sound changes, so that a performance without discomfort is realized.

[Brief description of drawings]

FIG. 1 is a configuration diagram illustrating an electronic musical instrument according to an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram showing a part of a more detailed configuration of the electronic musical instrument of the above embodiment.

FIG. 3 is a circuit configuration diagram showing a portion following FIG.

FIG. 4 is a circuit configuration diagram showing a portion following FIG. 2 similarly.

FIG. 5 is a diagram for explaining a form of performance sound information used in the above apparatus.

6A and 6B are views for explaining a data format of a melody part and an accompaniment part which are respectively stored as score data.

FIG. 7 is an eye configuration diagram illustrating an address generation device of the above-described embodiment device.

FIG. 8 is a configuration diagram similarly illustrating a mode control circuit.

FIG. 9 is a circuit configuration diagram showing a part of a control data register.

FIG. 10 is a circuit configuration diagram showing another portion of the control data register.

[Explanation of symbols]

11 ... musical score, 12 ... recording part, 13 ... reader, 14 ... front data memory, 17 ... gate circuit, 18-20 ... S / P conversion circuit, 2
1, 22 ... Score data memory, 25, 26 ... Address generation circuit, 27 ... Mode control circuit, 28 ... Automatic performance sound forming circuit, 29
... accompaniment sound forming circuit, 30, 31 ... reading control circuit, 38 ... start switch, 39 ... repeat switch, 65 ... control register circuit, 66 ... switch circuit group, 67 ... rism pattern memory, 68 ... tempo oscillator, 69 ... Counter, 70 ... Rhythm sound source.

Claims (1)

[Claims] 1. Storage means for storing in advance musical tone control data for controlling the generation of musical tones together with musical note data representing a musical composition, reading means for reading the musical note data and musical tone control data from the storing means, and this reading means. Automatic musical tone forming means for forming an automatic musical tone signal based on the note data read from the musical instrument, control data storing means for storing the musical tone control data read from the reading means, and a musical operation for designating a pitch A manual musical tone forming means for forming a manual musical tone signal corresponding to a pitch designated by the musical performance operator, and an automatic musical playing musical tone signal based on the stored data stored in the control data storing means. Control means for controlling a tone generation mode of a manual tone signal, and a tone control for controlling the tone generation mode And a tone control data setting operator for setting data, wherein the stored data of the control data storage means can be rewritten and set according to the operation of the tone control data setting operator. An electronic musical instrument.