JPH08275508A - Voltage step-up dc-dc converter - Google Patents

Voltage step-up dc-dc converter

Info

Publication number
JPH08275508A
JPH08275508A JP7339195A JP7339195A JPH08275508A JP H08275508 A JPH08275508 A JP H08275508A JP 7339195 A JP7339195 A JP 7339195A JP 7339195 A JP7339195 A JP 7339195A JP H08275508 A JPH08275508 A JP H08275508A
Authority
JP
Japan
Prior art keywords
voltage
transformer
fet
mos
mosfet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7339195A
Other languages
Japanese (ja)
Inventor
Kiminori Matsuno
公則 松野
Katsuyoshi Fujii
克芳 藤井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7339195A priority Critical patent/JPH08275508A/en
Publication of JPH08275508A publication Critical patent/JPH08275508A/en
Pending legal-status Critical Current

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  • Dc-Dc Converters (AREA)

Abstract

PURPOSE: To suppress the reverse flowing of the current from a smoothing capacitor and to achieve high efficiency of a voltage step-up DC-DC converter circuit using a synchronous commutation technology. CONSTITUTION: When the first MOSFET (M1) is on, the second MOSFET (M2) is made off, and a primary winding 11 of a transformer T1 is conducted. Energy is stored in the transformer T1. Thereafter, the first MOSFET (M1) is turned off, and the second MOSFET (M2) is turned on. The voltage obtained by adding the voltage of a DC power supply 1 and the voltage caused by the counterelectromotive force of the primary winding 11 of the transformer T1 is outputted to a load 14 through the second MOSFET (M2). Furthermore, the gate voltage of the second MOSFET (M2) is formed by a resonance circuit comprising a secondary wiring 12 of the transformer T1, a resonance capacitor C2 and a resistor R1. Thus, the dead time, in which both MOSFETs become the OFF state during the ON period of the first MOSFET (M1) and the second MOSFET (M2), is formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、DC−DCコンバータ
に係り、特に同期整流技術を用いた昇圧型DC−DCコ
ンバータに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC-DC converter, and more particularly to a step-up DC-DC converter using a synchronous rectification technique.

【0002】[0002]

【従来の技術】従来、昇圧型DC−DCコンバータで
は、整流素子としてダイオードを用いて外部に電流を放
出するものがほとんどであった。一方、ダイオードでの
電力損失及び発熱の問題から整流素子としてスイッチン
グ素子を用いた昇圧型DC−DCコンバータがあった。
2. Description of the Related Art Conventionally, most step-up DC-DC converters use a diode as a rectifying element to discharge a current to the outside. On the other hand, there is a step-up DC-DC converter that uses a switching element as a rectifying element because of the problems of power loss and heat generation in the diode.

【0003】以下に、従来の整流素子としてスイッチン
グ素子を用いた昇圧型DC−DCコンバータについて説
明する。
A conventional step-up DC-DC converter using a switching element as a rectifying element will be described below.

【0004】図3は、従来の昇圧型DC−DCコンバー
タの構成を示すブロック図である。図3において、1は
直流電源、T1は変成器、11及び12は変成器T1の1
次及び2次巻き線、M1,M2は交互にオンオフするMO
S-FET、Rは抵抗、C1は平滑コンデンサである。直
流電源1の正極は変成器の1次巻き線11に接続されて
いる。1次巻き線11の負荷側は、2次巻き線12、M
OS-FET M1のドレイン、MOS-FET M2のソー
スに接続され、MOS-FET M2のドレインは平滑コ
ンデンサC1の一端および負荷14に接続される。変成
器T1の2次巻き線12は抵抗を介してMOS-FET
M2のゲートに接続される。
FIG. 3 is a block diagram showing the structure of a conventional step-up DC-DC converter. In FIG. 3, 1 is a DC power source, T1 is a transformer, and 11 and 12 are transformers T1.
MO that turns on and off the secondary and secondary windings, M1 and M2 alternately
S-FET, R is a resistor, and C1 is a smoothing capacitor. The positive electrode of the DC power supply 1 is connected to the primary winding 11 of the transformer. On the load side of the primary winding 11, the secondary winding 12, M
The drain of the OS-FET M1 and the source of the MOS-FET M2 are connected, and the drain of the MOS-FET M2 is connected to one end of the smoothing capacitor C1 and the load 14. The secondary winding 12 of the transformer T1 is a MOS-FET via a resistor.
Connected to the gate of M2.

【0005】制御部13からは、所定の周期の電圧がM
OS-FET M1のゲートに印加され、印加されている
ときにMOS-FET M1はオン状態となり、ドレイン
・ソース間は通電され1次巻き線11にエネルギーが蓄
えられる。MOS-FET M1がオン状態からオフ状態
になったときに、1次巻き線11の両端には逆起電力に
よる電圧が生じ、同時に2次巻き線12の両端には誘導
起電力による電圧が生じる。このとき、MOS-FET
M2のゲート電位はソース電位よりも高電位となり、M
OS-FET M2はオン状態となる。従って、MOS-F
ET M1がオフ状態のとき、直流電源1の電圧に前記逆
起電力による電圧が加算された電圧が、MOS-FET
M2を介して負荷14に出力され、同時にコンデンサC1
を充電する。
From the control unit 13, the voltage of a predetermined cycle is M
The MOS-FET M1 is applied to the gate of the OS-FET M1, and the MOS-FET M1 is turned on when the voltage is applied, and the drain-source is energized to store energy in the primary winding 11. When the MOS-FET M1 changes from the ON state to the OFF state, a voltage due to the counter electromotive force is generated at both ends of the primary winding 11, and a voltage due to the induced electromotive force is simultaneously generated at both ends of the secondary winding 12. . At this time, MOS-FET
The gate potential of M2 becomes higher than the source potential, and M2
The OS-FET M2 is turned on. Therefore, MOS-F
When the ETM1 is in the OFF state, the voltage obtained by adding the voltage due to the counter electromotive force to the voltage of the DC power supply 1 is the MOS-FET.
It is output to the load 14 via M2 and at the same time the capacitor C1
To charge.

【0006】逆に、MOS-FET M1がオフ状態から
オン状態になったとき、2次巻き線12の両端に誘導起
電力による電圧が生じMOS-FET M2のゲート電位
はソース電位よりも低電位となり、MOS-FET M2
はオフ状態となる。また、MOS-FET M1がオン状
態のときは、コンデンサC1の放電により負荷14に電
流が流れる。これによって、負荷14には直流電源1の
電圧以上の電圧が出力される。
On the contrary, when the MOS-FET M1 is changed from the off state to the on state, a voltage due to an induced electromotive force is generated at both ends of the secondary winding 12, and the gate potential of the MOS-FET M2 is lower than the source potential. And MOS-FET M2
Is turned off. When the MOS-FET M1 is in the ON state, the discharge of the capacitor C1 causes a current to flow in the load 14. As a result, a voltage higher than the voltage of the DC power supply 1 is output to the load 14.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、前述し
た従来の昇圧型DC−DCコンバータにおいては、MO
S-FET M1がオフからオンに切り替わるときに、制
御部13からのパルスによりMOS-FET M1がオン
した後でMOS-FET M2がオフすることになる。そ
のため、コンデンサC1からMOS-FET M2及びMO
S-FET M1を介して、直流電源1の負極に電流が流
れ込むことによる効率の低下を引き起こし、1つの制御
部13により2つのスイッチング素子(M1,M2)の制
御を行う上での問題点となっていた。
However, in the above-mentioned conventional step-up DC-DC converter, the MO
When the S-FET M1 is switched from off to on, the pulse from the control unit 13 turns on the MOS-FET M1 and then turns off the MOS-FET M2. Therefore, from the capacitor C1 to the MOS-FET M2 and MO
There is a problem in controlling the two switching elements (M1, M2) by one control unit 13 due to a decrease in efficiency caused by the current flowing into the negative electrode of the DC power supply 1 through the S-FET M1. Was becoming.

【0008】本発明は上記従来の問題点を解決するもの
で、平滑コンデンサからの電流の逆流を抑え、同期整流
技術を用いた昇圧型DC−DCコンバータ回路の高効率
化を目的とする。
The present invention solves the above-mentioned conventional problems, and an object thereof is to suppress the reverse flow of current from a smoothing capacitor and to improve the efficiency of a step-up DC-DC converter circuit using a synchronous rectification technique.

【0009】[0009]

【課題を解決するための手段】この目的を達成するため
に本発明の昇圧型DC−DCコンバータは、直流電源
と、直流電源の正極に1次巻き線が直列に接続されかつ
1次巻き線と磁気的に結合された2次巻き線を有する変
成器と、変成器の1次巻き線と直流電源の負極間に接続
された第1のスイッチング素子と、一端が直流電源1の
負極に接続された平滑コンデンサと、変成器の1次巻き
線と平滑コンデンサの他端の間に直列に接続された第2
のスイッチング素子と、変成器の2次巻き線と第2のス
イッチング素子のコントロール端子の間に接続された共
振用コンデンサと、第2のスイッチング素子のコントロ
ール端子と直流電源の負極との間に接続された抵抗と、
第1のスイッチング素子に所定の周期の電圧を印加する
制御部とにより構成されている。
In order to achieve this object, a step-up DC-DC converter according to the present invention comprises a DC power source, a primary winding connected in series to the positive electrode of the DC power source, and the primary winding. A transformer having a secondary winding magnetically coupled to the first winding, a first switching element connected between the primary winding of the transformer and a negative electrode of the DC power supply, and one end connected to a negative electrode of the DC power supply 1. Second smoothing capacitor connected in series between the primary winding of the transformer and the other end of the smoothing capacitor.
Switching element, a resonance capacitor connected between the secondary winding of the transformer and the control terminal of the second switching element, and connected between the control terminal of the second switching element and the negative electrode of the DC power supply. Resistance
And a control unit that applies a voltage of a predetermined cycle to the first switching element.

【0010】[0010]

【作用】本発明は上記の構成により、制御部から所定の
周期で電圧が第1のスイッチング素子のコントロール端
子に印加され、電圧がコントロール端子に印加されてい
るときに、第1のスイッチング素子はオン状態となり、
ドレイン・ソース間は通電され1次巻き線にエネルギー
が蓄えられる。第1のスイッチング素子がオン状態から
オフ状態になったときに、1次巻き線の両端には逆起電
力による電圧が生じ、同時に2次巻き線の両端には誘導
起電力による電圧が生じる。
According to the present invention, with the above configuration, the voltage is applied from the control unit to the control terminal of the first switching element at a predetermined cycle, and when the voltage is applied to the control terminal, the first switching element Is turned on,
The drain and source are energized and energy is stored in the primary winding. When the first switching element changes from the ON state to the OFF state, a voltage due to a back electromotive force is generated at both ends of the primary winding, and a voltage due to an induced electromotive force is simultaneously generated at both ends of the secondary winding.

【0011】このとき、2次巻き線と共振コンデンサお
よび抵抗との直列共振により、第2のスイッチング素子
のコントロール端子には誘導起電力による電圧と同位相
の正弦波状の共振電圧が印加される。第2のスイッチン
グ素子は、共振電圧がそのしきい値電圧とその時の出力
電圧を加算した電圧を越えた場合にオン状態となる。
At this time, due to the series resonance of the secondary winding, the resonance capacitor and the resistor, a sinusoidal resonance voltage having the same phase as the voltage due to the induced electromotive force is applied to the control terminal of the second switching element. The second switching element is turned on when the resonance voltage exceeds the sum of the threshold voltage and the output voltage at that time.

【0012】従って、第1のスイッチング素子がオフ状
態のとき、直流電源の電圧に逆起電力による電圧が加算
された電圧が、第2のスイッチング素子を介して負荷に
出力され、同時にコンデンサを充電する。また、第1の
スイッチング素子がオン状態のときは第2のスイッチン
グ素子はオフ状態であり、コンデンサの放電により負荷
に電流が流れる。これによって、負荷には直流電源の電
圧以上の電圧が出力でき、かつ第1のスイッチング素子
と第2のスイッチング素子のオン時間の間にデッドタイ
ムが作れるため平滑コンデンサからの電流の逆流を抑え
ることができる。
Therefore, when the first switching element is in the off state, the voltage obtained by adding the voltage due to the back electromotive force to the voltage of the DC power source is output to the load through the second switching element and simultaneously charges the capacitor. To do. Further, when the first switching element is in the on state, the second switching element is in the off state, and current flows through the load due to discharge of the capacitor. As a result, a voltage higher than the voltage of the DC power supply can be output to the load, and a dead time can be created between the ON times of the first switching element and the second switching element, so that the backflow of the current from the smoothing capacitor is suppressed. You can

【0013】更に、コントロール端子に、矩形波ハ゜ルス電
圧ではなく正弦波状の共振電圧を印加できるためソフト
スイッチングを実現できる。
Furthermore, since a sinusoidal resonance voltage, rather than a rectangular wave pulse voltage, can be applied to the control terminal, soft switching can be realized.

【0014】[0014]

【実施例】以下本発明の1実施例について図面を参照し
ながら説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

【0015】図1は本発明の実施例における昇圧型DC
−DCコンバータの構成を示すブロック図であり、図2
は2つのMOS-FETの動作タイミングを示す図であ
る。図1において、1は直流電源、T1は変成器、11
及び12は変成器T1の1次及び2次巻き線、M1,M2は
交互にオンオフするMOS-FET、R1は抵抗、C2は
共振コンデンサ、C1は平滑コンデンサである。直流電
源1の正極を変成器T1の1次巻き線11と2次の巻き
線12の一端に接続し、変成器T1の2次巻き線12の
他端を共振コンデンサC2を介して第2のMOS-FET
M2のゲートに接続し、変成器T1の1次巻き線11の
他端を第1のMOS-FET M1のドレインと第2のM
OS-FET M2のソースに接続し、制御部13は第1
のMOS-FETM1のゲートに接続されている。
FIG. 1 shows a step-up DC according to an embodiment of the present invention.
2 is a block diagram showing a configuration of a DC converter, and FIG.
FIG. 6 is a diagram showing operation timings of two MOS-FETs. In FIG. 1, 1 is a DC power supply, T1 is a transformer, and 11
Reference numerals 12 and 12 are primary and secondary windings of the transformer T1, M1 and M2 are MOS-FETs which are alternately turned on and off, R1 is a resistor, C2 is a resonance capacitor, and C1 is a smoothing capacitor. The positive electrode of the DC power supply 1 is connected to one ends of the primary winding 11 and the secondary winding 12 of the transformer T1, and the other end of the secondary winding 12 of the transformer T1 is connected to the second end via the resonance capacitor C2. MOS-FET
It is connected to the gate of M2 and the other end of the primary winding 11 of the transformer T1 is connected to the drain of the first MOS-FET M1 and the second M-FET M1.
Connected to the source of OS-FET M2, the control unit 13 is the first
Is connected to the gate of the MOS-FET M1.

【0016】以上のように構成された本実施例の昇圧型
DC−DCコンバータについて、以下その動作について
説明する。
The operation of the step-up DC-DC converter of the present embodiment having the above configuration will be described below.

【0017】制御部13から所定の周期の電圧が第1の
MOS−FET M1のゲートに印加され、電圧がゲート
に印加されているときに第1のMOS−FET M1はオ
ン状態となり、ドレイン・ソース間は通電され変成器T
1の1次巻き線11にエネルギーが蓄えられる。第1の
MOS−FET M1がオン状態からオフ状態になったと
きに、変成器T1の1次巻き線11の両端には逆起電力
による電圧が生じ、同時に変成器T1の2次巻き線12
の両端には誘導起電力による電圧が生じる。このとき、
変成器T1の2次巻き線12と共振コンデンサC2および
抵抗R1との直列共振により、第2のMOS-FET M2
のゲートには誘導起電力による電圧と同位相の正弦波状
の共振電圧が印加される。第2のMOS-FET M2
は、共振電圧がそのしきい値電圧と出力電圧を加算した
電圧を越えた場合にオン状態となる。従って、第1のM
OS−FET M1がオフ状態のとき、直流電源の電圧に
逆起電力による電圧が加算された電圧が、第2のMOS
-FETM2を介して負荷14に出力され、同時に平滑コ
ンデンサC1を充電する。また、第1のMOS−FET
M1がオン状態のときは、第2のMOS-FET M2はオ
フ状態となり平滑コンデンサC1の放電により負荷14
に電流が流れる。
A voltage of a predetermined cycle is applied to the gate of the first MOS-FET M1 from the control unit 13, and when the voltage is applied to the gate, the first MOS-FET M1 is turned on and the drain A transformer T is energized between the sources
Energy is stored in the primary winding 11 of 1. When the first MOS-FET M1 is switched from the ON state to the OFF state, a voltage due to the counter electromotive force is generated across the primary winding 11 of the transformer T1, and at the same time, the secondary winding 12 of the transformer T1 is generated.
A voltage due to the induced electromotive force is generated at both ends of. At this time,
Due to the series resonance of the secondary winding 12 of the transformer T1, the resonance capacitor C2 and the resistor R1, the second MOS-FET M2
A sinusoidal resonance voltage having the same phase as the voltage due to the induced electromotive force is applied to the gate of the. Second MOS-FET M2
Turns on when the resonance voltage exceeds a voltage obtained by adding the threshold voltage and the output voltage. Therefore, the first M
When the OS-FET M1 is in the off state, the voltage obtained by adding the voltage due to the back electromotive force to the voltage of the DC power supply is the second MOS.
-It is output to the load 14 through the FET M2 and simultaneously charges the smoothing capacitor C1. Also, the first MOS-FET
When M1 is on, the second MOS-FET M2 is off and the smoothing capacitor C1 is discharged to load 14
Current flows through.

【0018】図2において、(a)は第1のMOS-F
ET M1の動作タイミングを示している。同様に、
(b)は第2のMOS-FET M2の動作タイミングを
示している。(c)は第2のMOS-FET M2のゲー
トに印加される電圧波形を示したものであり、前述した
ように変成器T1の2次巻き線12のインダクタンス成
分、共振コンデンサC2、抵抗R1の直列共振による共振
電圧波形となる。(a)に示す第1のMOS-FET M
1のオン・オフ動作により(c)に示す共振電圧波形が
生じる。(c)に示す共振電圧波形が第2のMOS-F
ET M2の出力電圧Vdにしきい値電圧VTを加算した電
圧以上になる期間では、(b)に示すように第2のMO
S-FETはオンの状態となり、それ以外の期間はオフ
状態となる。よって、図2(a)、(b)から判るよう
に、第1のMOS-FET M1と第2のMOS-FET
M2のオン期間の間に両MOS-FET共オフ状態となる
デッドタイムを作れ、平滑コンデンサC1からの電流の
逆流を抑えることができる。
In FIG. 2, (a) shows the first MOS-F.
The operation timing of ETM1 is shown. Similarly,
(B) shows the operation timing of the second MOS-FET M2. (C) shows a voltage waveform applied to the gate of the second MOS-FET M2. As described above, the inductance component of the secondary winding 12 of the transformer T1, the resonance capacitor C2, and the resistance R1 A resonance voltage waveform due to series resonance is obtained. The first MOS-FET M shown in (a)
The on / off operation of 1 produces the resonance voltage waveform shown in (c). The resonance voltage waveform shown in (c) is the second MOS-F.
During the period in which the output voltage Vd of the ETM2 is equal to or higher than the threshold voltage VT, as shown in FIG.
The S-FET is in the on state, and is in the off state in other periods. Therefore, as can be seen from FIGS. 2A and 2B, the first MOS-FET M1 and the second MOS-FET M1
A dead time in which both MOS-FETs are in the OFF state can be created during the ON period of M2, and the backflow of the current from the smoothing capacitor C1 can be suppressed.

【0019】更に、MOS-FET M2のゲート電圧を
従来の矩形波ハ゜ルス電圧ではなく、正弦波状の共振電圧と
することにより、MOS−FET M2のソフトスイッチ
ングが可能なためサージ電圧の発生を抑えることがで
き、ノイズの発生を低減することができる。
Further, by making the gate voltage of the MOS-FET M2 not a conventional square wave pulse voltage but a sinusoidal resonance voltage, soft switching of the MOS-FET M2 is possible, so that generation of surge voltage is suppressed. Therefore, the generation of noise can be reduced.

【0020】以上のように本発明の実施例によれば、2
つのMOS-FETのうちの1つに制御信号を与えるこ
とにより2つのMOS-FETの動作タイミングを取る
ための変成器を設け、更に平滑コンデンサからの電流の
逆流を抑えるために整流素子として使用するMOS-F
ETのゲート電圧を共振させる直列共振手段を設けて、
1つの制御部による2つのMOS-FETの制御を可能
にし、回路の低ノイズ化と高効率化を実現することにな
る。
As described above, according to the embodiment of the present invention, 2
A transformer is provided to control the operation timing of two MOS-FETs by giving a control signal to one of the two MOS-FETs, and is used as a rectifying element to suppress the reverse current of the current from the smoothing capacitor. MOS-F
By providing a series resonance means for resonating the gate voltage of ET,
This makes it possible to control two MOS-FETs by one control unit, thereby realizing low noise and high efficiency of the circuit.

【0021】[0021]

【発明の効果】以上のように本発明は、第1のスイッチ
素子がオンのとき第2のスイッチ素子をオフにして変成
器の1次巻き線を通電させ、変成器にエネルギーを蓄え
る。その後、第1のスイッチ素子をオフにし第2のスイ
ッチ素子をオンにして、直流電源の電圧と変成器の1次
巻き線の逆起電力による電圧とを加算した電圧を第2の
スイッチ素子を介して負荷に出力する。また、第2のス
イッチ素子のゲート電圧を変成器の2次巻き線、共振用
コンデンサ、および抵抗からなる共振回路により生成す
ることにより、第1のスイッチ素子と第2のスイッチ素
子のオン期間の間に両スイッチ素子共にオフ状態となる
デッドタイムが作れ、1つの制御部により2つのスイッ
チング素子の動作を行う場合に問題となる平滑コンデン
サからの電流の逆流を抑えることができるため、同期整
流技術を用いた低ノイズでかつ高効率の昇圧型DC−D
Cコンバータが実現できる。
As described above, according to the present invention, when the first switch element is on, the second switch element is off and the primary winding of the transformer is energized to store energy in the transformer. After that, the first switch element is turned off and the second switch element is turned on, and the voltage obtained by adding the voltage of the DC power supply and the voltage due to the counter electromotive force of the primary winding of the transformer is set to the second switch element. Output to the load via. Further, the gate voltage of the second switch element is generated by the resonant circuit including the secondary winding of the transformer, the resonance capacitor, and the resistor, so that the ON period of the first switch element and the second switch element is reduced. Since a dead time in which both switching elements are turned off is created between them, it is possible to suppress the backflow of the current from the smoothing capacitor, which is a problem when operating two switching elements with one control unit. DC-D with low noise and high efficiency using DC
A C converter can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例における昇圧型DC−DCコン
バータの構成を示すブロック図
FIG. 1 is a block diagram showing the configuration of a step-up DC-DC converter according to an embodiment of the present invention.

【図2】本発明の実施例におけるスイッチ動作のタイミ
ングを示す図
FIG. 2 is a diagram showing a timing of a switch operation in the embodiment of the present invention.

【図3】従来の昇圧型DC−DCコンバータの構成を示
すブロック図
FIG. 3 is a block diagram showing a configuration of a conventional step-up DC-DC converter.

【符号の説明】[Explanation of symbols]

1 直流電源 11 1次巻き線 12 2次巻き線 13 制御部 14 負荷 C1 平滑コンデンサ C2 共振コンデンサ M1,M2 MOS-FET R1 共振用抵抗 T1 変成器 VT MOS-FET M2のしきい値電圧 Vd 出力電圧 1 DC power supply 11 Primary winding 12 Secondary winding 13 Control section 14 Load C1 Smoothing capacitor C2 Resonance capacitor M1, M2 MOS-FET R1 Resonance resistor T1 Transformer VT MOS-FET M2 threshold voltage Vd Output voltage

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 直流電源と、前記直流電源の正極に1次
巻き線が直列に接続されかつ1次巻き線と磁気的に結合
された2次巻き線を有する変成器と、前記変成器の1次
巻き線と前記直流電源の負極間に接続された第1のスイ
ッチング素子と、一端が前記直流電源1の負極に接続さ
れた平滑コンデンサと、前記変成器の1次巻き線と平滑
コンデンサの他端の間に直列に接続された第2のスイッ
チング素子と、前記変成器の2次巻き線と前記第2のス
イッチング素子のコントロール端子の間に接続された共
振用コンデンサと、前記第2のスイッチング素子のコン
トロール端子と前記直流電源の負極との間に接続された
抵抗と、前記第1のスイッチング素子のコントロール端
子に所定の周期の電圧を印加する制御部とを備えた昇圧
型DC−DCコンバータ。
1. A transformer having a DC power source, a secondary winding in which a primary winding is connected in series to a positive electrode of the DC power source, and the secondary winding is magnetically coupled to the primary winding; A first switching element connected between the primary winding and the negative electrode of the DC power supply; a smoothing capacitor having one end connected to the negative electrode of the DC power supply 1; a primary winding of the transformer and a smoothing capacitor; A second switching element connected in series between the other ends, a resonance capacitor connected between the secondary winding of the transformer and a control terminal of the second switching element, and the second switching element. Step-up DC-DC including a resistor connected between the control terminal of the switching element and the negative electrode of the DC power supply, and a control unit that applies a voltage of a predetermined cycle to the control terminal of the first switching element Comba Data.
JP7339195A 1995-03-30 1995-03-30 Voltage step-up dc-dc converter Pending JPH08275508A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7339195A JPH08275508A (en) 1995-03-30 1995-03-30 Voltage step-up dc-dc converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7339195A JPH08275508A (en) 1995-03-30 1995-03-30 Voltage step-up dc-dc converter

Publications (1)

Publication Number Publication Date
JPH08275508A true JPH08275508A (en) 1996-10-18

Family

ID=13516858

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7339195A Pending JPH08275508A (en) 1995-03-30 1995-03-30 Voltage step-up dc-dc converter

Country Status (1)

Country Link
JP (1) JPH08275508A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0891038A4 (en) * 1996-11-13 2001-05-02 Seiko Epson Corp Power supply device and portable electronic equipment
US7285941B2 (en) 2004-03-26 2007-10-23 Samsung Electronics Co., Ltd. DC-DC converter with load intensity control method
JP2010200390A (en) * 2009-02-23 2010-09-09 Toyota Motor Corp Synchronous rectification type dc-dc converter
JP2011139563A (en) * 2009-12-28 2011-07-14 Mitsubishi Electric Corp Power supply device
JP2011151913A (en) * 2010-01-20 2011-08-04 Mitsubishi Electric Corp Power supply circuit and lighting device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0891038A4 (en) * 1996-11-13 2001-05-02 Seiko Epson Corp Power supply device and portable electronic equipment
US6421261B1 (en) 1996-11-13 2002-07-16 Seiko Epson Corporation Power supply apparatus with unidirectional units
US7285941B2 (en) 2004-03-26 2007-10-23 Samsung Electronics Co., Ltd. DC-DC converter with load intensity control method
JP2010200390A (en) * 2009-02-23 2010-09-09 Toyota Motor Corp Synchronous rectification type dc-dc converter
JP2011139563A (en) * 2009-12-28 2011-07-14 Mitsubishi Electric Corp Power supply device
JP2011151913A (en) * 2010-01-20 2011-08-04 Mitsubishi Electric Corp Power supply circuit and lighting device

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