JPH10225114A - Synchronous rectifier circuit - Google Patents

Synchronous rectifier circuit

Info

Publication number
JPH10225114A
JPH10225114A JP3844497A JP3844497A JPH10225114A JP H10225114 A JPH10225114 A JP H10225114A JP 3844497 A JP3844497 A JP 3844497A JP 3844497 A JP3844497 A JP 3844497A JP H10225114 A JPH10225114 A JP H10225114A
Authority
JP
Japan
Prior art keywords
mosfet
circuit
transformer
synchronous rectifier
commutation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3844497A
Other languages
Japanese (ja)
Other versions
JP3515675B2 (en
Inventor
Kiichi Tanaka
僖一 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP03844497A priority Critical patent/JP3515675B2/en
Publication of JPH10225114A publication Critical patent/JPH10225114A/en
Application granted granted Critical
Publication of JP3515675B2 publication Critical patent/JP3515675B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To avoid a short-circuit current, caused by the operation delay of a MOSFET in the secondary side of a transformer, by providing a control (discharging) circuit separately for switching off a commutating MOSFET and to prevent the decline of efficiency by making it possible to turn on the MOSFET over the total range of the commutation interval, which is a merit of the original choke coil driving system. SOLUTION: This circuit is a synchronous rectifier circuit of a converter, in which rectifying MOSFET 4 and commutating MOSFET 6 are connected to the secondary coil 2B of a transformer in a voltage converter circuit and which filters the output with a choke coil 8 and an output capacitor 9. The drive circuit 11 for turning on the commutating MOSFET 6 and a control (discharging) circuit 13 for turning it off are provided. The drive circuit 11 is made up of the auxiliary windings 8B of the choke coil 8 with one end connected to the source of the MOSFET 6 and a diode 12. The control circuit 13 contains at least a control switch 14, which operates synchronized with a main switching element 3, and its other end is connected to the drain of the commutating MOSFET 4.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は絶縁型一石フォワード型
コンバータに関するもので特に2次側にMO (2) SFETを使用した同期整流回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated one-stone forward converter, and more particularly to a synchronous rectifier circuit using an MO (2) SFET on the secondary side.

【0002】[0002]

【従来の技術】DC−DCコンバータ等の電圧変換装置
において、整流ダイオードをMOSFETに置き換えた
同期整流回路は、導通状態での電圧降下が低減出来るた
め回路の効率を向上できる利点がある。図6は同期整流
回路を用いた一石フォワードコンバータの従来例であ
る。3は主スイッチ素子、2はトランス、4は整流用M
OSFET、6は転流用MOSFET、8はチョークコ
イル、1は入力コンデンサ、9は出力コンデンサであ
る。整流及び転流用MOSFET4と6にはそれぞれ内
蔵されている寄生ダイオードを5及び7で図示されてい
る。
2. Description of the Related Art In a voltage converter such as a DC-DC converter, a synchronous rectifier circuit in which a rectifier diode is replaced with a MOSFET has an advantage that the voltage drop in a conductive state can be reduced and the efficiency of the circuit can be improved. FIG. 6 shows a conventional example of a one-stone forward converter using a synchronous rectifier circuit. 3 is a main switch element, 2 is a transformer, 4 is M for rectification.
OSFET, 6 is a commutation MOSFET, 8 is a choke coil, 1 is an input capacitor, and 9 is an output capacitor. Parasitic diodes incorporated in the rectification and commutation MOSFETs 4 and 6 are indicated by reference numerals 5 and 7, respectively.

【0003】図7は図6の同期整流回路のタイムチャー
トで、1次側の主スイッチ素子3の導通期間(t1)に
はトランス2を経由して、1次側の入力コンデンサ1か
ら出力コンデンサ9へ電力が伝送される。このときトラ
ンス2の2次巻線に発生した電圧が整流用MOSFET
4を導通させ、チョークコイル8に電磁エネルギーを蓄
積しながら出力コンデンサ9に所定の出力電圧を発生さ
せる。次に主スイッチ素子3が遮断されると、トランス
に蓄えられた励磁エネルギーは主スイッチ素子3の出力
容量、転流用MOSFET6の入力容量等の間で共振電
圧が発生する。
FIG. 7 is a time chart of the synchronous rectifier circuit shown in FIG. 6 during the conduction period (t1) of the primary side main switch element 3 via the transformer 2 from the primary side input capacitor 1 to the output capacitor. Power is transmitted to 9. At this time, the voltage generated in the secondary winding of the transformer 2 is a rectifying MOSFET.
4 is made conductive, and a predetermined output voltage is generated in the output capacitor 9 while storing electromagnetic energy in the choke coil 8. Next, when the main switch element 3 is cut off, the excitation energy stored in the transformer generates a resonance voltage between the output capacity of the main switch element 3, the input capacity of the commutation MOSFET 6, and the like.

【0004】この共振電圧によって、転流用MOSFE
T6は導通し、同時に整流用MOSFET4は遮断す
る。この動作によりチョークコイル8に蓄積されていた
電磁エネルギーは転流用MOSFET6を経由して出力
コンデンサ9に放出される。 (3) しかし共振電圧は期間t2で終了してしまい、なおかつ
共振電圧が交流電圧であるために転流用MOSFET6
が導通出来る期間は共振電圧が転流用MOSFET6の
ゲートスレショールド電圧Vth以上となる△t2の期間
のみで、残りの△t1,△t3及びt3の期間は転流用M
OSFET6は遮断され、チョーク コイル8に残った
上記電磁エネルギーは寄生ダイオード7を通って出力コ
ンデンサ9に放出される。
The commutation MOSFE is generated by the resonance voltage.
T6 conducts, and at the same time, the rectifying MOSFET 4 shuts off. With this operation, the electromagnetic energy stored in the choke coil 8 is released to the output capacitor 9 via the commutation MOSFET 6. (3) However, since the resonance voltage ends in the period t2 and the resonance voltage is an AC voltage, the commutation MOSFET 6
Can be conducted only during the period of Δt2 at which the resonance voltage becomes equal to or higher than the gate threshold voltage Vth of the MOSFET 6 for commutation, and during the remaining periods of Δt1, Δt3 and t3, the M
The OSFET 6 is cut off, and the electromagnetic energy remaining in the choke coil 8 is discharged to the output capacitor 9 through the parasitic diode 7.

【0005】上述のようにこの回路は主スイッチ素子3
の遮断期間にチョークコイル8の上記電磁エネルギーを
放出する転流用MOSFET6の導通期間が、上記共振
電圧の発生期間の一部△t2だけであり、残りの上記電
磁エネルギーはそれ以外の期間△t1と△t3+t3に転
流用MOSFET6の寄生ダイオード7を経由して放出
されるため、上記ダイオードの順方向電圧VFによる電
力損失が大きい。
As described above, this circuit includes the main switch element 3
During the cutoff period, the conduction period of the commutation MOSFET 6 that emits the electromagnetic energy of the choke coil 8 is only a part Δt2 of the generation period of the resonance voltage, and the remaining electromagnetic energy is the other period Δt1. At Δt 3 + t 3, the power is released via the parasitic diode 7 of the MOSFET 6 for commutation, so that the power loss due to the forward voltage VF of the diode is large.

【0006】上記欠点を改善する従来の技術の第2の例
を図8に示す。この従来例は特開昭55−66281で
明らかにされている如く、上述の第1の従来の同期整流
回路の諸要素に対して転流用MOSFET6のゲートが
チョークコイル8に設けられた補助巻線8Bによって駆
動される。なお図8においては整流MOSFETとして
P型MOSを使っているので、回路構成が図6と若干異
なるが、機能は変わらないので同一機能部分は同一符号
を付してある。
FIG. 8 shows a second example of the prior art for improving the above-mentioned disadvantage. As disclosed in Japanese Patent Application Laid-Open No. 55-66281, this conventional example has an auxiliary winding in which a gate of a commutation MOSFET 6 is provided in a choke coil 8 with respect to the elements of the first conventional synchronous rectifier circuit described above. 8B. In FIG. 8, since a P-type MOS is used as the rectifying MOSFET, the circuit configuration is slightly different from that of FIG. 6, but the function is not changed.

【0007】チョークコイル8には図7(e)に示され
ている如く、主スイッチ素子3のオン/オフ動作に連動
して正又は負の電圧を発生するので、この電圧波形を極
性反転すると転流用MOSFET6をドライブするのに
最適な短形波のスイッチング波形が得られる。更に図8
の方法によればトランスのリセット時の共振電圧を利用
しないので、図7に示す様な転流用MOSFET6のオ
ン時にゲートスレショールドに達する迄の遅れ時間△t
1が無くなるので、この分ダイオードに流すことによる
ロスが (4) 少なくなること、及びトランスの励磁インダクタンスと
回路の寄生容量によって決まる共振電圧の周期t2が転
流用MOSFET6の入力容量分減るので短く出来る利
点がある。これにより変換周波数を上げることが可能
で、より小型化が達成出来るメリットがある。
As shown in FIG. 7 (e), a positive or negative voltage is generated in the choke coil 8 in conjunction with the on / off operation of the main switch element 3. A switching waveform of a square wave optimal for driving the commutation MOSFET 6 is obtained. Further FIG.
According to the method described above, since the resonance voltage at the time of resetting the transformer is not used, the delay time Δt until the gate threshold is reached when the commutation MOSFET 6 is turned on as shown in FIG.
Since 1 is eliminated, the loss caused by flowing through the diode is reduced by (4), and the period t2 of the resonance voltage determined by the exciting inductance of the transformer and the parasitic capacitance of the circuit is reduced by the input capacitance of the MOSFET 6 for commutation. There are advantages. As a result, there is an advantage that the conversion frequency can be increased and the size can be further reduced.

【0008】上述した従来の同期整流回路で図8の回路
例は主スイッチ素子3のオフしている全期間(t2+t
3)に亘って転流用MOSFETを導通でき、なおかつ
共振周期を短かくできる等の利点があるが、この方式で
も以下に述べる不具合のため実際にはほとんど使われて
いない。第1はチョークコイル8の補助巻線8Bに発生
する電圧が正から負に変化するため、電圧の変化中△V
Lが大きく、これによる転流用MOSFET6の駆動ロ
スはC(△VL)2fとなるので、正から0迄の変化に比
べるとロスは4倍近く多くなる。
In the above-described conventional synchronous rectifier circuit shown in FIG. 8, the circuit example shown in FIG.
Although there is an advantage that the commutation MOSFET can be conducted for 3) and the resonance cycle can be shortened, this method is practically hardly used because of the following problems. First, since the voltage generated in the auxiliary winding 8B of the choke coil 8 changes from positive to negative, ΔV during the voltage change
Since L is large and the driving loss of the commutation MOSFET 6 due to this is C (△ VL) 2 f, the loss is nearly four times greater than the change from positive to zero.

【0009】第2は主スイッチ素子3がオンとなり転流
用MOSFET6がオフする時、そのゲート電荷をチョ
ークコイル8の補助巻線8Bを経由してソース側に流す
と、転流用MOSFET6のターンオフ時間tOFFのた
めに遅れが生じ、前記MOSFET6はすぐにはオフで
きない。しかし電流用MOSFET4又はダイオード5
には直ちに電流が流れるので、ほぼtOFF時間の間、転
流用MOSFET6と整流用MOSFET4又はダイオ
ード5を通ってトランス2次を短絡する電流が流れ、過
大なロスが発生する。この時、過電流保護機能等を備え
たDC−DCコンバータでは、保護機能が働いて、正常
に動作出来なくなる恐れがある。
Secondly, when the main switch element 3 is turned on and the commutation MOSFET 6 is turned off, the gate charge is passed to the source side via the auxiliary winding 8B of the choke coil 8, and the turn-off time tOFF of the commutation MOSFET 6 is turned off. Therefore, a delay occurs, and the MOSFET 6 cannot be turned off immediately. However, current MOSFET 4 or diode 5
, A current short-circuiting the secondary of the transformer flows through the commutation MOSFET 6 and the rectification MOSFET 4 or the diode 5 for approximately tOFF time, and an excessive loss occurs. At this time, in a DC-DC converter having an overcurrent protection function or the like, the protection function may be activated and may not be able to operate normally.

【0010】[0010]

【発明の目的】本発明はこれらの不具合を解決し、更に
効率の高い一石フォワードコンバータを提供することを
目的とする。 (5)
SUMMARY OF THE INVENTION It is an object of the present invention to solve these problems and to provide a more efficient one-stone forward converter. (5)

【0011】[0011]

【課題を解決するための手段】上記目的を達成するため
に本発明は少なくとも第1の巻線および第2の巻線を有
するトランスの第1の巻線に主スイッチ素子及びその駆
動回路を接続し、第2の巻線に整流用素子、転流用素子
および出力フィルタとしてチョークコイルとコンデンサ
を接続し、前記整流用素子と転流用素子としてMOSF
ETを使用し、前記主スイッチ素子のオン/オフにより
前記トランスに発生する電圧により前記MOSFETを
オン/オフさせるようにした一石フォワードコンバータ
において、前記転流用素子に対してはこれをオンするた
めの駆動回路と、オフするための制御(放電)回路を別
々に設けて、駆動回路は前記チョークコイルに付加され
た補助巻線からダイオードを経由して転流用素子にオン
信号を加え、制御回路は主スイッチ素子に同期して動作
する制御スイッチを介して整流用素子とトランス2次巻
線との接続点に接続して、転流用素子をオフする手段を
設けたことを特徴とするものである。
In order to achieve the above object, the present invention connects a main switch element and a drive circuit thereof to a first winding of a transformer having at least a first winding and a second winding. A choke coil and a capacitor are connected to the second winding as a rectifying element, a commutating element and an output filter, and a MOSF is used as the rectifying element and the commutating element.
In a one-piece forward converter using an ET and turning on / off the MOSFET by a voltage generated in the transformer by turning on / off the main switch element, it is necessary to turn on the commutation element. A drive circuit and a control (discharge) circuit for turning off are separately provided, and the drive circuit applies an on signal to a commutation element via a diode from an auxiliary winding added to the choke coil. A means is provided for connecting to a connection point between the rectifying element and the secondary winding of the transformer via a control switch operating in synchronization with the main switching element to turn off the commutating element. .

【0012】[0012]

【作用】上記手段により本発明は転流用MOSFETの
ゲートの駆動エネルギーとしてチョークコイルの励磁エ
ネルギーを利用すると共に、制御(放電)手段として制
御スイッチを使って、ゲート電荷を強制的に放電するこ
とにより転流用MOSFET起因する短絡電流を押さえ
ることが出来る。
According to the present invention, the present invention utilizes the excitation energy of the choke coil as the driving energy of the gate of the commutation MOSFET, and forcibly discharges the gate charge using the control switch as the control (discharge) means. Short circuit current caused by the commutation MOSFET can be suppressed.

【0013】[0013]

【実施例】次に本発明について図面を参照して説明す
る。図1は本発明によるフォワードコンバータのMOS
FET同期整流回路の第1の実施例を示す回路図であ
る。2つのMOSFET4、6のソースが共通である直
列回路をMOSFET4、6のドレインが接続されるよ
うに主トランスの2次巻線2Bと並列に接続し、転流用
MOSFET6のドレインとソース間に出力コンデンサ
9とチョークコイル (6) 8から構成される出力フィルタ回路を接続する。転流用
FET6のゲートには、このFET6をオンするための
駆動回路11とオフするための制御(放電)回路13を
接続する。駆動回路11はチョークコイル8に巻かれた
補助巻線8Bとダイオード12を図示した極性で接続す
る。制御回路13は主スイッチ素子3に同期して動作す
る制御スイッチ14を有し、他端は転流用MOSFET
6のソースに接続される。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 shows a MOS of a forward converter according to the present invention.
FIG. 2 is a circuit diagram showing a first embodiment of the FET synchronous rectifier circuit. A series circuit in which the sources of the two MOSFETs 4 and 6 are common is connected in parallel with the secondary winding 2B of the main transformer so that the drains of the MOSFETs 4 and 6 are connected, and an output capacitor is connected between the drain and the source of the MOSFET 6 for commutation. 9 and a choke coil (6) An output filter circuit composed of 8 is connected. A drive circuit 11 for turning on the FET 6 and a control (discharge) circuit 13 for turning off the FET 6 are connected to the gate of the FET 6 for commutation. The drive circuit 11 connects the auxiliary winding 8B wound around the choke coil 8 to the diode 12 with the polarity shown. The control circuit 13 has a control switch 14 that operates in synchronization with the main switch element 3, and the other end is a commutation MOSFET
6 sources.

【0014】次に上記第1の実施例回路の動作を図2を
用いて説明する。主スイッチ素子3がオンからオフに移
行すると、トランス2には共振電圧がt’2の期間発生
する。この期間t’2は転流用MOSFET6の入力容
量Cissが寄与しないため、図7に示した共振電圧発
生期間t2よりも小さい。主スイッチ素子がオフしてい
る期間(t’2+t’3)にチョークコイル8の補助巻線
8Bに発生した電圧により、転流用MOSFET6が導
通するので、チョークコイルに蓄積された電磁エネルギ
ーは前記FET6を通って出力コンデンサ9に放出され
る。次に主スイッチ素子3がオフからオンに移行する
と、直ちに制御スイッチ14がオンして転流用MOSF
ET6のゲート電荷を急速に放電することが出来る。
Next, the operation of the circuit of the first embodiment will be described with reference to FIG. When the main switch element 3 shifts from on to off, a resonance voltage is generated in the transformer 2 for a period of t'2. This period t′2 is smaller than the resonance voltage generation period t2 shown in FIG. 7 because the input capacitance Ciss of the commutation MOSFET 6 does not contribute. Since the commutation MOSFET 6 is turned on by the voltage generated in the auxiliary winding 8B of the choke coil 8 during the period (t'2 + t'3) when the main switch element is off, the electromagnetic energy accumulated in the choke coil is reduced by the FET6. Through the output capacitor 9. Next, when the main switch element 3 shifts from off to on, the control switch 14 is immediately turned on and the commutating MOSF is turned on.
The gate charge of ET6 can be rapidly discharged.

【0015】このとき整流用MOSFET4又はダイオ
ード5は転流用MOSFET6のゲート電荷が残ってい
る間は電流が流れられないので、転流用MOSFET6
と、整流用MOSFET4又はダイオード5が同時にオ
ンして短絡電流を流すことはない。従って図1の実施例
回路では転流用MOSFET6のゲートをチョークコイ
ル8の補助巻線2Bの電圧で駆動しているにもかかわら
ず、転流用MOSFET6のオフ時に発生する過大なロ
スを防ぐことができ、且つダイオード12によって負電
圧が前記MOSFETのゲートにかかるのを防止してい
るので転流用MOS (7) FET6を最適な電圧で駆動出来る。
At this time, no current flows through the commutation MOSFET 4 or the diode 5 while the gate charge of the commutation MOSFET 6 remains, so that the commutation MOSFET 6
Then, the rectifying MOSFET 4 or the diode 5 does not turn on at the same time and a short-circuit current flows. Therefore, in the circuit of the embodiment shown in FIG. 1, even though the gate of the commutation MOSFET 6 is driven by the voltage of the auxiliary winding 2B of the choke coil 8, excessive loss that occurs when the commutation MOSFET 6 is turned off can be prevented. In addition, since the diode 12 prevents a negative voltage from being applied to the gate of the MOSFET, the commutation MOS (7) FET 6 can be driven at an optimum voltage.

【0016】図3は図1の実施例のうち制御回路13を
具体的な回路で表現した本発明の第2の実施例であっ
て、15は制御用FET、16は前記制御用FET15
の寄生ダイオード(図示していない)を流れる電流を阻
止するためのダイオードである。制御用FET15は主
スイッチ素子3のオン動作に同期してオンする様に接が
れているので、同時に転流用MOSFET6のゲート電
荷を放電し、オフさせる。本実施例ではトランスのリセ
ット期間に転流用MOSFET6の入力容量Cissの
影響が無くなったことにより、共振電圧の発生期間は短
かくなったが、代って制御FET15の入力容量がトラ
ンス2次巻線間に並列に接続されるので、この分若干発
生期間が延びてしまうことになる。
FIG. 3 shows a second embodiment of the present invention in which the control circuit 13 of the embodiment of FIG. 1 is represented by a specific circuit. Reference numeral 15 denotes a control FET, and 16 denotes the control FET 15.
Is a diode for blocking a current flowing through a parasitic diode (not shown). Since the control FET 15 is connected so as to be turned on in synchronization with the on operation of the main switch element 3, it simultaneously discharges the gate charge of the commutation MOSFET 6 and turns it off. In this embodiment, the influence of the input capacitance Ciss of the commutation MOSFET 6 is eliminated during the reset period of the transformer, so that the period of generation of the resonance voltage is shortened. However, the input capacitance of the control FET 15 is replaced by the transformer secondary winding. Since they are connected in parallel, the generation period is slightly extended by that much.

【0017】図4は本発明の第3の実施例であって17
はコンデンサ、18は抵抗である。トランスの2次巻線
2B間にコンデンサ17と抵抗18の直列回路を設置
し、その中点から制御FET15のゲート信号を得るこ
とによって、トランスからみた制御FETの入力容量分
を小さくすることが出来る。
FIG. 4 shows a third embodiment of the present invention.
Is a capacitor, and 18 is a resistor. By installing a series circuit of a capacitor 17 and a resistor 18 between the secondary windings 2B of the transformer and obtaining the gate signal of the control FET 15 from the middle point, the input capacitance of the control FET viewed from the transformer can be reduced. .

【0018】図5は本発明の第4の実施例であって、主
スイッチ素子にMOSFETを使った時の具体的回路例
である。20は主スイッチ素子としてのMOSFET、
21はコンデンサ、22はパルストランス、23はMO
SFETの駆動信号源である。制御FET15のゲート
信号を、パルストランス22とコンデンサ21を経由し
てMOSFETの駆動信号源から供給することにより、
トランス2の共振電圧発生期間は転流用FET6及び制
御FET15の入力容量の影響を全く受けないので、変
換周波数より高周波化が可能である。 (8)
FIG. 5 shows a fourth embodiment of the present invention, which is a specific circuit example when a MOSFET is used as a main switch element. 20 is a MOSFET as a main switch element,
21 is a capacitor, 22 is a pulse transformer, 23 is MO
This is a drive signal source for the SFET. By supplying the gate signal of the control FET 15 from the drive signal source of the MOSFET via the pulse transformer 22 and the capacitor 21,
Since the resonance voltage generation period of the transformer 2 is not affected at all by the input capacitance of the commutation FET 6 and the control FET 15, the frequency can be higher than the conversion frequency. (8)

【0019】図9は本発明の他の実施例を示す回路図で
図中STは可飽和トランスで、制御用MOSFET15
のゲート信号を主スイッチ素子3の電流から供給するよ
うにしたものである。
FIG. 9 is a circuit diagram showing another embodiment of the present invention. In the figure, ST is a saturable transformer, and a control MOSFET 15 is provided.
Is supplied from the current of the main switch element 3.

【0020】[0020]

【発明の効果】以上説明したように本発明は出力チョー
クコイルに補助巻線を巻回しこの補助巻線に発生した電
圧で転流用MOSFETを駆動する同期整流方式で、転
流用MOSFETをオフするための制御(放電)回路を
別に設けることにより、前記FETの動作遅れによって
起こるトランス2次側の短絡電流を回避し、本来のチョ
ークコイル駆動方式のメリットである、転流期間全域に
亘るMOSFETの導通が可能になり、効率の低下を防
げる。更にトランスのリセットに要する共振電圧発生期
間を短く出来るので、変換周波数を上げることができ、
小型化に対して有効な手段となる。
As described above, the present invention is a synchronous rectification system in which the auxiliary winding is wound around the output choke coil and the commutation MOSFET is driven by the voltage generated in the auxiliary winding. The control (discharge) circuit is separately provided to avoid the short-circuit current on the secondary side of the transformer caused by the operation delay of the FET, and the conduction of the MOSFET over the entire commutation period, which is an advantage of the original choke coil driving method. Is possible, and a decrease in efficiency can be prevented. Furthermore, since the resonance voltage generation period required for resetting the transformer can be shortened, the conversion frequency can be increased,
This is an effective means for miniaturization.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の同期整流回路の第1の実施例を示す回
路である。
FIG. 1 is a circuit diagram showing a first embodiment of a synchronous rectifier circuit according to the present invention.

【図2】本発明の同期整流回路の第1の実施例の動作波
形を示す波形図である。
FIG. 2 is a waveform diagram showing operation waveforms of the first embodiment of the synchronous rectifier circuit of the present invention.

【図3】本発明の同期整流回路の第2の実施例を示す回
路である。
FIG. 3 is a circuit diagram showing a second embodiment of the synchronous rectifier circuit of the present invention.

【図4】本発明の同期整流回路の第3の実施例を示す回
路である。
FIG. 4 is a circuit diagram showing a third embodiment of the synchronous rectifier circuit of the present invention.

【図5】本発明の同期整流回路の第4の実施例を示す回
路である。
FIG. 5 is a circuit diagram showing a fourth embodiment of the synchronous rectifier circuit of the present invention.

【図6】従来の同期整流回路の第1の例を示す回路図で
ある。
FIG. 6 is a circuit diagram showing a first example of a conventional synchronous rectifier circuit.

【図7】(9) 従来の同期整流回路における動作波形を示す波形図であ
る。
FIG. 7 is a waveform diagram showing operation waveforms in the conventional synchronous rectifier circuit.

【図8】従来の同期整流回路の第2の例を示す回路図で
ある。
FIG. 8 is a circuit diagram showing a second example of a conventional synchronous rectifier circuit.

【図9】本発明の他の実施例を示す回路。FIG. 9 is a circuit showing another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 入力コンデンサ 2 トランス 3 主スイッチ素子 4 整流用MOSFET 5 整流用FETの寄生ダイオード 6 転流用MOSFET 7 転流用FETの寄生ダイオード 8 チョークコイル 9 出力コンデンサ 10 駆動回路 12,16 ダイオード 13 制御(放電)回路 14 制御スイッチ 15 制御FET 17,21 コンデンサ 18 抵抗 20 MOSFET 22 パルストランス 23 駆動信号源 ST 可飽和トランス REFERENCE SIGNS LIST 1 input capacitor 2 transformer 3 main switch element 4 rectifying MOSFET 5 rectifying FET parasitic diode 6 commutating MOSFET 7 commutating FET parasitic diode 8 choke coil 9 output capacitor 10 drive circuit 12, 16 diode 13 control (discharge) circuit Reference Signs List 14 control switch 15 control FET 17, 21 capacitor 18 resistor 20 MOSFET 22 pulse transformer 23 drive signal source ST saturable transformer

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 トランスの1次巻線に主スイッチ素子を
接続し、前記トランスの2次巻線に並列にソース共通の
整流用MOSFETと転流用MOSFETの直列回路を
接続し、整流出力をチョークコイルと出力コンデンサで
平滑するようにした同期整流回路において、前記チョー
クコイルに補助巻線を巻回し、該補助巻線の一部をダイ
オードに介して前記転流用MOSFETのゲートに接続
すると共に、該転流用MOSFETのゲートと前記整流
用MOSFETのドレイン間に前記主スイッチ素子と同
期して動作する制御スイッチを設けたことを特徴とする
同期整流回路。
1. A main switch element is connected to a primary winding of a transformer, and a series circuit of a rectifying MOSFET and a commutating MOSFET common to a source is connected in parallel to a secondary winding of the transformer, and a rectified output is choked. In a synchronous rectifier circuit configured to be smoothed by a coil and an output capacitor, an auxiliary winding is wound around the choke coil, and a part of the auxiliary winding is connected to a gate of the commutation MOSFET via a diode. A synchronous rectifier circuit comprising: a control switch that operates in synchronization with the main switch element between a gate of a commutation MOSFET and a drain of the rectification MOSFET.
【請求項2】 制御スイッチとしてMOSFETを用い
たことを特徴とする請求項1の同期整流回路。
2. The synchronous rectifier circuit according to claim 1, wherein a MOSFET is used as the control switch.
【請求項3】 MOSFETのゲートをトランスの2次
巻線の一端に接続したことを特徴とする請求項2の同期
整流回路。
3. The synchronous rectifier circuit according to claim 2, wherein a gate of the MOSFET is connected to one end of a secondary winding of the transformer.
【請求項4】 トランスの2次巻線間に並列にコンデン
サと抵抗の直列回路を接続し、前記コンデンサと抵抗の
接続点にMOSFETのゲートを接続したことを特徴と
する請求項2の同期整流回路。
4. A synchronous rectifier according to claim 2, wherein a series circuit of a capacitor and a resistor is connected in parallel between the secondary windings of the transformer, and a gate of a MOSFET is connected to a connection point of the capacitor and the resistor. circuit.
【請求項5】 MOSFETのゲート信号を主スイッチ
素子の電流を駆動源とする可飽和トランスから供給する
ようにしたことを特徴とする請求項2の同期整流回路。
5. The synchronous rectifier circuit according to claim 2, wherein the gate signal of the MOSFET is supplied from a saturable transformer driven by the current of the main switch element.
【請求項6】 主スイッチ素子の駆動用パルストランス
を設け、前記パルストランスの駆動信号源により制御ス
イッチを駆動するようにしたことを特徴とする請求項1
又は2の同期整流回路。
6. A pulse transformer for driving a main switch element is provided, and a control switch is driven by a drive signal source of the pulse transformer.
Or 2 synchronous rectifier circuits.
JP03844497A 1997-02-06 1997-02-06 Synchronous rectification circuit Expired - Lifetime JP3515675B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP03844497A JP3515675B2 (en) 1997-02-06 1997-02-06 Synchronous rectification circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP03844497A JP3515675B2 (en) 1997-02-06 1997-02-06 Synchronous rectification circuit

Publications (2)

Publication Number Publication Date
JPH10225114A true JPH10225114A (en) 1998-08-21
JP3515675B2 JP3515675B2 (en) 2004-04-05

Family

ID=12525476

Family Applications (1)

Application Number Title Priority Date Filing Date
JP03844497A Expired - Lifetime JP3515675B2 (en) 1997-02-06 1997-02-06 Synchronous rectification circuit

Country Status (1)

Country Link
JP (1) JP3515675B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001056141A1 (en) * 2000-01-28 2001-08-02 Ericsson Inc. Simplified implementation of parallelability for modules with synchronous rectification
WO2001033709A3 (en) * 1999-11-05 2001-12-13 Ericsson Inc Externally-driven scheme for synchronous rectification
JP2002233144A (en) * 2001-01-30 2002-08-16 Shindengen Electric Mfg Co Ltd Synchronous rectifying-type forward converter
WO2002067409A3 (en) * 2000-11-06 2003-01-30 Ericsson Inc Method and circuit reducing reverse currents in synchronous rectifier converter circuit
EP1513248A2 (en) * 2003-08-18 2005-03-09 Murata Manufacturing Co., Ltd. Switching electric source device
CN114008908A (en) * 2019-06-17 2022-02-01 原子能与替代能源委员会 Device for providing power from an AC voltage

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001033709A3 (en) * 1999-11-05 2001-12-13 Ericsson Inc Externally-driven scheme for synchronous rectification
WO2001056141A1 (en) * 2000-01-28 2001-08-02 Ericsson Inc. Simplified implementation of parallelability for modules with synchronous rectification
US6459600B2 (en) 2000-01-28 2002-10-01 Ericsson, Inc. Method of connecting synchronous rectifier modules in parallel without output voltage faults
WO2002067409A3 (en) * 2000-11-06 2003-01-30 Ericsson Inc Method and circuit reducing reverse currents in synchronous rectifier converter circuit
GB2388721A (en) * 2000-11-06 2003-11-19 Ericsson Inc Method and circuit reducing reverse currents in synchronous rectifier converter circuit
GB2388721B (en) * 2000-11-06 2005-05-18 Ericsson Inc Method and circuit reducing reverse currents in synchronous rectifier converter circuit
JP2002233144A (en) * 2001-01-30 2002-08-16 Shindengen Electric Mfg Co Ltd Synchronous rectifying-type forward converter
EP1513248A2 (en) * 2003-08-18 2005-03-09 Murata Manufacturing Co., Ltd. Switching electric source device
EP1513248A3 (en) * 2003-08-18 2007-07-11 Murata Manufacturing Co., Ltd. Switching electric source device
CN114008908A (en) * 2019-06-17 2022-02-01 原子能与替代能源委员会 Device for providing power from an AC voltage
CN114008908B (en) * 2019-06-17 2024-02-02 原子能与替代能源委员会 Device for providing power from an AC voltage

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