JPH08274195A - Ferroelectric fet element - Google Patents

Abstract

PURPOSE: To obtain a ferroelectric FET element in which the contact resistance is low, the assembly of a switching transistor is easy and the memory holding effect is improved by forming a channel and source, drain of specific oxides. CONSTITUTION: A source 2a, a drain 2b, a channel 2 between the source and the drain, a source electrode, a drain electrode 8 and a gate electrode 5 are provided on a substrate 1. In such a ferroelectric FET element the channel 2 is formed of an oxide semiconductor of a perovskite structure having at least one type of metal elements selected from rare earth metals, Bi and IV group to XI group metal elements. The source 2a and the drain 2b are formed of an oxide conductor exhibiting metal electric conduction. Further, metal oxide 4 of a ferroelectric element having a perovskite structure at least at the part and the electrode 5 provided in contact with it are formed on the channel 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric FET device composed of an oxide layer and capable of operating at room temperature, and more particularly to a ferroelectric FET device useful as an integrated circuit type non-volatile memory.

[0002]

2. Description of the Related Art In recent years, an element for storing a charge in a capacitor on the gate of a Si-MOS and reading out a change in the electrical characteristic of the MOS to be used as a non-volatile memory has been produced, which is called an EEPROM. In addition, a ferroelectric material is also used as a memory. Here, the ferroelectric refers to one that exhibits ferroelectric characteristics at room temperature according to the custom of electronic engineering. Although such a memory has been researched for a long time, in recent years, research on a ferroelectric memory called FRAM has been activated. This uses the polarization state of the ferroelectric substance as a memory. Writing is performed by polarizing the ferroelectric substance in a certain direction, and when reading, an electric field that polarizes the ferroelectric substance is added, and the polarization changes at this time. The generated pulse current is detected and read.

However, this method is
Since the written information is destroyed (destructive read), a circuit system to restore this is further required. Also, at the time of reading, a strong electric field is applied to the ferroelectric as at the time of writing, so the life of the ferroelectric is extended. There was a problem of shrinking. Further, since the detection signal current at the time of reading is proportional to the area of the ferroelectric substance, there is a problem that the area of the cell cannot be made sufficiently small and is not suitable for high integration.

On the other hand, as an FET type ferroelectric memory, an IEEE Transactions on Ele is used.
ctron Device ED-2l, No8, p4
In 1999 (1974), a ferroelectric substance was formed on a field effect transistor element (FET) in which a ferroelectric substance was formed on a Si semiconductor, and F was generated by electric charges induced by this polarization state.
A non-destructive read method of changing the electric conductivity of the ET channel and detecting a current flowing between the channels, and a non-destructive write method of changing the polarization by applying an electric field to the ferroelectric substance are shown.

However, as the ferroelectric material, Si is used.
Alternatively, since it is formed on GaAs or the like, a reaction layer is always formed, the writing voltage is too high, and there is a problem that the semiconductor and the ferroelectric react to form an interface layer and deteriorate the memory retention characteristics. It was In addition, the mechanical properties of the obtained thin film are poorly compatible with the substrate, so that sufficient properties cannot be obtained, which makes it difficult to incorporate into the process or lacks reliability.

On the other hand, the inventors of the present invention believe that the peculiarity of the copper oxide superconductor can be utilized if it is used in the normal conduction state instead of the superconducting state in order to apply it as an electronic device, and to utilize the room temperature characteristic. Through intensive studies, a new FET or the like having the same structure as the copper oxide superconductor and using copper oxide in a semiconductor state has been proposed (see, for example, JP-A-5-190924). Furthermore, studies were repeated for the purpose of using this element as a memory, and in JP-A-6-151872, by using a semiconductor of a perovskite oxide which is easy to match with many ferroelectrics in terms of crystal structure,
It is shown that the conventional problems can be greatly improved. In particular, perovskite oxides having the same crystal structure and different composition as the oxide high temperature superconductor have a charge transfer gap with a preferable width, and thus are suitable for use as the channel layer of the FET, and record retention which has not been found in the past. The characteristics and low voltage writing were possible.

However, if the structure exemplified in Japanese Patent Laid-Open No. 6-151872 is used as it is, the film thickness of the channel layer and the source / drain is thin, the processing precision for making contact with the wiring is severe, and the contact is made in the processing step. There are problems that the resistance is increased and the device characteristics are deteriorated, the area of the source / drain electrodes is increased, and the integration is disadvantageous, and it has been demanded to solve these problems.

[0008]

It has been found that the contact resistance with the channel part and the contact resistance with the metal wiring can be lowered by selecting the material of the source / drain part from a specific oxide. Further, a switching transistor may be incorporated in one means for reading out only the information of the selected cell when it is formed as an integrated circuit, but it does not complicate the process and does not increase the cell area, and only by slightly changing the element structure. They have also found that they can be incorporated and have completed the present invention.

That is, in the ferroelectric FET element according to the present invention, the channel is (1) in the ferroelectric FET element having the source, the drain, the channel between the source and the drain, and the source electrode, the drain electrode, and the gate electrode on the substrate. ) A rare earth metal or Bi and (2) an oxide semiconductor having a perovskite structure containing at least one kind of metal element selected from metal elements of Groups 4 to 11 of the periodic table, and the source and the drain are metallic A metal oxide layer which is formed of an oxide conductor exhibiting conduction and which is at least partially a ferroelectric having a perovskite structure, and a gate electrode provided in contact with the metal oxide layer. Ferroelectric FET
It is an element.

In addition, according to the present invention, in the above-mentioned ferroelectric FET device, the oxide semiconductor of the perovskite structure of the channel layer is a K ₂ NiF ₄ structure, an ABO ₃ structure or a layered compound structure containing Bi, A ferroelectric FET in which the channel and the metal oxide layer that is the ferroelectric substance are substantially epitaxially grown with respect to the substrate, so that the modulation of the device is larger and the memory retention effect is improved.
The device is obtained.

The present invention will be described in detail below. FIG. 1 shows the structure of the ferroelectric FET element of the present invention. Similar to the Si-MOSFET, the basic structure is the substrate 1 and the substrate 1.
It is composed of a drain 2b, a source 2a, which is an oxide having a perovskite structure, a channel 2 and an oxide dielectric 4 and a gate 5 which are formed on the channel 2 and which are formed on the channel 2.

Here, the semiconductor means a semiconductor whose electric resistance sharply increases by lowering the temperature from around room temperature, and its carrier concentration is usually about 5 × 10 ²⁰ / cm at room temperature.
^{It is 3} or less, and if specified by an electrical resistivity that is easier to measure, it is 2 mΩ · cm or more at room temperature, preferably 10
mΩ · cm or more. Further, when the channel layer material has anisotropy of electric resistivity, it is preferable that the low resistance direction is oriented in the direction connecting the source and drain. For example, when the electric resistance in the c-axis direction is significantly higher than that in the a- and b-axis directions such as La _2-x Sr _x CuO _4- δ, the c-axis orientation or the direction in which the c-axis connects the source and the drain. A film oriented so as to be orthogonal to is preferable.

The material used for the source / drain should not react with the material of the channel layer to form a layer having a high electric resistance at its interface, and the heat at the time of forming the channel layer or the source / drain layer, etc. Is selected so that it does not become high resistance due to deterioration. In order to satisfy this condition, it is preferable that the layers formed after the first layer can be formed at the same temperature or lower or the partial pressure of the oxygen source is equal or higher. As a specific example, a material having the same crystal structure as the material used for the channel layer is used. Incidentally, the source / drain layer generally does not have to be epitaxially grown, but in many cases the electric resistance can be reduced by making it epitaxial.
More preferable.

This memory element has an FET structure and stores the polarization state of the ferroelectric substance as a memory. When this element is a non-volatile memory cell, writing and reading of this element are the same as those of the conventional FET type dielectric memory. That is, writing and erasing are performed on the channel 2 and the gate electrode
An electric field is applied between the coercive electric fields of the ferroelectric substance, preferably until the polarization is saturated, and the polarization is aligned in a certain direction. Reading is performed by passing a current between the source 2a and the drain 2b of the FET and detecting the generated voltage.

The sign of the polarization charge generated in the channel of the FET differs depending on the polarization direction of the ferroelectric substance, and the sign of the polarization charge is the same as that of the carrier (p-type or n-type) of the channel (when no electric field is applied). If so, it will have a low resistance, and if it is different, it will have a high resistance and the generated voltage will be different, so it will act as a memory.

However, since switching of the ferroelectric layer generally does not have a clear threshold value, the polarization direction of the ferroelectric layer is partially changed even if a voltage less than half the write / erase voltage is applied to the ferroelectric layer. It is known that the partial inversion occurs even in the device of the present invention. Therefore, when incorporating the memory cell of the present invention into a circuit,
A selection switch is necessary for solving the partial inversion problem and selecting the memory cell at the time of reading.

As a specific example of this selection switch, it is possible to use a configuration substantially equivalent to the circuit configuration used for a conventional Si memory device as disclosed in Japanese Patent Laid-Open No. 2-64993. That is, the ferroelectric layer and the gate electrode in contact with the ferroelectric layer and at least one dielectric layer not showing ferroelectricity and the gate electrode in contact with the ferroelectric layer are provided on the channel. Further, this configuration is disclosed in Japanese Patent Laid-Open No. 2-649.
It has a remarkably simple structure as compared with the configuration described in Japanese Patent Publication No. 93
Since high integration is easy, it is superior to the case of forming an external selection switch.

The selection switch part is a part in which ferroelectrics are integrated.
It is simple to use the same material as the
The number of carriers in the switch portion may be reduced and used. Well
As a gate insulating film, it does not show ferroelectricity and has a dielectric constant.
Is high, it is hard to cause dielectric breakdown, and the leakage current is small (always).
Electric bodies are preferred. As an example, SiO_x(X = 1 to 1
2), TaO_x(X = 1.5 to 2.5), TiO_x(X
= 1.5-2), ZrO _x(X = 1.5 to 2) and SrT
iO₃Paraelectric materials such as perovskite oxide
It In addition, it is a thin film to the extent that it is difficult to reverse the polarization of ferroelectrics.
You may make it into and use it.

If such a method is not used, two to three transistors are arranged for each ferroelectric memory element, and only when both word lines and bit lines are selected, the desired ferroelectric memory element is provided. A circuit may be designed so that a voltage is applied to the ferroelectric substance, or a method of rewriting information for each block may be used. In this case, it is preferable to use a Si or GaAs substrate incorporating these transistors as a substrate for forming this element, and to form this element through a buffer layer described later. If no Si substrate is used,
These transistors may be formed by depositing a semiconductor thin film such as Si on an insulating substrate.

(Channel Layer Material) For the channel layer of the FET of the present invention, an oxide semiconductor having a perovskite structure can be used. That is, YBa ₂ Cu ₃ O ₇ , La
_{2-x M x CuO 4 (} x = 0.06~0.25) cuprate those superconductor sufficiently carrier concentration than the composition and exhibits superconductivity have the same structure is low first like Become a candidate. Specifically, (1) LnBa ₂ Cu ₃ O _{5.5 + x} (Ln is Y, Gd, S
at least one element selected from trivalent rare earth metal elements such as m, Nd and Eu, 0 <x <0.8, where Ln = P
For r 0 <x <1.5) ( 2) Bi 2 Sr 2 (Ca 1-y Ln y) n-1 Cu n O
_{6 + 2n +} δ (0 <δ <1, 1 ≦ n ≦ 3, Ln is a rare earth metal element such as Y and Nd, 0.5 ≦ y ≦ 1) (3) Ln _2−z M _z CuO ₄ −δ ( 0 <δ <0.1, preferably 0 <δ <0.05, 0 ≦ z ≦ 0.05, preferably 0 ≦ z ≦ 0.01, M is Sr, Ca, Ba, Ce, L
n represents a rare earth metal element such as La, Pr, Nd, Sm, Eu and Gd. As a typical example, La _2-z Sr _z CuO _4-
δ and Pr _2-x Ce _x CuO _4- δ) can be exemplified. (4) Cu of the materials described in (1) to (3) above is replaced with another transition metal of Group 7 to Group 10 of the periodic table such as Fe, Ni, Co and Mn.
In particular, a material that is partially or totally substituted with Fe, Ni, or Co. Specific examples include YBa ₂ Cu ₂ CoO ₇ (Co preferably substitutes Cu having a one-dimensional chain structure), Bi ₂ M
_{n + 1 Co n O 6 +} 2n + δ (0 <δ <1, n = 1,2, M =
Ca, Sr, Ba), La _2-z Sr _z CoO _4- δ (0 ≦
z ≦ 0.3), La _2−z Sr _z NiO ₄₋ δ (0 ≦ z ≦
0.3), Nd _2-z Sr _z NiO _4- δ (0 ≦ z ≦ 0.
3) is mentioned.

On the other hand, ABO₃Type perovskite oxide
As a semiconductor, the general formula is Ln_1-xM_xTO₃(Ln is
Rare earth metal elements (La, Ce, Pr, Nd, Sm, E
u, Gd, Td, Dy, Ho, Er, Tm, Yb, L
u and Y, usually at least one selected from La),
M is at least one selected from Mg, Ca, Sr and Ba
Species, usually Sr or Ca, T is a transition metal element
, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, etc.
Periodic table of the metal elements of groups 4 to 11 of the solid solution limit
In the range 0 ≦ x ≦ 0.99, usually up to about 0.4)
There are things. As a specific example, La_1-xM_xT
O₃(M is Ca, Sr, Ba, 0 ≦ x ≦ 0.1 or
0.9 ≦ x ≦ 0.99), La_1-xM_xCrO₃(M is
Mg, Sr, Ba, 0 ≦ x ≦ 0.1), La_1-xM_xM
nO₃(M is Ca, Sr, Ba, 0 ≦ x ≦ 0.2), L
a_1-xM_xFeO₃(M is Sr, Ba, 0 ≦ x ≦ 0.
1), La _1-xM_xCoO₃(M = Sr, Ba, 0 ≦ x
≤0.05), LnFe_1-xMo_xO₃(Both are 0 ≦
x ≦ 0.25, Ln is La, Pr, Nd, Sm, Eu,
Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu,
Y), LaCo_1-xW_xO₃, LnCo_1-xMo
_xO₃, LaNi_1-xW_xO₃, LaNi_1-xMo_xO
₃(0 ≦ x ≦ 0.25) and the like.

Particularly, from the viewpoint of thermal chemical stability and controllability of electric conductivity, perovskite copper oxide having a K ₂ NiF ₄ structure, perovskite oxide having a layered compound structure containing Bi, and Ln _1-x M _x TO _3- δ (Ln is a rare earth element, M
Is Ba, Sr, Ca, Ce, Th, T = a metal element selected from 3d metal elements of Groups 4 to 9 of the periodic table, −0.
04 ≦ δ ≦ 0.04, 0 ≦ x ≦ 0.2) AB
O ₃ -structured perovskite oxides are preferred.

Ln _1-x M _x TO _3- δ
If n is lanthanum, the mobility of carriers is likely to be high, and T is Mn, Fe, Co, Ni, Cu, etc.
It is preferable to include at least one kind of metal element selected from 3d metal elements of Group 3 to Group 9 from the viewpoint of thermal chemical stability and controllability of electric conductivity. The preferred composition range is 0 ≦ x ≦ 0.05, 0 ≦
δ ≦ 0.05. When T is Co, the charge transfer gap is small, which is more preferable.

Other preferable compositions include (1) La _2-x M _x CuO _4- δ (M is Ba, Sr, C
a, −0.04 ≦ δ ≦ 0.04), (2) Ln _2−x Ce _x CuO ₄₋ δ (Ln is Pr, Nd,
Pm, Sm, Eu, Gd, 0 ≦ δ ≦ 0.04), (3) La 2-xy M x Ln y CuO 4- δ (Ln is Pr,
Nd and M are Ba, Sr, Ca, -0.04 ≦ δ ≦ 0.0
4, 0 ≦ y ≦ 1), 0 ≦ x ≦ 0.04, more preferably 0 ≦ x ≦
0.01 composition.

(Source and Drain Material) The source or drain material is selected from the above channel layer materials.
A low electrical resistivity composition can be used. That is, specifically, in the above general formula, x or z is made sufficiently larger than that of the channel layer. Generally, it is a value between 0.1 and 0.5 or less solid solution limit. Specifically, the above _- mentioned La _2-x M _x CuO _4-
δ (M is Ba, Sr, Ca, -0.04 ≦ δ ≦ 0.0
4) or Ln _2-x Ce _x CuO _4- δ (Ln is Pr,
Nd, Pm, Sm, Eu, Gd, 0 ≦ δ ≦ 0.04),
La _2-x M _x Ln _y CuO _4- δ (Ln is Pr, Nd, M
Is Ba, Sr, Ca, -0.04 ≦ δ ≦ 0.04, 0 ≦
y ≦ 1), and a more preferable composition range is that x is 0.1
The range is from 5 to the solid solution limit, usually about 0.3.
Incidentally, these copper oxides have the best superconductivity around x = 0.15, but in the present invention, it is preferable to use x with a larger value (about 0.2 to 0.3).

Further, as the Bi-based layered compound, Bi₂
Sr₂Ca_n-1Cu_nO_{6 + 2n +}δ) 0 <δ <1, 1 ≦ n
≦ 3, preferably n = 1) can be used. the above
Ln _1-xM_xTO_3-δ (T is 3d gold of the 4th to 9th groups
For group elements, -0.04 ≤ δ ≤ 0.04), about 0.1 ≤
A solid solution limit of x ≦ about 0.6 is preferred. Also, Sr₂R
uO_Four, Sr_1-xCa_xRuO₃Gold such as (0 ≦ x ≦ 1)
It may be a generic perovskite. These perovsky
RuO as other conductive oxides in addition to oxide conductors
₂, IrO₂Refractory oxides such as
When the formation temperature of the channel layer is sufficiently low, In₂O₃, G
a₂O₃Etc. can also be used. Source, drain
The layer thickness is preferably much thicker than the channel layer.
, Typically more than double, 500 Å ~ 4000 Å
Is preferred. Thicker is better for easier etching
However, if it is too thick, microfabrication will occur when the element is 1 μm or less.
This is because it becomes difficult to do so.

In order to increase the electric conductivity change due to the electric field, it is necessary to reduce the areal density of carriers in the channel by optimizing the film thickness, and the oxide thin film layer has a layer thickness of 1000Å, preferably 500 Å or less is used,
As long as a good thin film can be obtained, it is more preferable that the thickness is about 100Å. However, in general, the thinner the film thickness, the greater the influence of the substrate interface level and the deterioration of the switching characteristics. Therefore, it is important to improve the quality of the thin film as the film thickness becomes thinner.

(Ferroelectric Material) As the ferroelectric material layer, many known ferroelectric materials having a perovskite structure can be used. In the present invention, the ferroelectric film is preferably grown epitaxially at least at the interface with the semiconductor layer. For this reason, it is preferable that the symmetry in the film plane is similar at least at room temperature, and the integer multiples of the lattice plane intervals in the coincident crystal lattice directions coincide with each other within 5%. An example of this is PLZ
T, that is, (Pb _1-x La _x (Ti _1-y Zr _y ) O ₃ (0 ≦
x ≦ 0.1, 0 ≦ y ≦ 0.5), Bi ₃ Ti ₄ O ₁₂ , B
a _1-x Sr _x TiO ₃ (0 ≦ x ≦ 0.4) and the like can be exemplified, and the long axis direction thereof is made perpendicular to the film surface to form La _2−x Sr _x Cu.
O _4- δ (-0.04≤δ≤0.04, 0≤x≤0.0
4), Bi ₂ Sr ₂ Ca _{n- 1} Cu _n O _{6 + 2n +} δ (0 <δ
<1, 1 ≦ n ≦ 2) or La _1-x Sr _x CoO ₃ (0 ≦
(x ≦ 0.05) When laminated with a C-axis oriented film, the lattice constants match within 5%.

To retain the memory, the Curie temperature is 1
It is necessary that the temperature is not lower than 00 ° C. Furthermore, the remanent polarization charge density is 1 μC (microcoulomb) / cm ² or more, and the coercive electric field value at the time of thinning is sufficiently smaller than the value obtained by dividing 10 V by the film thickness (typically 100 kV / cm), and the minimum voltage and It is preferable to have a coercive field value that is sufficiently higher than the fluctuation level. Further, it is preferable that the electric resistance is sufficiently high and there is no pinhole so that the leakage current from the gate to the channel is sufficiently small (typically 1 μA or less).

The thickness of the ferroelectric layer is such that the polarization is saturated at a low gate switching voltage of 0.1 V to 5 V.
The thinner the film thickness, the better as long as the coercive electric field is suitable. However, if the film thickness is extremely thin, the leakage current may not be negligible or the ferroelectricity may be lost, so the normal film thickness is 1000Å to 5000Å.

The ferroelectric thin film is preferably epitaxially grown on the channel layer. However, if polycrystallization causes a decrease in the leakage current of the ferroelectric or an increase in remanent polarization, at least a part of the ferroelectric thin film is increased. It may be crystallized. Moreover, the ferroelectric thin film is preferably oriented such that the polarization charge, the electrical resistivity and the dielectric breakdown voltage are maximized in the film thickness direction. Further, the ferroelectric layer is usually a single phase composed of one kind of ferroelectric material, but it may be a multiphase, or it may be multi-layered with different paraelectric materials, antiferroelectric materials or ferroelectric materials. Alternatively, a superlattice may be formed to improve characteristics such as polarization charge, electric resistivity, breakdown voltage, and coercive electric field.

In particular, it is preferable that the side directly in contact with the channel layer has a high insulating property and has few defects, and it is necessary to suppress the interface reaction with the channel layer to the minimum. Therefore, it is possible to epitaxially grow the channel layer in this portion. A paraelectric material having a high dielectric constant and a good lattice matching with the channel layer material, for example, Sr _1-x Ba _x TiO ₃ (0 ≦ x ≦ 0.7) or Pb
_A ferroelectric substance may be formed on _1-x La _x TiO ₃ (0.15 ≦ x ≦ 0.25) or the like.

The gate electrode (upper electrode) on the ferroelectric is
Conventionally good conductive metals such as Pt, Au, Al and Cu, and laminated films and alloys thereof may be used, and the material system shown in the above-mentioned channel material may be selected from among the channel materials. Further, it may be doped to have high conductivity. However, it is preferable that the substrate temperature required for the film formation does not exceed the substrate temperature at the time of forming the ferroelectric layer.

(Film formation) Usually, a channel, a ferroelectric layer, and an (upper) gate electrode are formed in this order on the substrate. When a conductive oxide is used for the gate electrode, the gate electrode and the ferroelectric layer are formed. The body layer, the channel, and optionally the protective film may be sequentially laminated on the substrate. In this case, there are advantages that the effect of the ferroelectric substance can be exerted on a wide range of the channel, large modulation can be taken, and patterning is easy.

The thin film is formed by physical vapor deposition such as laser vapor deposition, sputter vapor deposition, reactive vapor deposition, MO-CVD, CV.
Chemical vapor deposition such as D or plasma CVD can be used. The substrate is preferably a material that has a good lattice match with the channel material, for example, a minimum lattice plane of about 4Å × 4Å can be selected, and one in which the reaction between the substrate and the channel layer during the formation of the channel layer is sufficiently small is preferable. An example is Mg
O, SrTiO ₃ , LaAlO ₃ , NdGaO ₃ , Pr
GaO ₃ , LaSrGaO ₄ , NdSrGaO ₄ , Nd
Doped YAlO ₃ , YSZ (Y-doped Zr
O ₂ ), Y ₂ O ₃ , Gd ₂ O ₃ , CeO ₂ , Dy ₂ O ₃
An oxide single crystal substrate such as an oxide of a rare earth metal is used, and a sapphire, Si, or GaAs substrate in which these oxides are thinned and laminated as a buffer layer to suppress an interface reaction is used. Further, an amorphous material such as glass on which a buffer layer is formed may be used as the substrate.

(Processing) In element processing, acid (HF, HCl, HNO ₃ , H ₂ SO ₄ , H
₃ PO ₄ , Br ethanol, acetic acid, oxalic acid, etc.), plasma etching (Ar, O ₂ , N ₂ , Br ₂ , CH _n Cl _{4- n} , CH _{n in} dry lithography.
Mixed gas such as F _4-n (n = 1 to 4), ion (neutral atom) milling (Ar, O ₂ , N ₂ , Br ₂ , C)
L ₂ etc.) is used. In this case, the higher the etching rate is, the more convenient the process is. Such adjustment of the etching rate can also be realized by devising the process, for example, using a selective etchant, selecting a material that is more easily etched in the upper layer, and the like.

The element can be processed by a known lithography method using a photoresist or an electron beam resist or a resistless processing method such as laser etching or focused ion beam etching. This time,
When using a Si substrate or the like and disposing a Si transistor in the present memory element, the transistor is formed on the Si substrate in advance, and then a thin film is formed.

3, 4, and 5 show the ferroelectric FE according to the present invention.
It is a figure explaining the manufacturing process of a T element, and a resist process is abbreviate | omitted and described. As shown in FIGS. 1 and 2, the case where thin films are sequentially formed on the substrate from the channel is shown. 1 is a substrate, 2 is a channel layer, 3 is a paraelectric layer, 4 is a ferroelectric layer, 5 is a ferroelectric gate electrode, 6 is an insulating film, 7 is a paraelectric gate electrode, and 8 is a source / drain portion electrode. 2a is a source and 2b is a drain. FIG. 3 shows a case where there is no gate for the switching transistor and a case where there is a gate for the switching transistor. 3 to 5 show a method of forming a contact to the channel by etching up to the channel layer 2 after forming the gate electrode 5, but in the process of FIG. 4, the dielectric layer 3 is formed and then the channel layer 2 is formed. The contacts to the gate electrode 5 and the channel 2 may be formed by etching up to the top.

In the case of FIG. 3, at least the channel layer 2 must be patterned in advance. This may be patterned after the formation of the channel layer 2 and before the formation of the gate electrode 5, or it may be a thin film that reacts with the channel layer 2 in a place other than the channel layer before the formation of the channel layer 2 to significantly reduce the electrical conductivity. The channel layer may be pre-patterned by forming layer 8 (Si, Zn, Cr, etc. and compounds thereof).

The above procedure will be described with reference to FIG. FIG.
Then, first, thin films for the source 2a and the drain 2b are deposited on the substrate 1 (FIG. 3a), a resist is applied and developed, and only the source / drain portions 2a and 2b are left by etching (FIG. 3b). Next, the channel layer 2,
Ferroelectric layer 4 is laminated (FIG. 3c), a resist is applied and developed, and etching is performed so as to leave only a portion directly above the gate of the ferroelectric 4 and electrically conductive to the source / drain portion. At least a channel layer. Etch leaving 2 (FIGS. 3d and 3e). At this time, the step of adjusting the outer shape of the device at the beginning of FIG. 3d may be omitted, and the process may be performed as shown in FIG. 3e at once. Next, the gate electrode 5 and the source / drain electrode 8 are formed by preventing the gate electrode 5 and the channel layer 2 from being short-circuited with the insulating film 6 such as SiO 2 (FIG. 3f).

On the other hand, FIGS. 4 and 5 are process diagrams in the case of incorporating a paraelectric gate for a selection switch. FIG. 4 shows the case where the paraelectric layer and the ferroelectric layer are laminated in this order, and the opposite is the case in FIG. In FIG. 4, first, thin films for the source 2a and the drain 2b are deposited on the substrate 1 (FIG. 4a), and the source / drain portion 2a,
Only 2b remains (Fig. 4b). Next, the channel layer 2 and the paraelectric layer 3 are laminated (FIG. 4c), and etching is performed (FIG. 4) only right above the portion where the paraelectric gate is provided.
d). Next, the ferroelectric layer 4 is laminated (FIG. 4e), and etching is performed until the source / drain portions 2a and 2b are electrically connected (FIG. 4f), leaving only the portion directly above the portion where the ferroelectric gate is provided. Next, the gate electrode 5 and the channel layer 2 are prevented from being short-circuited by the insulating film 6 such as SiO 2 (FIG. 4g).
The gate electrodes 5 and 7 and the source / drain electrode 8 are formed (FIG. 4h). The paraelectric layer used in this step does not react with either the channel layer or the ferroelectric layer at the deposition temperature of the ferroelectric layer, and preferably has good lattice matching. Of the bodies, perovskite oxides are preferred.

On the other hand, in FIG. 5, first, thin films for the source 2a and the drain 2b are deposited on the substrate 1 (FIG. 5a),
Only the source / drain portions 2a and 2b are left by etching (FIG. 5b). Next, the channel layer 2 and the ferroelectric layer 4 are laminated (FIG. 5c), and etching is performed (FIG. 5d), leaving only the portion directly above the portion where the ferroelectric gate is provided. Next, the paraelectric layer 3 is laminated (FIG. 5e), and the paraelectric layer in other portions is removed, leaving only the portion directly above the portion where the paraelectric layer gate is provided (FIG. 5f). Next, the source / drain portions 2a and 2b
The parts other than the gate part are etched until electrical continuity is obtained (FIG. 5g). Next, the gate electrode 5 and the channel layer 2 are prevented from being short-circuited by the insulating film 6 such as SiO 2 (see FIG.
h), the gate electrodes 5 and 7 and the source / drain electrode 8 are formed (FIG. 5i). The etching shown in FIGS. 5f and 5g may be performed at once if the ferroelectric characteristics of the gate portion 5 are small due to the etching.

Also, during or after the above process, heat treatment in oxygen or air may be performed to recover the deterioration during processing. The paraelectric layer used in this step must be manufactured at a low temperature so that the channel layer and the ferroelectric layer do not react with each other and deteriorate. Therefore, the paraelectric layer may not necessarily be a crystalline film but may be polycrystalline or amorphous. However, it has been found that this reaction can be ignored up to about 300 ° C. In this case, all of the above-mentioned paraelectric materials for switching gates can be used.

In addition to the memory element, this element may be applied as a pseudo neural circuit element.

[0045]

EXAMPLES The present invention will be described in more detail with reference to examples. (Example 1) 99.9% pure La ₂ O _3, SrC
O ₃ and CuO powders were sintered at 1050 ° C and La _1.75 Sr
_{A 0.25} CuO ₄ , La _1.99 Sr _0.01 CuO ₄ target was produced. This target and PbO, TiO ₂ , Zr
PbTi _0.8 Zr _0.2 O ₃ prepared by mixing and sintering O _2.
The target was placed on a target holder in a vacuum device. As the substrate, a 15 mm square SrTiO ₃ (100) substrate with high polishing accuracy (surface roughness of about 20 Å) was used.

First, La _1.75 Sr _0.25 Cu was formed by laser deposition at an oxygen pressure of 100 mtorr and a substrate temperature of 720 ° C.
About 2000 liters of O ₄ was deposited. In laser deposition, Ar
Using F laser, laser power density is about 1 J / cm
^{2. The} repetition frequency was 5Hz, and the target was rotated and revolved while laser scanning the target.

The substrate was taken out into the atmosphere, a resist was applied, and the shape of the source drain portion was cut out by milling with an ion beam neutralized into a convex shape. At this time, the size of the convex projection of the source / drain was a square having a side of 100 μm, and the convex stand portion was a square having a side of 1 mm. The distance between the convex tip of the source and the convex tip of the drain is 200μ
m. In the ion milling, a slight overetching (about 10Å) was carried out so that La _1.75 Sr _0.25 CuO ₄ was completely removed from this portion.

After removing the resist and washing with ultrapure water, the resist is set again in the laser deposition apparatus, the oxygen pressure is set to 100 mtorr, and the substrate temperature is heated from 720 ° C. to room temperature. La _1.75 Sr _0.25 CuO at the same substrate temperature and oxygen pressure
La _1.99 Sr _0.01 C by laser deposition under the same conditions as ₄
About 200Å of uO ₄ was deposited. After this oxygen pressure is 300m
After setting the temperature to torr and lowering the substrate temperature to 590 ° C. and stabilizing the substrate temperature, PbTi _0.8 Zr _0.2 O is formed by laser deposition.
₃ was laminated in 3000Å. Laser power density is about 3J
/ Cm ² , other conditions were not changed. Cooling while filling oxygen to 600 torr in the laser deposition device,
When the substrate temperature was around room temperature, it was taken out into the atmosphere. X-ray diffraction of this laminated film provided results corresponding to the C-axis orientation of each layer.

A resist was applied to this laminated film and developed, and each element was cut out in a bridge type in order to separate each element by ion milling. For element isolation,
It was performed by etching a little deeper than Å. After the separation, in order to connect the electrodes to the source and drain, Pb
The Ti _0.8 Zr _0.2 O ₃ layer was removed by etching leaving about several tens of Å. At this time, the etching precision was increased by using the conditions used for element isolation. After that, the photolithography process was used again to perform the insulation separation of the channel and the gate by the SiO _x (1 ≦ x ≦ 1.5) thin film and the formation of the gate, source and drain electrodes by the gold thin film. The effective area of the gate electrode of the final device is about 50 microns x 170 microns,
The channel width and length was about 50 microns x 200 microns. For this device, as shown in FIG. 6, the source was grounded, a DC voltage was applied to the drain, and a pulse voltage was applied to the gate, and the memory characteristics were measured by the two-terminal method. Apply + 7V voltage to gate 5 for 0.1ms,
After 5 minutes, the operation of applying the −7V voltage for 0.1 millisecond was repeated to read the current I flowing between the source 2a and the drain 2b. The result is shown by the solid line in FIG.

In the present embodiment, La_1.75Sr_0.25CuO
_FourTo Sr₂RuO_Four, SrRuO₃Even if you change to P
bTi_0.8Zr_0.2O₃To PbTi_0.9Zr_0.1O₃,
Pb _0.95La_0.05Ti_0.8Zr_0.2O₃Same as if
The result was obtained.

(Comparative Example 1) La _{1.75 is formed in the} source / drain portion.
An element having the same final element size as that of the example was formed in the same manner as in example 1 except that the Sr _0.25 CuO ₄ layer was not formed. The final element has the same configuration as the element according to Example 1 except that 2a and 2b are not provided in FIG. Memory characteristics were measured by the two-terminal method in the same manner as in Example 1. In this case, however, a voltage pulse of ± 7 V was used for 1 ms because sufficient modulation could not be obtained with a voltage pulse of ± 7 V for 0.1 ms. The result is shown by the dotted line in FIG. Although the result is qualitatively the same as that of the first embodiment, the absolute value of the current value and the modulation width are reduced to about half. Further, when an element was manufactured with this configuration, the difference in characteristics between batches and the difference in characteristics within the same batch were larger than in Example 1.

(Comparative Example 2) A source / drain portion was formed in the source / drain portion using polycrystalline Si, which has been often used in the past, and thereafter, an element having the same final element size was formed in the same manner as in Example 1. did. The memory characteristic was measured by the two-terminal method in the same manner as in Example 1, but the current value was 100 of Example 1.
Memory characteristics could not be measured below 1/0. Also, a similar device was manufactured by using Al instead of Si, but it was the same.

(Comparative Example 3) A source / drain portion was formed of platinum on the source / drain portion, and thereafter, an element having the same final element size was formed in the same manner as in Example 1. The memory characteristics were measured by the two-terminal method as in Example 1, but only the same current and modulation as in Comparative Example 1 were obtained.

Comparative Example 4 A laser deposition method was used to form a 2000 Å layer of SrTiO ₃ : 1 wt% Nb on the source / drain portion and a 200 Å layer of SrTiO ₃ : 0.1 wt% Nb on the channel portion. The other conditions are those in Example 1.
A device having the same final device size as that of the example was formed in the same manner as in. Memory characteristics were measured by the two-terminal method in the same manner as in Example 1. At a source-drain voltage of 1 V, the current value was less than 1/1000 of that of Example 1, and the memory characteristics could not be measured.

(Example 2) La having a purity of 99.9%
La _0.5 Sr _0.5 CoO ₃ and La _0.99 Sr produced by sintering ₂ O ₃ , SrCO ₃ and CoO powder at 1050 ° C.
_0.01 CoO ₃ target and PbO, TiO ₂ , Zr
PbTi _0.8 Zr _0.2 O ₃ prepared by mixing and sintering O _2.
The target was placed on a target holder in a vacuum device. As the substrate, a 15 mm square SrTiO ₃ (100) substrate with high polishing accuracy (surface roughness of about 20 Å) was used. With an oxygen pressure of 100 mtorr and a substrate temperature of 680 ° C.,
About 20 La _0.5 Sr _0.5 CoO ₃ was deposited by laser deposition.
00Å deposited. Laser power density is about 1 J / c
m ² , and the repetition frequency was effective 5 Hz.

In the same manner as in Example 1, take out into the atmosphere and
Stroke is applied to neutralize the shape of the source and drain parts to a convex shape.
It was cut out by milling with the ion beam. Chan
Completely La from the flannel part_0.5Sr_0.5CoO₃Without
It was overetched a little. After this, remove the resist
Separated, washed with ultrapure, then installed again in the laser deposition equipment
Then, set the oxygen pressure to 100 mtorr and set the substrate temperature from room temperature.
Heat to 680 ° C. At the same substrate temperature and oxygen pressure
Then, by the laser deposition under the same conditions as described above, La_{0. 99}S
r_0.01About 200Å of CoO was deposited. After this, increase the oxygen pressure to 3
Set to 00 mtorr and lower the substrate temperature to 580 ° C
After stabilization of the substrate temperature, laser deposition of PbTi_0.8Zr
_0.2O₃3000 Å were laminated. Laser power density is
About 3 J / cm ²Other conditions were the same as above. laser
ー While filling the vapor deposition equipment with oxygen up to 600 torr
After cooling, when the substrate temperature is near room temperature, place it in the atmosphere.
Started. In X-ray diffraction of this laminated film, the C-axis orientation of each layer
Corresponding results were obtained. After that, in the same manner as in Example 1,
Thus, an element having the same final dimensions as in Example 1 was obtained.

For this device, the memory characteristics were measured by the two-terminal method as in Example 1. When a + 7V voltage is applied to the gate 5 for 0.1 millisecond, the source 2a drain 2b
The value of the current flowing between the electrodes was 0.8 μA on average, and when a voltage of −7 V was applied for 0.1 msec after 5 minutes, the current value was 0.9 μA on average, which were repeatedly observed.

(Comparative Example 5) La _{0.5 in the} source / drain portion.
An element having the same final element size as that of Example 2 was formed in the same manner as in Example 2 except that the Sr _0.5 CoO ₃ layer was not formed. The final element has the same configuration as that of the second embodiment except that there are no 2a and 2b. The memory characteristics were measured by the two-terminal method in the same manner as in Example 2. In this case, however, a voltage pulse of ± 7 V was used for 1 ms because sufficient modulation could not be obtained with a voltage pulse of ± 7 V for 0.1 ms. Example 2
Compared with, the absolute value of the current value and the width of the modulation became about half. Further, when an element was manufactured with this configuration, the difference in characteristics between batches and the difference in characteristics within the same batch were larger than in Example 2.

(Embodiment 3) In the same manner as in Embodiment 1, La
_1.7 Sr _0.3 CuO ₄ was deposited to about 2000 Å to form a convex-shaped source / drain portion. La _1.99 Sr _0.01 CuO
About ₄ of 200 was deposited. After this, oxygen pressure is set to 300 mto
After setting the temperature to rr, lowering the substrate temperature to 530 ° C., stabilizing the substrate temperature, and then laser-depositing Bi ₄ Ti ₃ O ₁₂ to 3000.
Å Stacked. The laser power density was about 3 J / cm ² and the other conditions were the same as above. 60 in laser deposition equipment
The substrate was cooled to 0 torr while being filled with oxygen, and when the substrate temperature reached around room temperature, it was taken out into the atmosphere. In X-ray diffraction of this laminated film, as shown in FIG. 8, results corresponding to the C-axis orientation of each layer were obtained.

In the same manner as in Example 1, the device isolation and saw
PbTi on the drain and drain_0.8Zr_0.2O₃Layer removal,
Insulation separation of gate, gate, source, and drain with thin gold film
The in electrode was formed. With gate electrode of final device
Effective area is about 50 micron x 170 micron, channel
The width and length are about 50 microns x 200 microns.
This device has a memory characteristic of 2 as in Example 1.
It was measured by the terminal method. + 5V for 0.1ms to gate 5
When pressure is applied, the electric current flowing between the source 2a and the drain 2b
The average flow rate is 1.5 μA, and after 5 minutes 0.1 ms
When -7V voltage is applied, the current value becomes 1.7μA on average.
Moreover, these were repeatedly observed. Source and drain
La of part_1.7Sr_0.3CuO_FourTo Bi₂Sr₂CuO₆₊
δ (0 <δ <0.5), La of the channel section_1.99Sr
_0.01CuO_FourTo Bi₂Sr₂CoO _6.25+δ (0 <δ <
Similar results were obtained even when changing to 0.5).

Example 4 Using a SrTiO ₃ (100) substrate of 15 mm square with high polishing accuracy, La _1.75 Sr _0.25 CuO ₄ was deposited by about 2000 Å by laser vapor deposition in the same manner as in Example 1 and was sourced by ion milling. cut out the drain part, La _{1. 99} Sr _0.01 again by the laser deposition
The same procedure as in Example 1 was performed until about 200 Å of CuO ₄ was deposited. Then, the oxygen pressure was set to 1 mtorr, the substrate temperature was lowered to 450 ° C., and after stabilizing the substrate temperature, 100 Å of SrTiO ₃ was laminated by laser deposition. Laser power density is about 3 J / cm ² , repetition frequency is 5 Hz
Then, the target was rotated and revolved and vapor-deposited while laser scanning the target. Next, set the oxygen pressure to 300 mt.
Orb was set, the substrate temperature was raised to 580 ° C., and 3000 Å of PbTi _0.8 Zr _0.2 O ₃ was laminated by laser deposition. The laser power density was about 3 J / cm ² and the other conditions were the same as above. 600tor in laser deposition equipment
It was cooled while being filled with oxygen up to r, and taken out into the atmosphere when the substrate temperature became around room temperature.

A resist was applied to this laminated film and developed, and each element was cut out in a bridge type in order to separate each element by ion milling. Next, in order to reduce the ferroelectric film thickness on the paraelectric gate to make it paraelectric, after the photolithography process, leave the ferroelectric gate part and leave the other ferroelectric layers at 300 Å. Ion-milled. Next, in order to electrically connect the electrodes to the source and drain, a PbTi _0.8 Zr _0.2 O ₃ layer other than on the paraelectric gate 7 ferroelectric gate was removed by etching by a photolithography process and ion milling, leaving about several tens of Å. After that, the photolithography process was used again to perform the insulation separation of the channel and the gate by the SiO _x (1 ≦ x ≦ 1.5) thin film and the formation of the gate, source and drain electrodes by the gold thin film.

The effective area of the ferroelectric gate electrode of the final device is about 50 microns × 100 microns, the effective area of the two paraelectric gate electrodes is about 50 microns × 350 microns, and the channel width and length are about 50 micron x 200
Micron. For this device, as shown in FIG. 9, the source was grounded, a direct current voltage was applied to the drain, and independent pulse voltages were applied to the ferroelectric gate and the paraelectric gate, and the memory characteristics were measured by the two-terminal method. . A voltage of + 7V is applied to the ferroelectric gate 5 for 0.1 second, and immediately thereafter, a voltage of + 5V is applied to the paraelectric gate 7 for 1 second, the current value is read during this period, and a voltage of -5V is applied for 1 second. When reading the value, 0.03μA and 0.2μA respectively
Met.

Next, after 5 minutes, a voltage of -7V was applied to the ferroelectric gate 5 for 0.1 millisecond, and immediately thereafter, a voltage of + 5V was applied to the paraelectric gate 7 for 1 second, and the current value during this period was read. When a voltage of -5 V was applied for a second and the current values were read during this period, they were 0.04 μA and 0.23 μA, respectively.
From this, it can be seen that by applying a voltage to the paraelectric gate, any memory cell in the integrated state can be selectively read. Next, when a voltage of +5 V was applied to the paraelectric gate and a voltage of ± 7 V was applied to the ferroelectric gate for 0.1 ms, the read current after that was the same as before the voltage was applied. From this, it can be seen that by combining the voltage pulses to the paraelectric gate, any memory cell in the integrated case can be selectively rewritten.

[0065]

EFFECTS OF THE INVENTION The element of the present invention, which is an improved ferroelectric FET element using an oxide semiconductor having a perovskite structure that can be formed on the same substrate as an oxide having a perovskite structure or can be epitaxially grown on each other, has high integration. It can be applied to memory and pseudo neural circuits that cannot be obtained with conventional semiconductor devices. Further, an element smaller than the limit size of the conventional Si semiconductor element becomes possible. In the examples and the comparative examples, a relatively large element is manufactured for the purpose of confirming characteristics as a memory element, but it goes without saying that the present invention is not particularly limited to this size.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of the most basic configuration of a device according to the present invention.

FIG. 2 is a diagram showing another basic configuration example of the element according to the present invention.

FIG. 3 is a diagram showing a step of element processing.

FIG. 4 is a diagram showing a step of element processing.

FIG. 5 is a diagram showing a step of element processing.

FIG. 6 is a diagram showing a characteristic measuring method of an element according to the present invention.

FIG. 7 is a diagram showing a characteristic measurement result of an element according to the present invention.

FIG. 8 is a diagram showing an X-ray diffraction pattern of a laminated film used in the device according to the present invention.

FIG. 9 is a diagram showing a characteristic measuring method of an element according to the present invention.

[Explanation of symbols]

1 Substrate 2 Channel Layer 3 Dielectric Layer 4 Ferroelectric Layer 5 Ferroelectric Gate Electrode 6 Insulating Film 7 Paraelectric Gate Electrode 8 Source / Drain Part Electrode 2a Source 2b Drain 10 DC Power Supply 11 Ammeter 12 Pulse Source 12b Pulse Source 1b Semiconductor substrate 2c Source (highly doped region with reverse conduction type carrier with substrate) 2d Drain substrate and highly doped region with reverse conduction type carrier)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location C30B 29/22 H01L 29/78 617S H01L 27/10 451 618B 29/786 21/336

Claims (7)

[Claims] 1. A source, a drain, a channel between the source and the drain, a source electrode, and a drain electrode on a substrate,
In a ferroelectric FET device having a gate electrode, the channel has a perovskite structure containing (1) a rare earth metal or Bi and (2) at least one metal element selected from metal elements of Groups 4 to 11 of the periodic table. A metal oxide layer composed of an oxide semiconductor, a source and a drain of which are formed of an oxide conductor exhibiting metallic electrical conductivity, and at least a part of which is a ferroelectric having a perovskite structure on the channel, and in contact with the metal oxide layer. A ferroelectric FET device characterized in that a provided gate electrode is formed. 2. The perovskite structure oxide semiconductor of the channel layer is K ₂ NiF ₄ structure, ABO ₃ structure or B.
2. The ferroelectric FET device according to claim 1, wherein the ferroelectric FET device has a layered compound structure containing i, and the channel and the metal oxide layer as the ferroelectric substance are substantially epitaxially grown on the substrate. 3. The ferroelectric layer according to claim 1, further comprising a ferroelectric layer and a gate electrode in contact with the ferroelectric layer, and at least one dielectric layer not exhibiting ferroelectricity and a gate electrode in contact with the ferroelectric layer on the channel. Dielectric FET device. _4. A perovskite oxide having a K ₂ NiF ₄ structure is La _2-x M _x CuO _4- δ (M = Ba, Sr, C
a, δ = −0.04 to 0.04, x = 0 to 0.04) or Ln _2−x Ce _x CuO ₄₋ δ (Ln = Pr, Nd,
Pm, Sm, Eu, Gd, δ = 0 to 0.04, x = 0
0.04), La _2-xy M _x Ln _y CuO _4- δ (Ln =
Pr, Nd, M = Ba, Sr, Ca, δ = −0.04 to
0.04, y = 0 to 1, x = 0 to 0.04), The ferroelectric FET element according to claim 2. 5. ABO₃Structural perovskite oxide
But Ln_1-xM_xTO _3-δ (Ln = rare earth element, M = B
a, Sr, Ca, Ce, Th, T = Group 4 to Periodic Table
At least one metal selected from Group 11 metal elements
Element, δ = −0.04 to 0.04, x = 0 to 0.99)
The ferroelectric substance F according to claim 2, characterized in that
ET element. 6. A perovskite having a layered compound structure containing Bi.
Ito oxide is Bi ₂Sr₂(Ln_1-xCa_x)_n-1C
u_nO_{6 + 2n +}δ (Ln = rare earth element, 0 <δ <1, n =
1-3, Ln = Y, rare earth metal elements such as Nd, x = 0
0.2) The ferroelectric according to claim 2, wherein
Body FET device. 7. A perovskite having a layered compound structure containing Bi.
Ito oxide is Bi ₂Sr₂(Ln_1-xCa_x)_n-1T
_nO_{6 + 2n +}δ (Ln = rare earth element, T = periodic table group 7?
At least one selected from Group 3 3d metal elements
Metal elements of class 0 <δ <1, n = 1 to 3, Ln = Y, Nd
And other rare earth metal elements, x = 0 to 1),
The ferroelectric FET device according to claim 2.