KR100389894B1 - Mfs transistor using cbn - Google Patents
Mfs transistor using cbn Download PDFInfo
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- KR100389894B1 KR100389894B1 KR1019960080122A KR19960080122A KR100389894B1 KR 100389894 B1 KR100389894 B1 KR 100389894B1 KR 1019960080122 A KR1019960080122 A KR 1019960080122A KR 19960080122 A KR19960080122 A KR 19960080122A KR 100389894 B1 KR100389894 B1 KR 100389894B1
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 26
- 239000010703 silicon Substances 0.000 claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 3
- 229910052751 metal Inorganic materials 0.000 claims abstract description 3
- 238000003980 solgel method Methods 0.000 claims description 9
- 230000005669 field effect Effects 0.000 claims description 8
- 239000012212 insulator Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract description 10
- 239000012774 insulation material Substances 0.000 abstract 1
- 239000000463 material Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 230000008021 deposition Effects 0.000 description 4
- 230000005621 ferroelectricity Effects 0.000 description 4
- 238000004549 pulsed laser deposition Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000010287 polarization Effects 0.000 description 3
- 239000010408 film Substances 0.000 description 2
- 235000015067 sauces Nutrition 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6684—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a ferroelectric gate insulator
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Abstract
Description
본 발명은 금속-강유전체-반도체(Metal-Ferroelectric-Semiconductor; MFS) 구조의 트랜지스터에 관한 것으로, 상세하게는 CBN 강유전체를 버퍼층으로 이용한 MFS 구조에 의한 전계 효과 트랜지스터(Field Effect Transistor; FET)에 관한 것이다.The present invention relates to a metal-ferroelectric-semiconductor (MFS) transistor, and more particularly to a field effect transistor (FET) using an MFS structure using a CBN ferroelectric as a buffer layer. .
도 1은 일반적인 MFS-FET의 대략적인 구조를 나타내는 단면도이다. 도시된 바와 같이, 일반적인 개념의 MFS-FET는 실리콘 기판(1)의 상부에 불순물이 도핑되어 형성된 소스(2) 및 드레인(3)을 구비한 반도체 트랜지스터의 채널(1') 상부에 직접 강유전체층(4)을 형성하고, 그 위에 백금 전극(5)을 형성한 구조로 되어있다.1 is a cross-sectional view showing a schematic structure of a general MFS-FET. As shown, a general concept MFS-FET is a ferroelectric layer directly on top of a channel 1 'of a semiconductor transistor having a source 2 and a drain 3 formed by doping impurities on top of a silicon substrate 1. (4) was formed and the platinum electrode 5 was formed on it.
일반적으로 강유전성(ferroelectric) 물질을, 상기와 같이, 실리콘 위에 증착하여 게이트 산화막(gate oxide)으로 이용하기 위해서는 강유전체 물질(4)과 실리콘(1)과의 계면에서의 반응이 없어야 하는것이 우선적인 조건이다. 현재 사용되는 PZT와 같은 강유전체를 실리콘 위에 증착할 경우 바로 Pb와 실리콘과의 반응이 일어나 계면에 반응층이 형성되는 문제를 발생시키므로, 실제 도 1에 도시된 바와 같은 MFS FET의 제조라는 것은 매우 어렵다고 할 수 있다. 이를 피하기 위한 방법으로 강유전체와 실리콘 사이에 절연막을 삽입하는 방법도 강구되고 있으나 이 절연층에 의한 전압강하 효과가 커서 실제 강유전체의 분극반전을 일으키고 트랜지스터를 작동시키기 위해서는 다소 높은 수준의 전압이 요구된다.In general, in order to deposit a ferroelectric material on silicon as described above and use it as a gate oxide, it is preferable that there is no reaction at the interface between the ferroelectric material 4 and the silicon 1. to be. When a ferroelectric such as PZT is used on silicon, a reaction between Pb and silicon occurs immediately, resulting in the formation of a reaction layer at the interface. Therefore, it is very difficult to manufacture an MFS FET as shown in FIG. 1. can do. As a method of avoiding this, a method of inserting an insulating film between the ferroelectric and silicon has been devised. However, since the voltage drop effect by the insulating layer is large, the polarization inversion of the ferroelectric is actually required, and a relatively high level of voltage is required to operate the transistor.
본 발명은 상기와 같은 문제점을 개선하고 창안된 것으로, 높은 수준의 전압이 요구되지 않아 저전압에 의한 분극 반전이 용이하게 일어나면서도, 제조 공정시 실리콘과 반응하지 않는 강유전체층을 구비한 MFS FET를 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and provides an MFS FET having a ferroelectric layer that does not react with silicon during the manufacturing process while easily inverting polarization due to low voltage because a high level of voltage is not required. Its purpose is to.
도 1은 일반적인 MFS-FET의 대략적인 구조를 나타내는 단면도이고,1 is a cross-sectional view showing the general structure of a typical MFS-FET,
도 2는 본 발명에 따른 MFS-FET의 대략적인 구조를 나타내는 단면도이다.2 is a cross-sectional view showing the schematic structure of the MFS-FET according to the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
1. Si 기판2. 소스Si substrate 2. sauce
3. 드레인4. 강유전체층Drain 4. Ferroelectric layer
5. Pt 전극5. Pt electrode
11. Si 기판12. 소스Si substrate 12. sauce
13. 드레인14a. CBN 제1강유전체 버퍼층13. Drain 14a. CBN first ferroelectric buffer layer
14b. SBT 제2강유전체층15. Pt 전극14b. SBT Second Ferroelectric Layer 15. Pt electrode
상기와 같은 목적을 달성하기 위하여 본 발명에 따른 금속-강유전체-반도체 전계 효과 트랜지스터는, 불순물 도핑에 의해 형성된 소스 및 드레인 구비된 실리콘 기판; 상기 소스 및 드레인 사이의 실리콘 기판에 형성된 통전용 채널 상에 형성된 게이트 절연물로서 형성된 강유전체층; 및 상기 강유전체층 상에 금속 전극으로 형성된 게이트;를 구비하여 된 금속-강유전체-반도체 전계 효과 트랜지스터에 있어서, 상기 강유전체층은 CBN으로 형성된 제1강유전체 버퍼층; 및 상기 제1강유전체층 상에 PZT로 형성된 제2강유전체층;을 구비하여 된 것을 특징으로 한다.In order to achieve the above object, a metal-ferroelectric-semiconductor field effect transistor according to the present invention comprises a silicon substrate having a source and a drain formed by impurity doping; A ferroelectric layer formed as a gate insulator formed on a conductive channel formed in the silicon substrate between the source and drain; And a gate formed of a metal electrode on the ferroelectric layer. The metal-ferroelectric-semiconductor field effect transistor comprising: a first ferroelectric buffer layer formed of CBN; And a second ferroelectric layer formed of PZT on the first ferroelectric layer.
본 발명에 있어서, 상기 제2강유전체층은 상기 CBN 버퍼층과의 격자 상수을 일치시키기 위하여 PZT 보다 SBT로 형성하는 것이 더욱 바람직하며, 또한,상기 강유전체층을 SBT/CBN의 다중층으로 형성함에 있어서, 대면적의 증착에 유리한 솔-겔(Sol-Gel)법을 이용하는 것이 더욱 바람직하다.In the present invention, the second ferroelectric layer is more preferably formed of SBT than PZT in order to match the lattice constant with the CBN buffer layer, and furthermore, in forming the ferroelectric layer as a multilayer of SBT / CBN, It is more preferable to use the Sol-Gel method which is advantageous for the deposition of the area.
이하 도면을 참조하면서 본 발명에 따른 금속-강유전체-반도체 전계 효과 트랜지스터(MFS FET)를 설명한다.Hereinafter, a metal-ferroelectric-semiconductor field effect transistor (MFS FET) according to the present invention will be described with reference to the drawings.
도 2는 본 발명에 따른 MFS-FET의 대략적인 구조를 나타내는 단면도이다. 도시된 바와 같이, 본 발명에 따른 MFS-FET는, 실제 PZT 또는 SBT와 같은 강유전체를 실리콘 위에 바로 증착하기가 어렵다는 사실을 극복하기 위하여, 실리콘과 반응층을 형성하지 않는다고 알려진 CaBi2Nb2O9(CBN) 강유전체를 실리콘(11)과 SrBi2Ta2O9(SBT) 강유전체(14b) 사이의 버퍼층(14a; buffer layer)으로 사용한다. 이와 같이 할 경우 강유전체와 실리콘과의 반응층의 형성을 억제하는 동시에 그 자체가 강유전체인 버퍼층(14a)을 이용함으로서 강유전체 게이트 산화물(gate oxide)에 의한 트랜지스터의 동작을 보다 효과적으로 구현할 수 있다. 즉 이는 순수한 MFS 구조에 근접하는 구조를 이루게 하는 방법이다. 현재 문헌상으로는 CBN과 SBT를 실리콘 위에 직접 증착하는 것에 대한 내용이 "Hae-Seok Cho, Seshu B. Desu Appl. Phys. Lett. 1996 (to be submitted)"에 의해 보고되고 있으나 이들의 다중층화된 강유전체(mutilayered ferroelectric) 구조에 의한 것은 전혀 언급된 바가 없다. 또한 상기 저자의 경우에는 증착방법으로 Pulsed Laser Deposition (PLD)을 사용하였으나 본 발명에서는 CBN과 SBT 양자를 모두 솔-겔(Sol-Gel)법에 의해 증착한다. 이 방법에 대한 보고는 아직 나와있지 않다. 한편, PLD에 의한 증착 방법도 적용 가능하지만 막의 균일도(uniformity)가 좋지 못하여 대면적의 증착이 어렵다.2 is a cross-sectional view showing the schematic structure of the MFS-FET according to the present invention. As illustrated, MFS-FET according to the present invention, the right to deposit the ferroelectric lifelike PZT or SBT on the silicon does in order to overcome the difficulties in fact, to form silicon and the reaction layer known CaBi 2 Nb 2 O 9 A (CBN) ferroelectric is used as the buffer layer 14a between the silicon 11 and the SrBi 2 Ta 2 O 9 (SBT) ferroelectric 14b. In this case, the operation of the transistor by the ferroelectric gate oxide can be more effectively implemented by suppressing the formation of the reaction layer between the ferroelectric and silicon, and by using the buffer layer 14a which is itself a ferroelectric. In other words, this is a way to achieve a structure close to the pure MFS structure. Currently, literature on the direct deposition of CBN and SBT onto silicon is reported by "Hae-Seok Cho, Seshu B. Desu Appl. Phys. Lett. 1996 (to be submitted)", but their multilayered ferroelectrics No mention has been made of mutilayered ferroelectric structures. In addition, in the case of the author, Pulsed Laser Deposition (PLD) was used as the deposition method, but in the present invention, both CBN and SBT are deposited by the Sol-Gel method. There are no reports of this method yet. On the other hand, the deposition method by PLD is also applicable, but the uniformity of the film is not good, so that the deposition of a large area is difficult.
이상과 같은 구조의 MFS FET의 제조 방법은 불순물 도핑에 의해 소스(12) 및 드레인(13)이 형성된 실리콘 기판(11)의 채널(11') 상부에 게이트 산화물(gate oxide)로 강유전체층을 증착하되, Si 기판(11)과의 반응이 없는 것으로 알려진 CaBi2Nb2O9(CBN) 강유전성 물질을 Sol-Gel법에 의해 약 500Å의 얇은 박막으로 증착한다. 다음에 SrBi2Ta2O9(SBT) 강유전성 물질을 역시 Sol-Gel법으로 증착하여 제2강유전체층(14b)을 형성한다. 다음에, SBT 제2강유전체층(14b) 상에 Pt 전극(15)을 형성하여 MFS-FET의 구조를 완성한다. 여기서, 제2강유전체층(14b)의 물질로 PZT 강유전체 물질을 사용하는 것도 무방하나 CBN 버퍼층(14a)과의 격자 상수 매칭을 위하여 SBT를 사용하는 것이 바람직하다. 결론적으로, Pt/SBT/CBN/Si의 구조로 구성되는 MFS-FET의 게이트 강유전성 산화물(gate ferroelectric oxide)에서 CBN이 버퍼층으로 사용되며, SBT/CBN 층들을 Sol-Gel법으로 형성하는 것이 본 발명의 요지이다. 이러한 구조와 제조 방법을 이용할 경우 MFS-FET 구조를 용이하게 실현할 수 있으며, 이로부터 단일 트랜지스터(single transistor)로 구성된 메모리 소자를 집적할 경우 캐패시터와 트랜지스터로 구성된 일반적인 구조의 메모리 소자에 비해 더욱 큰 초고집적화를 구현시킬 수 있다. 또한 Sol-Gel법을 이용함으로써 대면적의 균일한 증착이 가능하므로 실제 반도체 소자을 양산할 수 있게 된다.In the manufacturing method of the MFS FET having the above structure, the ferroelectric layer is deposited with a gate oxide on the channel 11 'of the silicon substrate 11 on which the source 12 and the drain 13 are formed by impurity doping. However, a CaBi 2 Nb 2 O 9 (CBN) ferroelectric material, which is known to have no reaction with the Si substrate 11, is deposited in a thin thin film of about 500 mW by the Sol-Gel method. Next, an SrBi 2 Ta 2 O 9 (SBT) ferroelectric material is also deposited by the Sol-Gel method to form the second ferroelectric layer 14b. Next, a Pt electrode 15 is formed on the SBT second ferroelectric layer 14b to complete the structure of the MFS-FET. Here, although the PZT ferroelectric material may be used as the material of the second ferroelectric layer 14b, it is preferable to use SBT for lattice constant matching with the CBN buffer layer 14a. In conclusion, CBN is used as a buffer layer in the gate ferroelectric oxide of MFS-FET having a structure of Pt / SBT / CBN / Si, and the SBT / CBN layers are formed by the Sol-Gel method. It is the gist of. Using this structure and manufacturing method, the MFS-FET structure can be easily realized, and from this, when integrating a memory device composed of a single transistor, it is much larger than a memory device having a general structure composed of a capacitor and a transistor. High integration can be achieved. In addition, since the large-area uniform deposition is possible by using the Sol-Gel method, actual semiconductor devices can be mass-produced.
실제로, CBN 강유전체는 비록 실리콘과 반응하지는 않으나 그 강유전성이 PZT 또는 SBT에 비해 좋지 못하여 MFS-FET의 게이트 산화물로 쓰기에는 한계가 있다. 그러므로 이를 강유전체 버퍼층으로 가능한한 얇게 형성하고, 그 위에 강유전성이 우수한 SBT 혹은 PZT를 사용함으로써, 실리콘층과의 계면에서 반응층은 형성하지 않으면서 보다 나은 강유전성의 강유전체층을 형성하게 되었다.Indeed, although CBN ferroelectrics do not react with silicon, their ferroelectricity is not as good as that of PZT or SBT, which limits their use as gate oxides in MFS-FETs. Therefore, by forming it as thin as a ferroelectric buffer layer and using SBT or PZT having excellent ferroelectricity on it, a better ferroelectric ferroelectric layer can be formed without forming a reaction layer at the interface with the silicon layer.
실시예를 소개하면 다음과 같다.An embodiment is as follows.
소스 및 드레인이 형성된 실리콘 기판의 채널 상에 약 500Å 정도의 얇은 두께의 CBN 강유전체층을, 도 2에 도시된 바와 같이, Sol-Gel법으로 증착하고, 그 위에 다시 보다 강유전성 본연의 분극 특성이 우수하고 피로(fatigue) 특성이 우수한 SBT 강유전체를 역시 Sol-Gel법으로 약 1600Å 정도의 두께로 증착하였다. 이와 같이 함으로써, CBN과 실리콘 및 SBT 간의 상호 격자 부정합(lattice mismatch)이 적어 결함 발생을 줄일 수 있었다. 또한, 이와 같은 이중층 구조(Bi-layered structure)인 CBN과 SBT 박막을 다중층 강유전체 구조(multilayered ferroelectric structure)로 형성하여 이용하는 것도 용이하다.A thin CBN ferroelectric layer having a thickness of about 500 GPa is deposited on the channel of the silicon substrate on which the source and the drain are formed, by the Sol-Gel method, as shown in FIG. 2, and further superior ferroelectric intrinsic polarization characteristics thereon. And the SBT ferroelectric with excellent fatigue characteristics was also deposited to a thickness of about 1600G by the Sol-Gel method. In this way, the lattice mismatch between CBN, silicon, and SBT is small, and defect occurrence can be reduced. In addition, the CBN and SBT thin films, which are such bi-layered structures, may be easily formed into a multilayer ferroelectric structure.
이상 설명한 바와 같이, 본 발명에 따른 MFS FET는 구조적으로 강유전체 게이트 산화물로서 실리콘과의 반응층의 형성없는 CBN 강유전체를 이용하여 실리콘층 상에 직접 증착하고, 그 위에 강유전성이 우수한 SBN 강유전체를 증착함으로써, 격자 부정합(lattice mismatch)이 거의 없는 소자의 제작이 가능한다. 또한, 층 구조 물질(layered structure material)에서 결정의 방향성에 의해 크게 영향을 받는 전기적 성질을 고려해 볼 때 유리한 C-axis로 방향성을 가진 박막을 성장시키기가 쉽다.As described above, the MFS FET according to the present invention is deposited directly on the silicon layer using a CBN ferroelectric structurally without formation of a reaction layer with silicon as a ferroelectric gate oxide, and by depositing an SBN ferroelectric having excellent ferroelectricity thereon, It is possible to fabricate devices with little lattice mismatch. In addition, it is easy to grow oriented thin films with an advantageous C-axis in view of the electrical properties greatly influenced by the crystal orientation in layered structure materials.
또한 MFIS 구조, 즉 Metal-Ferroelectric-Insulator-Semiconductor 구조에 비해 이 CBN 버퍼층 자체가 갖는 강유전성으로 인해 소자 작동상 유리하게 되어 있다. 한편 제조 방법에 있어서는 현재 CBN, SBT 각각의 물질에 대해 사용한 것이 보고되는 PLD에 의한 증착방법에 비해 대면적에 대한 박막 균일도(uniformity)가 좋기 때문에 웨이퍼 개념의 제조 개념에 더욱 부합된다.In addition, the ferroelectricity of the CBN buffer layer itself is advantageous to device operation compared to the MFIS structure, that is, the metal-ferroelectric-insulator-semiconductor structure. On the other hand, the manufacturing method is more consistent with the manufacturing concept of the wafer concept because the thin film uniformity of the large area is better than that of the PLD deposition method, which is currently used for each material of CBN and SBT.
Claims (4)
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| CN109970443A (en) * | 2019-04-25 | 2019-07-05 | 广州光鼎科技集团有限公司 | A kind of rubidium, cerium codope bismuth niobate calcium base high-temperature piezoelectric ceramics and preparation method thereof |
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| JPH05235370A (en) * | 1992-02-24 | 1993-09-10 | Rohm Co Ltd | Field effect transistor |
| JPH08274195A (en) * | 1995-03-30 | 1996-10-18 | Mitsubishi Chem Corp | Ferroelectric fet element |
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| JPH05235370A (en) * | 1992-02-24 | 1993-09-10 | Rohm Co Ltd | Field effect transistor |
| JPH08274195A (en) * | 1995-03-30 | 1996-10-18 | Mitsubishi Chem Corp | Ferroelectric fet element |
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| CN109970443A (en) * | 2019-04-25 | 2019-07-05 | 广州光鼎科技集团有限公司 | A kind of rubidium, cerium codope bismuth niobate calcium base high-temperature piezoelectric ceramics and preparation method thereof |
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