CN115224191A - A ferroelectric superlattice multivalued memory device and method of making the same - Google Patents

Abstract

The invention discloses a ferroelectric superlattice multi-value memory and a manufacturing method thereof, comprising a substrate with a source electrode, a drain electrode and a gate window composed of the source electrode and the drain electrode on the substrate; It has a ferroelectric superlattice structure. The ferroelectric superlattice structure is composed of multiple layers of ferroelectric layers and channel layers. The source and drain electrodes are in terminal contact with the ferroelectric superlattice structure; on the ferroelectric superlattice structure A gate dielectric layer is provided, and a gate electrode is provided on the gate dielectric layer. The invention realizes the multi-value memory by adopting the multi-value memory realized by the two-dimensional ferroelectric superlattice, improves the operation efficiency of the data, and further realizes the high-density storage of the data, and has a wide application prospect.

Description

A ferroelectric superlattice multi-value memory device and method of making the same

technical field

The invention relates to a ferroelectric superlattice storage device, in particular to a ferroelectric superlattice multi-value storage device and a manufacturing method thereof.

Background technique

Multi-value storage can store multiple values, improve the adjustment range of weight parameters in the weight matrix network, and facilitate the realization of complex calculations in artificial neural networks. Since 2D transition metal dichalcogenides (TMDs) have no dangling bonds, atomic thickness, and excellent electrostatic control ability, and molybdenum sulfide (MoS ₂ ) is a typical representative, it has a suitable band gap (1.2ev for monolayer), The high switching ratio (I _ON /I _OFF ≈ ^{10 8} ) facilitates scaling down of device size and is a powerful choice for low-power storage and logic circuits.

Compared with Flash (industry), the biggest advantage of ferroelectric storage is that the speed is improved by three orders of magnitude. Ferroelectric memory advantages: (1) high-speed erasing and writing (nanosecond level), non-destructive reading (2) durability (more than 10 years), high reliability (polarization stability), low power consumption, easy for high-density integration . At present, the storage capacity of ferroelectric memory is not high, and the integration level is not high, and it cannot reach the commercial level comparable to Flash flash memory. Moreover, the structure and function are relatively simple, and can only store low-capacity data; and at present, a single device of ferroelectric memory can only store one bit of binary data, and cannot realize multi-value storage.

SUMMARY OF THE INVENTION

The embodiment of the present invention proposes a multi-value memory realized by using a two-dimensional ferroelectric superlattice. A first aspect of the present invention provides a ferroelectric superlattice multi-value storage device:

There is a substrate with a source electrode, a drain electrode and a gate window composed of the source electrode and the drain electrode on the substrate;

The above-mentioned gate window has a ferroelectric superlattice structure, the above-mentioned ferroelectric superlattice structure is composed of multiple layers of ferroelectric layers and a channel layer, and the above-mentioned source electrode and the above-mentioned drain electrode and the above-mentioned ferroelectric superlattice structure are terminal type touch;

The ferroelectric superlattice structure has a gate dielectric layer thereon, and the gate dielectric layer has a gate electrode.

In an embodiment of the first aspect of the present invention, the ferroelectric layer is selected from copper indium thiophosphate (CIPS) or hafnium zirconium oxide (HZO).

In an embodiment of the first aspect of the present invention, the channel layer is selected from molybdenum sulfide or carbon nanotubes.

In an embodiment of the first aspect of the present invention, the gate dielectric layer is selected from SiO ₂ , Si ₃ N ₄ , HfO ₂ or hexagonal boron nitride.

In a second aspect, the present invention provides a method for fabricating a ferroelectric superlattice multi-value memory device, comprising the following steps: providing a substrate, and growing a ferroelectric superlattice structure on the substrate;

patterning the above-mentioned ferroelectric superlattice structure to define an active region;

A source electrode and a drain electrode are respectively formed on both sides of the above-mentioned active region;

A high-k gate oxide layer and gate are formed over the above-mentioned active regions.

In an embodiment of the second aspect of the present invention, the above-mentioned ferroelectric superlattice structure is formed by alternately growing the channel layer and the ferroelectric layer multiple times.

In an embodiment of the second aspect of the present invention, the above-mentioned channel layer is formed by growing 1-5 layers of molybdenum sulfide by CVD, ALD or MBE.

In an embodiment of the second aspect of the present invention, the ferroelectric layer is formed by growing 1-20 nm of copper indium thiophosphate (CIPS) by CVD, ALD or MBE.

In an embodiment of the second aspect of the present invention, a 1-10 nm high-k gate dielectric layer is grown by ALD.

In an embodiment of the second aspect of the present invention, the above-mentioned source electrode and the above-mentioned drain electrode are formed by PVD.

The invention realizes the multi-value memory through the two-dimensional ferroelectric superlattice structure, improves the operation efficiency of the data, and realizes the high-density storage of the data; and can also be used as the underlying unit in the memory-computing integrated neural network.

Description of drawings

The present invention can be better understood from the following description of specific embodiments of the invention in conjunction with the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar features.

1 is a schematic diagram of a ferroelectric superlattice multi-value memory according to an embodiment of the present invention;

2 is a transfer characteristic curve of a ferroelectric superlattice multi-valued memory according to an embodiment of the present invention;

3 is a schematic diagram of the principle of a ferroelectric superlattice multi-valued memory according to an embodiment of the present invention;

Figure 4 is a ferroelectric superlattice structure and a silicon nitride layer formed on a substrate;

Figure 5 is the active region defined by photolithography and ICP etching;

FIG. 6 is for forming a source-drain metal layer;

Fig. 7 is the formation of silicon oxide layer;

8 is a CMP silicon oxide layer;

FIG. 9 is the removal of silicon nitride to expose the ferroelectric superlattice active layer;

Figure 10 is a high-k gate dielectric layer;

Figure 11 is a photolithography patterned gate;

FIG. 12 is the formation of a silicon nitride mask layer;

Figure 13 shows the formation of a patterned tungsten column and the completion of peripheral connections;

Detailed ways

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the various figures, the same elements are designated by the same reference numerals, and the various parts of the figures are not drawn to scale. Additionally, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be depicted in one figure.

It will be understood that, in describing the structure of a device, when a layer or region is referred to as being "on" or "over" another layer or region, it can be directly on the other layer or region, or Other layers or regions are also included between it and another layer, another region. And, if the device is turned over, the layer, one region, will be "under" or "under" another layer, another region.

In order to describe the situation directly above another layer, another area, the expression "A is directly above B" or "A is above and adjacent to B" will be used herein. In this application, "A is located directly in B" means that A is located in B, and A is directly adjacent to B, rather than A located in a doped region formed in B.

FIG. 1 is a schematic diagram of a ferroelectric superlattice multi-valued memory according to an embodiment of the present invention. It can be seen from the figure that there is a substrate (not shown in the figure), on the substrate there is a source electrode 1, a drain electrode 2 and a gate window composed of the source electrode 1 and the drain electrode 2; there is iron in the gate window Electric superlattice structure, ferroelectric superlattice structure is composed of multi-layer channel layer 3 and ferroelectric layer 4, wherein channel layer 3 can be selected from molybdenum sulfide or carbon nanotube, in this embodiment, molybdenum sulfide ( MoS ₂ ) as the channel layer. The ferroelectric layer is selected from copper indium thiophosphate (CIPS) or hafnium zirconium oxide (HZO). In this embodiment, copper indium thiophosphate (CIPS) is used as the ferroelectric layer. The ferroelectric superlattice has a MoS ₂ /CIPS structure of at least 3 periods, and 3 periods are used in this example. Generally, the contact between metal and semiconductor is divided into side contact (Side-Contact) and end-contact (End-Contact). The metal electrode of the side contact is parallel to the semiconductor material, and the metal electrode of the end contact is perpendicular to the semiconductor material. The source electrode 1 and the drain electrode 2 are in terminal contact with the above-mentioned ferroelectric superlattice structure. The source and drain metals can be Ti, Pd, Au, TiN and the like. A high-k gate dielectric layer 5 and a gate 6 are formed on the ferroelectric superlattice structure, wherein the high-k gate dielectric layer 5 can be any high-k dielectric, for example, can be selected from SiO ₂ , Si ₃ N ₄ , HfO ₂ or hexagonal boron nitride (h-bn), in this embodiment hexagonal boron nitride (h-bn) is used. The gate 6 may be a Ti or Au electrode.

By applying a voltage to the gate of the ferroelectric superlattice multi-value memory of the embodiment of the present invention, the polarization of CIPS ferroelectric materials with different layers is reversed, and different partners form inversion layers or depletion layers of MoS ₂ , The more inversion layers, the larger the on-current or the conductance value, thereby realizing multi-value storage. The working principle of the ferroelectric superlattice multi-value memory according to the embodiment of the present invention will be described in detail below with reference to FIG. 2 and FIG. 3 , taking an NMOS device having a three-layer channel as an example. FIG. 2 is a schematic diagram of the electrical characteristics of the multi-value storage of the device, the abscissa represents the gate voltage applied to the device, and the ordinate represents the drain current. Fig. 3-a to Fig. 3-g show in detail the working principles of data writing and data erasing in the embodiment of the present invention, wherein Fig. 3-a is the initial state of the device, assuming that the initial polarization directions of the ferroelectric layer CIPS are all upward , because no voltage is applied to the gate, the three layers of molybdenum sulfide are all depletion layers, the device is blocked, the current is "0", and no data is written, which corresponds to the curve state (1) in Figure 2. During data writing, as shown in Figure 3-b, when a small positive voltage is applied to the gate, the electric field strength is only enough to flip the uppermost CIPS, and then only reaches the corresponding lower MoS ₂ to form an inversion layer. The data "1" corresponds to the curve state (2) in Figure 2; as shown in Figure 3-c, when the positive voltage applied to the gate is increased, the electric field strength makes the two layers of CIPS flip, and then the MoS corresponding to the two layers is reached. ₂ forms an inversion layer, and then writes data "2", and the current rises to "2", which corresponds to the curve state (3) in FIG. 2 . As shown in Figure 3-d, when the positive voltage applied to the gate continues to increase, the polarization of all CIPS is finally reversed, and all the corresponding layers of MoS ₂ form an inversion layer, the data "3" is written, and the current rises to "3" ”, corresponding to the curve state (4) in Figure 2, the memory space is full. When erasing data, it is assumed that the initial state memory storage space is full and the stored data is "3", as shown in Figure 3-d, and data erasing is performed on this basis. As shown in Figure 3-e, by applying a small negative voltage to the gate, the electric field strength is only enough to flip the uppermost layer of CIPS, and then only reaches the corresponding lower layer of MoS ₂ to form a depletion layer. After partial erasing, the data becomes "2", corresponding to the curve state (5) in Figure 2. As shown in Figure 3-f, when the negative voltage applied to the gate is increased, the electric field strength is enough to flip the two layers of CIPS, and then reach the corresponding lower layer of MoS ₂ to form a depletion layer. After erasing, the data becomes "1", Corresponds to the curve state (6) in FIG. 2 . Further as shown in Fig. 3-g, when the negative voltage at the gate is large enough, the electric field strength is enough to make all CIPS polarizations flip, and then reach all MoS ₂ layers to form a depletion layer, the data is completely erased, and the current drops to 0 , return to the initial curve state (7).

In another embodiment of the present invention, the process steps of the ferroelectric superlattice multi-value memory of the present invention are described, as shown in FIGS. 4-13 . First, as shown in FIG. 4 , a wafer 101 is provided as a substrate, and the substrate can be sapphire, silicon oxide, silicon nitride, etc. In this embodiment, a silicon oxide substrate is used. Then, about 1-5 layers of molybdenum sulfide (MoS ₂ ) channel layer 102 are grown on the wafer 101 by chemical vapor deposition. In other embodiments, atomic layer deposition (ALD) or molecular beam epitaxy (MBE) can also be used. ) to grow the above molybdenum sulfide channel layer. Then, a 1-20 nm copper indium thiophosphate (CIPS) ferroelectric layer 103 is further grown on the molybdenum sulfide channel layer by chemical vapor deposition (CVD). In other embodiments, atomic layer deposition (ALD) can also be used. ) or molecular beam epitaxy (MBE) to grow the above-mentioned CIPS ferroelectric layer. A ferroelectric superlattice structure is formed by alternately growing the above-described molybdenum sulfide channel layer 102 and copper indium thiophosphate (CIPS) ferroelectric layer 103 multiple times. In this embodiment, the molybdenum sulfide channel layer 102 and the copper indium thiophosphate (CIPS) ferroelectric layer 103 are three layers. A silicon nitride layer 104 is then deposited on the above-mentioned ferroelectric superlattice structure by chemical vapor deposition or plasma chemical vapor deposition.

Further as shown in FIG. 5 , the silicon nitride layer 104 is patterned by photolithography to define an active region, and then the ferroelectric superlattice is further etched by IPC using the silicon nitride as a mask to form an active region. Then, as shown in FIG. 6 , a source-drain contact metal layer 105 is deposited on the active region by PVD. In this embodiment, Ti is used as the source-drain contact metal. In other embodiments, Pd and Au may be used. , TiN and other metals. Further, a silicon oxide layer 106 is deposited on the source-drain contact metal layer 105 by CVD, and thermal annealing is performed to improve the terminal contact of the source-drain metal. Next, CMP is performed on the silicon oxide 106 to expose the silicon nitride layer 104 on top of the active layer, and then the silicon nitride layer 104 is removed with hot phosphoric acid to expose the ferroelectric superlattice structure. Further, a high-k gate dielectric layer 107 of 1-10 nm is deposited on the above structure by ALD. In this embodiment, the high-k gate dielectric layer 107 is hafnium oxide. In other embodiments, aluminum oxide, silicon nitride, etc. can be used as the High-k gate dielectric layer. Then, the high-k gate dielectric layer 107 is further patterned by photolithography, and a metal gate 108 is formed on the high-k gate dielectric layer 107 through a metal deposition + etching patterning process. In this embodiment, the metal gate 108 is Ti Metal gate.

Further, a layer of silicon nitride mask layer 109 is formed on the structure formed in the above steps by CVD or PECVD, and a through hole pattern is defined, and then a connecting through hole is etched by ICP, and formed by sputtering in the through hole by PVD The tungsten column 110 is formed, and the peripheral connection lines are completed, thereby forming the ferroelectric superlattice multi-value memory according to the embodiment of the present invention.

The manufacturing process of the ferroelectric superlattice multi-value memory in the embodiment of the present invention is compatible with the traditional integrated circuit process. At the same time, the ferroelectric materials and channel materials required in the superlattice structure can be obtained by CVD/ALD/MBE methods. growth for ease of device integration and mass production. The CVD silicon oxide mask in the process is beneficial to protect the terminal core contact metal and maintain the stability of the superlattice structure during the device fabrication process.

Although the present invention has been described in detail above with general description and specific embodiments, some modifications or improvements can be made on the basis of the present invention, which is obvious to those skilled in the art. Therefore, these modifications or improvements made without departing from the spirit of the present invention fall within the scope of the claimed protection of the present invention.

Claims (10)

1. A ferroelectric superlattice multivalued memory device, characterized in that:

the transistor comprises a substrate, a source electrode, a drain electrode and a grid window consisting of the source electrode and the drain electrode, wherein the substrate is provided with the source electrode and the drain electrode;

the gate window is provided with a ferroelectric superlattice structure, the ferroelectric superlattice structure consists of a plurality of ferroelectric layers and a channel layer, and the source electrode and the drain electrode are in end-type contact with the ferroelectric superlattice structure;

the ferroelectric superlattice structure is provided with a gate dielectric layer, and the gate dielectric layer is provided with a gate.

2. A ferroelectric superlattice multivalued memory device as recited in claim 1, wherein said ferroelectric layer is selected from copper indium thiophosphate (CIPS) or Hafnium Zirconium Oxide (HZO).

3. A ferroelectric superlattice multivalued memory device as recited in claim 1, wherein said channel layer is selected from molybdenum sulfide or carbon nanotubes.

4. A ferroelectric superlattice multivalued memory device as recited in claim 1, wherein said gate dielectric layer is selected from the group consisting of SiO ₂ 、Si ₃ N ₄ 、HfO ₂ Or hexagonal boron nitride.

5. A method of fabricating a ferroelectric superlattice multivalued memory device as claimed in any one of claims 1-4, characterized by comprising the steps of:

providing a substrate, and growing a ferroelectric superlattice structure on the substrate;

patterning the ferroelectric superlattice structure to define an active region;

forming a source electrode and a drain electrode on two sides of the active region respectively;

and forming a high-k gate dielectric layer and a gate above the active region.

6. A method of fabricating a ferroelectric superlattice multivalued memory device as claimed in claim 5, wherein said ferroelectric superlattice structure is formed by alternately growing a channel layer and a ferroelectric layer a plurality of times.

7. A method of fabricating a ferroelectric superlattice multi-value memory device as in claim 6, wherein said channel layer is formed by growing 1-5 layers of molybdenum sulfide by CVD, ALD or MBE.

8. A method of fabricating a ferroelectric superlattice multivalued memory device as claimed in claim 6, wherein said ferroelectric layer is formed by growing 1-20nm copper indium thiophosphate (CIPS) by CVD, ALD or MBE.

9. A method of fabricating a ferroelectric superlattice multivalued memory device as in claim 5, wherein a 1-10nm high-k gate dielectric layer is grown by ALD.

10. A method of fabricating a ferroelectric superlattice multivalued memory device as claimed in claim 5, wherein said source electrode and said drain electrode are formed by PVD.

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