JPH08264705A - Semiconductor device and package structure and packaging method using the same - Google Patents

Semiconductor device and package structure and packaging method using the same

Info

Publication number
JPH08264705A
JPH08264705A JP7069689A JP6968995A JPH08264705A JP H08264705 A JPH08264705 A JP H08264705A JP 7069689 A JP7069689 A JP 7069689A JP 6968995 A JP6968995 A JP 6968995A JP H08264705 A JPH08264705 A JP H08264705A
Authority
JP
Japan
Prior art keywords
semiconductor device
external connection
connection terminals
substrate
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7069689A
Other languages
Japanese (ja)
Inventor
Akihiro Murata
昭浩 村田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP7069689A priority Critical patent/JPH08264705A/en
Publication of JPH08264705A publication Critical patent/JPH08264705A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Abstract

PURPOSE: To reduce sharply the thickness of a semiconductor package at the time of mounting a board, to make a pitch interval of external connection terminals small and to attain ultra-high density packaging by providing cuts (noches) in external connection terminal parts of a lead time. CONSTITUTION: A semiconductor package is of a type wherein a semiconductor element is sealed with molding resin and wherein external connection terminals 12 are led outside the mounting resin being a sealing part. In these external connection terminals 12 of a lead frame, cuts (notch parts) 14 are provided at an interval of 0.5-3.5mm and external leads can be bent arbitrarily at the notch parts 14 as the starting points of bending. First external connection terminals and second external connection terminals bent upward and downward and in the shape of L respectively are shown in the Fig. According to this constitution, packaging of a semiconductor device on a board for packaging thereof can be simplified.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置及びそれを用
いた実装構造及び実装方法に関するものであり、更に詳
しくは封止部から突出した外部接続端子に特徴を有する
半導体装置及びそれを用いた実装構造及び実装方法に関
するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a mounting structure and a mounting method using the same, and more specifically, a semiconductor device characterized by external connection terminals protruding from a sealing portion and the semiconductor device using the same. The present invention relates to a mounting structure and a mounting method.

【0002】[0002]

【従来の技術】以下は半導体素子の封止を行う際に、封
止構造の一例としてレジンモールド型半導体装置を例に
あげ、説明することとする。
2. Description of the Related Art A resin mold type semiconductor device will be described below as an example of a sealing structure when a semiconductor element is sealed.

【0003】レジンモールド型半導体装置の組立には図
5に示す様な半導体装置用リードフレームが用いられ
る。
A lead frame for a semiconductor device as shown in FIG. 5 is used for assembling a resin mold type semiconductor device.

【0004】図5(a)が平面図、図5(b)が平面図
をA−A断面で切断した断面図である。この半導体装置
用リードフレーム1は金属薄板をエッチングあるいはプ
レス加工による打ち抜きによって部分的に除去して形成
する。
FIG. 5 (a) is a plan view, and FIG. 5 (b) is a sectional view taken along the line AA of the plan view. The lead frame 1 for a semiconductor device is formed by partially removing a thin metal plate by etching or punching by pressing.

【0005】構造的には半導体装置用リードフレーム1
は矩形枠からなるフレーム外枠2を有し、このフレーム
外枠2の略中央に半導体回路素子をとりつける矩形のダ
イパッド3を有している。さらにダイパッド3は、タブ
吊りリード4によってフレーム枠2に支持されている。
またフレーム外枠2の内側からは多数の細い内部リード
5が、前記ダイパッド3に向かって延在しており、各内
部リード5はレジンモールド時にレジン流出を防止する
ダムバー6で支持されている。このダムバー6は補強部
材ともなっている。
Structurally, a semiconductor device lead frame 1
Has a frame outer frame 2 formed of a rectangular frame, and has a rectangular die pad 3 to which a semiconductor circuit element is attached at substantially the center of the frame outer frame 2. Further, the die pad 3 is supported by the frame frame 2 by the tab suspension leads 4.
A large number of thin inner leads 5 extend toward the die pad 3 from the inside of the frame outer frame 2, and each inner lead 5 is supported by a dam bar 6 that prevents resin from flowing out during resin molding. The dam bar 6 also serves as a reinforcing member.

【0006】このような半導体装置用リードフレーム1
にあっては、ダイパッド3上に半導体回路素子7を固定
した後、半導体回路素子7の各電極10と、これらの電
極に対応するリード5の内端とを金属細線8等の接続手
段にて接続し、その後、ダムバー6の近傍の内側のモー
ルド領域9をモールドレジンと呼ばれる樹脂でモールド
し、半導体装置のレジン部分で回路素子7,ワイヤ8,
内部リード5を被う。
[0006] Such a semiconductor device lead frame 1
In this case, after fixing the semiconductor circuit element 7 on the die pad 3, each electrode 10 of the semiconductor circuit element 7 and the inner end of the lead 5 corresponding to these electrodes are connected by a connecting means such as a thin metal wire 8. After that, the inner mold region 9 near the dam bar 6 is molded with a resin called a mold resin, and the circuit element 7, the wire 8,
Cover the inner lead 5.

【0007】次に前記半導体装置の実装方法及び実装す
る基板について説明する。
Next, a method of mounting the semiconductor device and a substrate to be mounted will be described.

【0008】図6は従来の半導体装置用実装基板の説明
図である。図6(a)が平面図、図6(b)が基板をB
−B断面で切断した断面図である。
FIG. 6 is an explanatory view of a conventional semiconductor device mounting substrate. 6A is a plan view, and FIG. 6B is a substrate B.
It is sectional drawing cut | disconnected by the B cross section.

【0009】まず、半導体装置用パッケージ20を基板
30上へ裁置する、この時外部接続端子12をランド3
1へ合わせて裁置する。そして、半田を溶融させ外部接
続端子12とランド31とを電気的及び機械的に接続し
固定する。本説明図では基板の表裏両面に実装したタイ
プ(両面実装タイプ)の一例を示した。本図での半導体
装置は従来の半導体装置の一例として半導体装置のボデ
ィー部分からガルウイング形状の外部接続端子が四方向
に出ているQFP(クワッド・フラット・パッケージ)
タイプのものを図に示している。従来の半導体装置では
本図のように一つの半導体装置で外部接続端子が基板に
対して片側のみの接続が可能となっており、基板の表裏
両面に実装する際は2つ以上の半導体装置が必要であ
る。
First, the semiconductor device package 20 is placed on the substrate 30. At this time, the external connection terminals 12 are connected to the lands 3.
Put it according to 1. Then, the solder is melted to electrically and mechanically connect and fix the external connection terminal 12 and the land 31. In this explanatory view, an example of a type (double-sided mounting type) mounted on both front and back surfaces of the substrate is shown. The semiconductor device shown in this figure is a QFP (quad flat package) in which gull wing-shaped external connection terminals are projected in four directions from the body portion of the semiconductor device as an example of a conventional semiconductor device.
The type is shown in the figure. In the conventional semiconductor device, as shown in the figure, one semiconductor device can connect the external connection terminal to only one side of the board. When mounting on both front and back surfaces of the board, two or more semiconductor devices are connected. is necessary.

【0010】[0010]

【発明が解決しようとする課題】現在、上記のようなレ
ジンモールドされた半導体パッケージに於いては実際の
使用の際に基板の片面のみ使用して実装したり、あるい
は高集積化の狙いで基板の両方の面に半導体装置用パッ
ケージを両面実装したりしていた。しかしながらこれら
の方法であると実装された基板はパッケージを搭載する
事により厚みがパッケージの分だけ厚くなってしまう欠
点があった。また外部接続端子のピッチは半導体装置用
基板のランド31もピッチによって規定されてしまい外
部接続端子数の高密度化が難しかった。
At present, in the resin-molded semiconductor package as described above, only one side of the substrate is used for mounting in actual use, or the substrate is intended for high integration. Both sides of the semiconductor device package are mounted on both sides. However, according to these methods, the mounted substrate has a drawback that the thickness of the package is increased by mounting the package. Further, the pitch of the external connection terminals is also defined by the pitch of the lands 31 of the semiconductor device substrate, which makes it difficult to increase the number of external connection terminals.

【0011】本発明ではパッケージ搭載時の厚みを大幅
に抑え、なおかつ超高密度実装を可能とする事を目的と
する。
It is an object of the present invention to significantly reduce the thickness of a package when mounted, and to enable ultra-high density mounting.

【0012】[0012]

【課題を解決するための手段】上記目的を達成すべく、
請求項1に記載の半導体装置は、封止部から突出した外
部接続端子を有する半導体装置であって、前記外部接続
端子は、該端子の端部が前記半導体装置の厚さ方向にお
いて第一の方向に配設してなる第一外部接続端子と、該
端子が前記第一の方向と逆方向に配設してなる第二外部
接続端子と、を有することを特徴とする。
In order to achieve the above object,
The semiconductor device according to claim 1, wherein the external connection terminal has an external connection terminal protruding from a sealing portion, and the external connection terminal has a first end in a thickness direction of the semiconductor device. It is characterized by having a first external connection terminal arranged in a direction and a second external connection terminal arranged in a direction opposite to the first direction.

【0013】そして請求項1において、前記外部接続端
子に、少なくとも二つのノッチ部を有することを特徴と
する。
According to a first aspect of the present invention, the external connection terminal has at least two notches.

【0014】更に請求項2において、前記ノッチ部の少
なくとも一つは前記樹脂封止部より0.5〜3.0mm
の間に設けてなることを特徴とする。
Furthermore, in claim 2, at least one of the notch portions is 0.5 to 3.0 mm from the resin sealing portion.
It is characterized in that it is provided between.

【0015】更に請求項1乃至3において、前記第一及
び第二外部接続端子が混在してなることを特徴とする。
Further, in claims 1 to 3, the first and second external connection terminals are mixed.

【0016】また請求項1乃至3において、前記第一及
び第二外部接続端子が交互に配置されてなることを特徴
とする。
Further, in the first to third aspects, the first and second external connection terminals are alternately arranged.

【0017】また請求項1記載の半導体装置を用いた実
装構造において、半導体装置が配置されるべく開口部を
有し、第一面及び前記第一面の裏面となる第二面にラン
ドが配設された基板を用いて、前記開口部内に配置され
た前記半導体装置の第一及び第二外部接続端子が、前記
第一面のランドと前記第一外部接続端子及び前記第二面
のランドと前記第二外部接続端子にて各々接続されてな
ることを特徴とする。
Also, in the mounting structure using the semiconductor device according to claim 1, there is an opening for disposing the semiconductor device, and lands are arranged on the first surface and a second surface which is a back surface of the first surface. Using the substrate provided, the first and second external connection terminals of the semiconductor device arranged in the opening, the first surface land and the first external connection terminal and the second surface land The second external connection terminals are connected to each other.

【0018】また請求項1記載の半導体装置を用いた実
装方法において、請求項1記載の半導体装置を基板の開
口部内に配置する工程と、前記半導体装置の第一及び第
二外部接続端子を前記基板の所望のランドと対向するよ
うフォーミングする工程と、前記第一及び第二外部接続
端子と前記所望のランドとを接合する工程と、を含むこ
とを特徴とする。
Also, in a mounting method using the semiconductor device according to claim 1, the step of disposing the semiconductor device according to claim 1 in an opening of a substrate, and the first and second external connection terminals of the semiconductor device are It is characterized by including a step of forming so as to face a desired land of the substrate, and a step of joining the first and second external connection terminals to the desired land.

【0019】以上を提供することにより、本課題を解決
する手段とする。
By providing the above, it is a means for solving this problem.

【0020】[0020]

【実施例】図1は本発明に係わる半導体装置の実施例を
説明するための説明図である。
1 is an explanatory view for explaining an embodiment of a semiconductor device according to the present invention.

【0021】図1(a)は本発明の半導体装置の平面図
であり、図1(b)はその半導体装置をA−Aで切断し
たときの断面図であり、図1(c)は図1(a)を横か
らみた側面図の拡大図である。本発明による半導体装置
(以下パッケージと称す)は半導体素子をモールドレジ
ンで封止し、更に封止部であるモールドレジンの外部へ
外部接続端子12を引き出したタイプで、図1(b)の
様に外部接続端子12は第一曲げ部50の部分を起点と
して、外部接続端子12の端部がパッケージの厚さ方向
において第一の方向を向く第一外部接続端子と、その第
一の方向と逆の方向を向く第二外部接続端子が存在す
る。図1では、第一外部接続端子と第二外部接続端子が
それぞれ上下両方向に向き、しかもL字形に曲げた形状
である。本発明によるパッケージは半導体装置実装用基
板(以下基板と称す)への実装を簡易にするため外部接
続端子の略中央部である第二曲げ部に、エッチング又は
スタンピングにより、パッケージの根本より0.5〜
3.0mmの間にノッチ部14を設けてあり簡易な実装
を実現している。つまり、実装の際にはこのノッチ部1
4を起点として、外部リードを曲げる事により、パッケ
ージの実装を容易にする事が可能である。また第一曲げ
部にもノッチ部を設ければフォーミングがより簡易にな
る。
FIG. 1A is a plan view of a semiconductor device of the present invention, FIG. 1B is a sectional view taken along the line AA of the semiconductor device, and FIG. It is an enlarged view of the side view of FIG. A semiconductor device (hereinafter referred to as a package) according to the present invention is a type in which a semiconductor element is sealed with a mold resin, and an external connection terminal 12 is drawn out to the outside of the mold resin, which is a sealing portion, as shown in FIG. The external connection terminal 12 has a first bent portion 50 as a starting point, and an end portion of the external connection terminal 12 faces the first direction in the thickness direction of the package. There is a second external connection terminal facing in the opposite direction. In FIG. 1, the first external connection terminal and the second external connection terminal are oriented in both the upper and lower directions and are bent in an L shape. The package according to the present invention has a structure in which a second bent portion, which is a substantially central portion of the external connection terminal, is etched from the root of the package to 0. 5-
The notch 14 is provided between 3.0 mm to realize simple mounting. That is, when mounting, this notch 1
By bending the external leads starting from 4, it is possible to easily mount the package. Forming becomes easier if a notch is also provided in the first bent portion.

【0022】図1(c)では外部接続端子を上下方向に
交互に曲げたタイプを本発明の一例としてあげてある。
これらは別段、上下均等に外部リードを曲げる必要性は
なく、基板や、半導体素子の種類により、曲げ角度、曲
げ数、曲げたリードの上下への配分をかえる事も可能で
ある。このように本発明のパッケージは基板の表裏両方
向へ実装する為、基板の表裏それぞれの配線パターンに
応じて外部接続端子を振り分けて曲げる事ができる。そ
のため外部接続端子が基板を挟む構造となり、接合強度
が増し、信頼性の高い構造が提供できる。
In FIG. 1C, a type in which external connection terminals are alternately bent in the vertical direction is shown as an example of the present invention.
It is not necessary to bend the external leads evenly above and below, and it is possible to change the bending angle, the number of bends, and the distribution of the bent leads above and below depending on the substrate and the type of the semiconductor element. Since the package of the present invention is thus mounted on both the front and back sides of the board, the external connection terminals can be distributed and bent according to the wiring patterns on the front and back of the board. Therefore, the external connection terminals have a structure sandwiching the substrate, the bonding strength is increased, and a highly reliable structure can be provided.

【0023】図2に本発明の半導体装置用リードフレー
ムの説明図をあげた。
FIG. 2 shows an explanatory view of the lead frame for a semiconductor device of the present invention.

【0024】図2(a)は本発明による半導体装置用リ
ードフレームの平面図であり、図2(b)はそれをA−
Aで切断したときの断面図である。この半導体装置用リ
ードフレーム1は金属薄板をエッチングあるいはプレス
加工による打ち抜きによって部分的に除去して形成す
る。構造的には半導体装置用リードフレーム1は矩形枠
からなるフレーム外枠2を有し、このフレーム外枠2の
略中央に半導体回路素子をとりつける矩形のダイパッド
3を有している。さらにダイパッド3は、タイバー4に
よってフレーム枠2に支持されている。またフレーム外
枠2の内側からは多数の細い内部リード5が、前記ダイ
パッド3に向かって延在しており、各内部リード5はレ
ジンモールド時にレジン流出を防止するダムバー6で支
持されている。このダムバー6は補強部材ともなってい
る。そして略中央に位置しているダイパッド3上に半導
体素子7を載置し、その後インナーリード5と半導体素
子の電極15と金属細線8で電気的に接続される。外部
接続端子12にはノッチ部14が設けられており、その
位置はモールドライン9から外側(外部接続端子側)へ
0.5〜3.5mmの間に、適当に設けられている。こ
れらのノッチ部を設ける位置、あるいは深さは、実装す
る基板の厚みや、基板上の配線の位置により適当に決め
る事ができる。
FIG. 2A is a plan view of a lead frame for a semiconductor device according to the present invention, and FIG.
It is sectional drawing when it cut | disconnects by A. The lead frame 1 for a semiconductor device is formed by partially removing a thin metal plate by etching or punching by pressing. Structurally, the lead frame 1 for a semiconductor device has a frame outer frame 2 formed of a rectangular frame, and a rectangular die pad 3 for mounting a semiconductor circuit element at a substantially central portion of the frame outer frame 2. Further, the die pad 3 is supported by the frame frame 2 by tie bars 4. A large number of thin inner leads 5 extend toward the die pad 3 from the inside of the frame outer frame 2, and each inner lead 5 is supported by a dam bar 6 that prevents resin from flowing out during resin molding. The dam bar 6 also serves as a reinforcing member. Then, the semiconductor element 7 is placed on the die pad 3 located substantially at the center, and thereafter, the inner lead 5 and the electrode 15 of the semiconductor element are electrically connected to the metal thin wire 8. The external connection terminal 12 is provided with a notch portion 14, and the position thereof is appropriately provided outside the mold line 9 (to the external connection terminal side) within a range of 0.5 to 3.5 mm. The position or depth at which these notch portions are provided can be appropriately determined depending on the thickness of the substrate to be mounted and the position of wiring on the substrate.

【0025】図3に本発明による実装基板を説明するた
めの説明図をあげた。図3(a)が平面図、図3(b)
が平面図をB−Bで切断した時の断面図である。本発明
では半導体装置用基板30に、ガラスエポキシ材を使用
した。当然の事ながら、これらはガラスエポキシ以外で
も、セラミック基板やシリコン基板でも代用できる。そ
して、その半導体装置用基板の略中央には、半導体装置
載置用の載置穴28が設けられており、その載置穴28
を中心として、半導体装置の外部リードを半導体装置用
基板上の配線へ接続するための、ランド31を適宜必要
に応じて配置してある。本発明では、この、ランドには
材質として金を使用した。裁置穴28の大きさ及びラン
ドの間隔や、配線パターンはそれを搭載するパッケージ
の大きさや種類によって適宜必要に応じて決められる。
また、配線パターンや、ランドは、別段、基板の表裏
共、配線が一緒である必要性もなく、実装基板、半導体
素子の種類や目的に応じて、適当な配線を、基板の表裏
に自由に設ける事ができる。また、半導体装置用基板の
材質、あるいは、ランドの材質は、半導体装置用基板の
種類や、半導体装置の種類によって、適当に決める事が
できる。
FIG. 3 is an explanatory view for explaining the mounting board according to the present invention. 3 (a) is a plan view and FIG. 3 (b).
FIG. 3 is a cross-sectional view of the plan view taken along the line BB. In the present invention, a glass epoxy material is used for the semiconductor device substrate 30. As a matter of course, other than glass epoxy, ceramic substrates or silicon substrates can be used instead. Then, a mounting hole 28 for mounting a semiconductor device is provided at substantially the center of the substrate for semiconductor device, and the mounting hole 28 is provided.
A land 31 for connecting the external lead of the semiconductor device to the wiring on the substrate for the semiconductor device is appropriately arranged as required. In the present invention, gold is used as the material for the land. The size of the arranging hole 28, the space between the lands, and the wiring pattern are appropriately determined depending on the size and type of the package in which the mounting pattern is mounted.
In addition, wiring patterns and lands do not have to be the same wiring on both the front and back sides of the board. Can be provided. Further, the material of the semiconductor device substrate or the material of the land can be appropriately determined depending on the type of the semiconductor device substrate and the type of the semiconductor device.

【0026】次に本発明による半導体装置の実装基板及
び基板への実装方法について説明する。
Next, a mounting substrate of the semiconductor device according to the present invention and a mounting method on the substrate will be described.

【0027】図4は本発明の実装方法を説明するための
説明図である。図4(a)は平面図、図4(b)は平面
図をA−A断面で切断した断面図である。本発明による
基板には略中央に半導体装置を裁置する半導体装置用裁
置穴28がありその周辺に半導体装置の外部接続端子を
接続するためのランド31がある、ランド31は基板の
表裏両方にあり、その間隔や裁置位置は半導体装置の種
類や大きさによって適宜必要に応じて決められる。そし
て半導体装置の実装は、本発明による半導体装置を、基
板の半導体装置裁置穴28に挿入し、そしてノッチ部1
4を起点としてランド31側に折り曲げランド31と外
部接続端子12とを接触させ、その後、その接点を半田
等によって接続固定する。これらを表裏両方について行
い実装を終える。実装後の図が図4となる。本発明で
は、半導体装置と半導体装置用基板の接続方法を、半田
で行ったが、導電性の接着剤等で接続する事も可能であ
る。
FIG. 4 is an explanatory diagram for explaining the mounting method of the present invention. FIG. 4A is a plan view, and FIG. 4B is a cross-sectional view taken along the line AA of the plan view. The substrate according to the present invention has a semiconductor device arranging hole 28 for arranging a semiconductor device in substantially the center thereof, and a land 31 for connecting an external connection terminal of the semiconductor device to the periphery thereof. The spacing and the position of placement are appropriately determined depending on the type and size of the semiconductor device. To mount the semiconductor device, the semiconductor device according to the present invention is inserted into the semiconductor device mounting hole 28 of the substrate, and the notch portion 1 is formed.
The bending land 31 and the external connection terminal 12 are brought into contact with each other on the side of the land 31 with 4 as the starting point, and then the contact point is connected and fixed by soldering or the like. This is done for both the front and back, and the mounting is completed. The figure after mounting is shown in FIG. In the present invention, the method of connecting the semiconductor device and the semiconductor device substrate is performed by soldering, but it is also possible to connect by a conductive adhesive or the like.

【0028】本明細書では、ノッチ部14を起点とし
て、外部リードを曲げる方法を説明したが、ノッチ部1
4を設けずとも、外部リードを曲げ、そして実装する事
も可能である。また、外部リードを基板の上下両方に実
装する必要もなく、外部リードを基板の上側一方、ある
いは、下側一方へのみ曲げる事も可能である。
In the present specification, the method of bending the external lead from the notch portion 14 as the starting point has been described.
It is also possible to bend the external leads and mount them without providing 4. Further, it is not necessary to mount the external leads on both the upper and lower sides of the substrate, and it is possible to bend the external leads only to one upper side or one lower side of the substrate.

【0029】なお、封止構造の一例としてレジンモール
ド型半導体装置を例にあげ説明したが、封止部から外部
接続端子が突出した構造の半導体装置であれば、封止構
造はいかなる構造を採っていても良いことはいうまでも
ない。
Although the resin mold type semiconductor device has been described as an example of the sealing structure, any sealing structure may be adopted as long as the semiconductor device has a structure in which the external connection terminals are projected from the sealing portion. Needless to say, it is okay.

【0030】[0030]

【発明の効果】以上の説明から、本発明による半導体装
置、実装基板の使用により以下のような効果が得られ
る。
From the above description, the following effects can be obtained by using the semiconductor device and the mounting substrate according to the present invention.

【0031】(1)半導体装置の実装高さが低くなり高
密度実装が可能となる。
(1) The mounting height of the semiconductor device is reduced, and high-density mounting is possible.

【0032】(2)半導体装置の外部接続端子のピッチ
を細かくする事が出来、高密度実装が可能となった。
(2) The pitch of the external connection terminals of the semiconductor device can be made fine, and high-density mounting is possible.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係わる半導体装置の実施例を説明する
為の説明図である。
FIG. 1 is an explanatory diagram for explaining an embodiment of a semiconductor device according to the present invention.

【図2】本発明に係わる半導体装置用リードフレームの
説明図である。
FIG. 2 is an explanatory diagram of a lead frame for a semiconductor device according to the present invention.

【図3】本発明に係わる半導体装置用の基板の説明図で
ある。
FIG. 3 is an explanatory view of a substrate for a semiconductor device according to the present invention.

【図4】本発明に係わる半導体装置を実装した基板の説
明図である。
FIG. 4 is an explanatory diagram of a substrate on which a semiconductor device according to the present invention is mounted.

【図5】従来の半導体装置用リードフレームの説明図で
ある。
FIG. 5 is an explanatory diagram of a conventional semiconductor device lead frame.

【図6】従来の実装方法の説明図である。FIG. 6 is an explanatory diagram of a conventional mounting method.

【符号の説明】[Explanation of symbols]

1 リードフレーム 2 フレーム外枠 3 ダイパッド 4 タブ吊りリード 5 内部リード 6 ダムバー 7 半導体素子 8 金属細線 9 モールドライン 10 ボンディングパッド 11 フレームゲート 12 外部接続端子 14 ノッチ部 20 半導体装置 28 半導体装置載置穴 30 半導体装置用基板 31 ランド 50 第一曲げ部 1 Lead Frame 2 Frame Outer Frame 3 Die Pad 4 Tab Suspension Lead 5 Inner Lead 6 Dam Bar 7 Semiconductor Element 8 Metal Fine Wire 9 Mold Line 10 Bonding Pad 11 Frame Gate 12 External Connection Terminal 14 Notch 20 Semiconductor Device 28 Semiconductor Device Mounting Hole 30 Semiconductor device substrate 31 Land 50 First bent portion

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 封止部から突出した外部接続端子を有す
る半導体装置であって、 前記外部接続端子は、該端子の端部が前記半導体装置の
厚さ方向において第一の方向に配設してなる第一外部接
続端子と、該端子が前記第一の方向と逆方向に配設して
なる第二外部接続端子と、を有することを特徴とする半
導体装置。
1. A semiconductor device having an external connection terminal protruding from a sealing portion, wherein the external connection terminal is arranged such that an end portion of the terminal is arranged in a first direction in a thickness direction of the semiconductor device. A semiconductor device, comprising: a first external connection terminal formed by: and a second external connection terminal formed by disposing the terminal in a direction opposite to the first direction.
【請求項2】 前記外部接続端子に、少なくとも二つの
ノッチ部を有することを特徴とする請求項1記載の半導
体装置。
2. The semiconductor device according to claim 1, wherein the external connection terminal has at least two notches.
【請求項3】 前記ノッチ部の少なくとも一つは前記樹
脂封止部より0.5〜3.0mmの間に設けてなること
を特徴とする請求項2記載の半導体装置。
3. The semiconductor device according to claim 2, wherein at least one of the notch portions is provided within 0.5 to 3.0 mm from the resin sealing portion.
【請求項4】 前記第一及び第二外部接続端子が混在し
てなることを特徴とする請求項1乃至3のいずれかに記
載の半導体装置。
4. The semiconductor device according to claim 1, wherein the first and second external connection terminals are mixed.
【請求項5】 前記第一及び第二外部接続端子が交互に
配置されてなることを特徴とする請求項1乃至3のいず
れかに記載の半導体装置。
5. The semiconductor device according to claim 1, wherein the first and second external connection terminals are alternately arranged.
【請求項6】 半導体装置が配置されるべく開口部を有
し、第一面及び前記第一面の裏面となる第二面にランド
が配設された基板を用いて、前記開口部内に配置された
前記半導体装置の第一及び第二外部接続端子が、前記第
一面のランドと前記第一外部接続端子及び前記第二面の
ランドと前記第二外部接続端子にて各々接続されてなる
ことを特徴とする請求項1記載の半導体装置を用いた実
装構造。
6. A substrate having an opening for arranging a semiconductor device and having lands arranged on a first surface and a second surface which is a back surface of the first surface is arranged in the opening. First and second external connection terminals of the semiconductor device are connected to the land of the first surface and the first external connection terminal and the land of the second surface and the second external connection terminal, respectively. A mounting structure using the semiconductor device according to claim 1.
【請求項7】 請求項1記載の半導体装置を基板の開口
部内に配置する工程と、前記半導体装置の第一及び第二
外部接続端子を前記基板の所望のランドと対向するよう
フォーミングする工程と、 前記第一及び第二外部接続端子と前記所望のランドとを
接合する工程と、を含むことを特徴とする請求項1記載
の半導体装置を用いた実装方法。
7. A step of disposing the semiconductor device according to claim 1 in an opening of a substrate, and a step of forming the first and second external connection terminals of the semiconductor device so as to face a desired land of the substrate. And a step of joining the first and second external connection terminals to the desired land, the mounting method using the semiconductor device according to claim 1.
JP7069689A 1995-03-28 1995-03-28 Semiconductor device and package structure and packaging method using the same Pending JPH08264705A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7069689A JPH08264705A (en) 1995-03-28 1995-03-28 Semiconductor device and package structure and packaging method using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7069689A JPH08264705A (en) 1995-03-28 1995-03-28 Semiconductor device and package structure and packaging method using the same

Publications (1)

Publication Number Publication Date
JPH08264705A true JPH08264705A (en) 1996-10-11

Family

ID=13410098

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7069689A Pending JPH08264705A (en) 1995-03-28 1995-03-28 Semiconductor device and package structure and packaging method using the same

Country Status (1)

Country Link
JP (1) JPH08264705A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011249870A (en) * 2010-05-21 2011-12-08 Olympus Corp Imaging apparatus
JP2020202317A (en) * 2019-06-11 2020-12-17 株式会社デンソー Semiconductor package and semiconductor device using the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011249870A (en) * 2010-05-21 2011-12-08 Olympus Corp Imaging apparatus
JP2020202317A (en) * 2019-06-11 2020-12-17 株式会社デンソー Semiconductor package and semiconductor device using the same

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