JPH08262118A - Waveform generating circuit for semiconductor testing device - Google Patents

Abstract

PURPOSE: To provide a waveform generating circuit for semiconductor testing device which can obtain a waveform having high timing accuracy by making pattern information to be able to be unified even when a pin-multiplex function is used and shorting the pattern information preparing and correcting time and redundant pattern information transferring time. CONSTITUTION: In a multi-pin system which corrects the rise and fall of a plurality of timing signals by utilizing the variable delay circuits 30-35 of other pins, pattern information selecting circuits 50 and 51 which decide whether or not the pattern information to be distributed to the other pins is to be distributed to their own pins are provided before the inputs of the waveform generating circuits 40, 41, and 42 of each pin. Therefore, the pattern information can be unified and the transferring time of the pattern information from a storage device to the pattern information register of each pin can be shortened. In addition, the preparing work and correcting work of the pattern information become easier, because the overlapping processing of preparation or correction is not required for the pattern information of a plurality of pins constituted of the same data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform generating circuit of a semiconductor testing device for obtaining a waveform with good timing accuracy.

[0002]

2. Description of the Related Art In testing a semiconductor, when it is necessary to apply a waveform to a specific pin at a cycle of 1/2 or 1/3 of a basic cycle, a waveform mode having a plurality of change points within the cycle is used. And generate a waveform using a plurality of timing signals. FIG. 2 shows a basic waveform mode. Where NRZ
(Non Return to Zero) Waveform has pattern information “1”
When the pattern information is "1", the waveform does not return to "0", and when the pattern information is "0", the waveform does not return to "1" even when the waveform becomes "0". In the example shown here, ACLK is used as the timing signal, and the waveform changes from "0" to "1" and "1" to "0" at the timing of ACLK.

An RZ (Return to Zero) waveform returns to "0" in a cycle after the waveform changes to "1" when the pattern information is "1", and the waveform when the pattern information is "0". The waveform remains unchanged at "0". In the example shown here, BCLK and CCL are used as timing signals.
K is used, the waveform changes from “0” to “1” at the timing of BCLK, and the waveform changes from “1” to “0” at the timing of CCLK.

An SBC (Surrounded By Complement) waveform has "0" before and after the waveform "1" in the cycle when the pattern information is "1", and "0" in the cycle when the pattern information is "0". The waveform before and after "is 1". In the case of the example shown here, ACLK, BCLK and CCLK are used as the timing signals.
Timing corresponds to the first change point in the cycle, and B
The CLK timing corresponds to the second change point in the cycle, the CCLK timing corresponds to the third change point in the cycle, and the waveform is "0" at each change point.
May change from "1" to "1" and from "1" to "0".

The above waveforms are generated by the circuit shown in FIG. 3 which is distributed to each test pin. In this circuit, timing signals ACLK, BCLK and CC
One variable delay circuit controlled by data for correcting the variation in the delay of LK is provided on each of the SET side and the RESET side. In the example shown in FIG.
In the case of the NRZ waveform, ACLK is used at both its rising and falling edges. Therefore, the variable delay circuit 3
0 corrects ACLK as the rising edge of the output waveform, and the variable delay circuit 31 corrects ACLK as the falling edge of the output waveform, whereby an output waveform with good timing accuracy can be obtained.

In the example shown in FIG. 2, in the case of the RZ waveform,
BCLK at the rising edge and CCL at the falling edge
K is used. Therefore, the variable delay circuit 30 is
By correcting CLK as the rising edge of the output waveform and correcting the CCLK as the falling edge of the output waveform, the variable delay circuit 31 can obtain the output waveform with good timing accuracy.

In the example shown in FIG. 2, in the case of the SBC waveform, ACLK, BCLK and CCLK may rise and fall, and in order to obtain an output waveform with good timing accuracy, three rise corrections are performed. A variable delay circuit and three variable delay circuits for falling correction are required. In the circuit of FIG. 3, there is only one variable delay circuit for correcting the rising and falling edges of the output waveform, and the SB having good timing accuracy is provided.
C waveform cannot be obtained.

Therefore, as a method of solving this, the pin multi system shown in FIG. 4 has been conventionally used. FIG.
In the case of the pin multi method, the other two variable delay circuits are used to obtain three variable delay circuits for rising correction and three variable delay circuits for falling correction. In this circuit, for example, the variable delay circuit 30 is used to correct the rising edge of ACLK, and the variable delay circuit 31 is used.
For the fall correction of ACLK and the variable delay circuit 32 for B
The variable delay circuit 33 is BCL for the rising edge correction of CLK.
By assigning the variable delay circuit 34 to the rising edge correction of CCLK and the variable delay circuit 35 to the falling edge correction of CCLK, the rising edge and the falling edge of all the timing signals can be corrected, and the timing accuracy is good. An SBC waveform can be obtained.

[0009]

In the pin multi system shown in FIG. 4, the waveform generating circuit corresponding to each pin has independent pattern information. In the example of obtaining the SBC waveform with good timing accuracy described above, the pattern information for each pin is exactly the same,
For each pin, it takes time and effort to create the same pattern information, and at the time of pattern modification, it becomes necessary to make corrections for a large number of pins, which increases pattern information creation and modification time.
Further, the register transfer time of the pattern information also increases the transfer time because the same pattern is transferred unnecessarily. The present invention makes it possible to unify pattern information even when the pin multi method is used, reduces the pattern information creation and correction time, and reduces the redundant pattern information transfer time to obtain a waveform with good timing accuracy. It is intended to realize a waveform generation circuit of the device.

[0010]

In order to achieve the above object, the waveform generating circuit of the present invention is configured as follows. In other words, in the pin multi system that performs rising correction and falling correction of a plurality of timing signals by using the variable delay circuit of another pin, whether or not the pattern information to be distributed to another pin is selected for its own pin. A pattern information selection circuit for controlling this is provided before the input of the waveform generation circuit of each pin.

[0011]

In the waveform generating circuit configured as described above, the pattern information can be unified, the pattern information transfer time from the memory device to the pattern information register of each pin can be shortened, and the pattern information can be created and the pattern information can be generated. In the correction of information, it is not necessary to duplicate or create the pattern information of a plurality of pins composed of the same data, which facilitates the work.

[0012]

EXAMPLE FIG. 1 shows an example of the present invention. In this circuit, pattern information selection circuits 50 and 51 for controlling whether or not the pattern information to be distributed to other pins to be selected for its own pin by the mode signal are provided in the conventional pin-multi system shown in FIG. There is. Here, by selecting the pattern information (1) as the pattern information to be input to the waveform generating circuit of each pin by the mode signal, the pattern information can be unified and the pattern information transfer time can be reduced. Further, as in the conventional pin-multi system, the variable delay circuit 30 is used to correct the rising edge of ACLK, and the variable delay circuit 31 is used.
For the fall correction of ACLK and the variable delay circuit 32 for B
The variable delay circuit 33 is BCL for the rising edge correction of CLK.
By assigning the variable delay circuit 34 to the rising edge correction of CCLK and the variable delay circuit 35 to the falling edge correction of CCLK, the rising edge and the falling edge of all the timing signals can be corrected, and the timing accuracy is good. Waveforms can be obtained.

[0013]

Since the present invention is configured as described above, it has the following effects. That is, in the waveform generating circuit of the present invention, the pattern information can be unified, the pattern information transfer time from the memory device to the pattern information register of each pin can be shortened, and in the creation of the pattern information and the correction of the pattern information, There is no need for duplicate processing of creation or correction for pattern information of a plurality of pins configured by the same data, and there is an effect that the work is facilitated.

[Brief description of drawings]

FIG. 1 is a block diagram of a waveform generation circuit of the present invention.

FIG. 2 is a timing diagram showing waveform modes.

FIG. 3 is a block diagram of a conventional waveform generation circuit.

FIG. 4 is a circuit block diagram of a conventional pin multi system.

[Explanation of symbols]

 20, 21, 22, 40, 41, 42 Waveform generation circuit 30, 31, 32, 33, 34, 35 Variable delay circuit 50, 51 Pattern information selection circuit

Claims (1)

[Claims] 1. In a pin multi system that corrects rising and falling of a plurality of timing signals by using a variable delay circuit of another pin, pattern information to be distributed to another pin is selected for its own pin. A waveform generation circuit for a semiconductor test apparatus, comprising at least one pattern information selection circuit for controlling whether or not to perform.