JP2001215260A - Integrated circuit tester and integrated circuit testing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correctly judge, at a low cost, whether an integrated circuit operating at a high speed is defective or not. SOLUTION: When test pattern data 124 is supplied from a pattern memory 110 to an LSI 104 in synchronization with a reference clock signal 120, the LSI 104 operates based on the supplied data 124 to output data 104A corresponding to the data 124 and a strobe signal 8. In synchronization with the signal 8, a result memory 6 takes in and holds the data outputted by the LSI 104. After all the data outputted by the LSI 104 correspondently to the data 124 is taken in and held by the memory 6, a test control means 106 controls the memory 6 and an expected-value memory 4 so that the memories 4, 6 successively output their held data to a comparison circuit 112. The circuit 112 compares the two groups of data with each other to judge whether or not the two coincide with each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an apparatus and a method for testing an integrated circuit such as a CPU and a DSP.

[0002]

2. Description of the Related Art LSIs (large-scale integrated circuits) such as CPUs (central processing units) and DSPs (digital signal processing units)
Is tested by a LSI tester at the time of manufacture to see if it operates normally. In the test by the LSI tester, basically, a large number of test pattern data prepared in advance are sequentially supplied to the LSI, and at this time, the data output by the LSI for each test pattern data is based on the correct expectation that the LSI should originally output. This is performed by sequentially comparing with the value data. If at least one of the data actually output by the LSI does not match the corresponding expected value data, L
SI is determined to be defective. The expected value data is created by, for example, simulating the operation of the LSI in advance.

[0003] In recent years, in order to handle an enormous amount of data such as moving image data, a faster CPU or DSP has been required. Therefore, these L
In the SI, a reference clock signal supplied from the outside is internally frequency-multiplied to generate an internal clock signal having a higher frequency of, for example, 200 MHz or more, and data is exchanged with an external circuit in synchronization with the reference clock signal. On the other hand, inside the LSI, a configuration is adopted in which high-speed operation is performed using the internal clock signal as a timing reference.

Therefore, such a high-speed LSI
Therefore, a higher-speed LSI tester will be used to test. However, at present, a low-speed LSI tester with a reference clock signal of about 40 MHz is about 150 million yen, whereas a high-speed tester with a reference clock signal of about 100 MHz is very expensive, about 200 million yen.

[0005] In view of the above, it has been studied to suppress an increase in manufacturing equipment costs by making it possible to test a high-speed LSI using a low-speed LSI tester. An example of such a technique is disclosed in Japanese Patent Application Laid-Open No. 02-157675. It is disclosed in the gazette. FIG. 5 is a block diagram showing the conventional LSI tester, FIG. 6 is a timing chart showing the operation of the LSI tester of FIG. 5, and FIG. 7 is the same flowchart. The LSI tester 102 shown in FIG. 5 is for testing the LSI 104, and includes a test control unit 106, a test pattern file device 108, a pattern memory 110, and a comparison circuit 1.
12, a reference clock generation circuit 114, and a strobe signal generation circuit 116.

[0006] The test control means 106 includes a computer (not shown), which operates based on a test program stored in a test program file device 106A and controls each unit. L to be tested
The SI 104 is, for example, a CPU or a DSP, and includes a PLL circuit 118 therein. The PLL circuit 118 multiplies the frequency of the reference clock signal 120 supplied from the reference clock generation circuit 114 to increase the frequency. Generate a high internal clock signal 122. The transfer of data to and from the external circuit is performed in synchronization with the reference clock signal 120, while the PLL circuit 118 internally
Operates at high speed using the internal clock signal 122 generated by the above as a timing reference.

[0007] The test pattern file device 108 includes:
A large number of test pattern data created in advance are stored. The pattern memory 110 fetches and holds the test pattern data from the test pattern file device 108 under the control of the test control means 106 at the start of the test.
24 sequentially in synchronization with the reference clock signal 120,
104.

The pattern memory 110 also stores expected value data created by the test control means 106 at the start of the test. The expected value data is obtained by converting each test pattern data 124 held in the pattern memory 110 into an LSI 1
When the signal is given to the LSI 04, the data should be output when the LSI 104 operates normally. Test control means 106
Generates such expected value data by simulating the operation of the LSI 104 for each test pattern data.

A strobe signal generation circuit 116 generates a strobe signal for each cycle of the reference clock signal 120 and supplies it to a comparison circuit 112. The comparison circuit 112 generates a strobe signal every time the strobe signal is input.
0 is the test pattern data 12 supplied to the LSI 104
4 and the expected value data 1 output by the pattern memory 110 from the LSI 104 as a result of the internal operation.
25 to determine whether the two data match.

Next, the operation of the LSI tester 102 thus configured will be described with reference to FIG.
The test control means 106 controls the test pattern file device 1
08 and the pattern memory 110 are controlled to cause the pattern memory 110 to hold a large number of test pattern data 124 stored in the test pattern file device 108. Further, the expected value data is stored in the pattern memory 110.

[0011] The test control means 106 then controls the LSI 10
In order to start the test of No. 4, the reference clock generation circuit 114 is activated to generate the reference clock signal 120, and the strobe signal generation circuit 116 and the comparison circuit 112 are activated (step S100). When the reference clock generation circuit 114 generates the reference clock signal 120, L
In the SI 104, a PLL circuit 118 operates to generate a reference clock signal 120 from the reference clock generation circuit 114.
To the internal clock signal 1 having a higher frequency.
22 is generated (step S101). At this time, PL
Until the L circuit 118 locks and the internal clock signal 122 synchronized with the reference clock signal 120 is generated, L
The SI 104 does not perform an operation related to data processing.

When the PLL circuit 118 locks, the LSI
104 starts operation, and when the first test pattern data 124 is supplied from the pattern memory 110 in synchronization with the reference clock signal 120 (step S102), L
The SI 104 operates in synchronization with the internal clock signal 122 (step S103), processes the supplied test pattern data 124 to generate corresponding data, and outputs the same data 104A in the next cycle of the reference clock signal 120. (Step S104).

The pattern memory 110 also outputs each expected value data 125 in synchronization with the reference clock signal 120, and the comparison circuit 112 outputs the strobe signal 116A
Is input, the reference clock signal 12
For each cycle of 0, the expected value data 125 output by the pattern memory 110 is compared with the data 104A output by the LSI 104 as a result of the internal operation, and it is determined whether the two data match (step S105). .

If the LSI 104 is operating normally and the result of this determination is Yes, the test control means 106
Determines whether all the test pattern data 124 held in the pattern memory 110 is supplied to the LSI 104 and the test is completed (step S106). If the result of this determination is No, the test control means 10
6 continues the operation of each part, and as a result, step 102
To 106 are repeated. On the other hand, when the determination result is Ye
In the case of s, the test control means 106 stops the operation of each unit and ends the test (step S107). If the determination result in step S105 is No, the LSI 1
Since the operation in step 04 is abnormal, the test control means 106 proceeds to step 107 and ends the test.

[0015]

However, in such a conventional LSI tester 102, it is necessary to accurately synchronize the reference clock signal 120 supplied to the LSI 104 and the internal clock signal 122 generated inside the LSI 104. Due to the difficulty, there is a case where a malfunction occurs and the LSI 104 is determined to be abnormal even though the LSI 104 is operating normally.

First, a deviation between the reference clock signal 120 and the internal clock signal 122 will be described. The reference clock signal 120 generated by the reference clock generation circuit 114 always contains a small amount of timing jitter. When the timing of the reference clock signal 120 fluctuates due to such jitter, the PLL circuit 118 in the LSI 104 attempts to synchronize the timing of the internal clock signal 122 in accordance with the fluctuation, but cannot synchronize instantaneously. As a result, for example, when the jitter of the reference clock signal 120 is generated with a width of about 1 ns before and after, the timing of the reference clock signal 120 and the internal clock signal 122 is shifted by about 1 ns before and after.

Also, the reference clock signal 120 and the internal clock signal 12 may vary depending on the performance variation of the LSI 104 and therefore the PLL circuit 118 and the difference in operating conditions.
The phase relationship with 2 changes. For example, the PLL circuit 118
The delay time from the rising edge of the reference clock signal 120 to the latest rising edge of the internal clock signal 122 under the condition that the switching speed of the transistor constituting Has a difference of about several ns.

FIG. 6 shows how erroneous determination occurs due to such a timing shift.
This will be described with reference to FIG. As shown in FIG. 6, if the value of the test pattern data 124 output from the pattern memory 110 at the period P1 is “1”, the LSI 104
Operates based on the test pattern data 124, and generates data having a value of, for example, 0x1111 as a processing result (0x indicates that the following number is a hexadecimal number). The LSI 104 outputs this data to the comparison circuit 112 in the next cycle P2.

However, as described above, the reference clock signal 1
If the timing shift between the internal clock signal 20 and the internal clock signal 122 is large, the LSI 104 operates in synchronization with the internal clock signal 122 to the last, so that the operation may start with a delay from the start timing of the cycle P1. In such a case, the processing for the test pattern data 124 is not completed in the cycle P1, but is completed in the next cycle P2. Therefore, the data having a value of 0x1111 as the processing result is shown in FIG. As described above, the data is output to the comparison circuit 112 in the cycle P3.

However, the expected value data corresponding to this data is output from the pattern memory 110 at the period P2 and supplied to the comparison circuit 112 as shown in FIG. Although the operation is normal, the comparison result by the comparison circuit 112 becomes inconsistent (Fail).

Due to the timing difference between the reference clock signal 120 and the internal clock signal 122, the test pattern data 124 supplied to the LSI 104 after the period P2 is 0x222 in the periods P4 and P5.
Assuming that the data of 2,0x3333 are to be output at periods P5 and P6, respectively, as shown in FIG. 6, even though the LSI 104 is operating normally, the periods P4, P5, P6 All of the comparison results in are inconsistent.

An object of the present invention is to solve such a problem, and an object of the present invention is to provide an integrated circuit tester and an integrated circuit test method capable of judging the quality of an integrated circuit operating at high speed at low cost and without error. Is to provide.

[0023]

According to the present invention, in order to achieve the above object, the present invention operates based on an internal clock signal which is synchronized with an externally applied reference clock signal and has a higher frequency than the reference clock signal. An integrated circuit tester for testing an integrated circuit that outputs data corresponding to the data in synchronization with the clock signal in synchronization with the reference clock signal and outputs a strobe signal indicating that the data has been output; A pattern memory that holds a plurality of test pattern data, sequentially supplies the held test pattern data to the integrated circuit in synchronization with the reference clock signal, and the pattern memory stores the test pattern data in the integrated circuit. The test circuit supplies the test pattern data, and the integrated circuit outputs data corresponding to the test pattern data. When the data is output, in synchronization with the strobe signal output by the integrated circuit, a result memory that captures and holds the data output by the integrated circuit and the plurality of test pattern data are supplied to the integrated circuit. When the integrated circuit holds the expected value data that should be output by the integrated circuit for each test pattern data, the data held by the result memory and the data held by the expected value memory are read from each memory. A comparison circuit for receiving and comparing, and after the result memory captures and holds all the data output by the integrated circuit corresponding to each of the plurality of test pattern data, controls the result memory and the expected value memory. Test control means for sequentially outputting the data held in each memory to the comparison circuit. Characterized by comprising.

Further, according to the present invention, data is supplied in synchronization with an externally applied reference clock signal, operating based on an internal clock signal having a higher frequency than the reference clock signal, and in synchronization with the reference clock signal. A method for testing an integrated circuit that outputs data corresponding to the same data in synchronization with the reference clock signal and outputs a strobe signal indicating that the data has been output,
A plurality of test pattern data are sequentially supplied to the integrated circuit in synchronization with the reference clock signal, and when the integrated circuit outputs data corresponding to each test pattern data, the integrated circuit outputs the strobe signal. Synchronously, the data output by the integrated circuit is held in a result memory, and when the plurality of test pattern data is supplied to the integrated circuit, an expected value that the integrated circuit should originally output for each test pattern data After holding the data in the expected value memory in advance and holding all the data output by the integrated circuit corresponding to the plurality of test pattern data in the result memory, the data held in the result memory It is characterized by sequentially comparing the expected value data stored in the expected value memory with the expected value data.

In the integrated circuit tester of the present invention, when test pattern data is supplied to the integrated circuit from the pattern memory in synchronization with the reference clock signal, the integrated circuit operates based on the supplied test pattern data, and performs the test. It outputs data corresponding to the pattern data and outputs a strobe signal. At this time, the result memory is
In synchronization with the strobe signal, the data output from the integrated circuit is captured and held. Then, the test control means controls the result memory and the expected value memory to hold the data output from the integrated circuit corresponding to each of the plurality of test pattern data, and the result memory and the expected value memory. The data is sequentially output to the comparison circuit. The comparing circuit receives the data held in the result memory and the data held in the expected value memory from each memory and compares them.

In the integrated circuit test method of the present invention, a plurality of test pattern data are sequentially supplied to an integrated circuit in synchronization with a reference clock signal, and the integrated circuit outputs data corresponding to each test pattern data. The data output from the integrated circuit is held in the result memory in synchronization with the strobe signal output from the integrated circuit. Then, after all the data output from the integrated circuit corresponding to each of the plurality of test pattern data are held in the result memory, the data held in the result memory and the expected value data held in the expected value memory are compared. Compare sequentially.

As described above, according to the present invention, when the integrated circuit outputs the strobe signal, the data output from the integrated circuit is held in the result memory, so that the integrated circuit operates based on each test pattern data. Only the data to be output is stored in the result memory in the order output by the integrated circuit. Each data held in the result memory is reliably compared with the corresponding expected value data held in the expected value memory independently of the operation timing of each test pattern data of the integrated circuit.

Therefore, even if the timing at which the integrated circuit outputs data is delayed due to a timing difference between the reference clock signal and the internal clock signal, the data output by the integrated circuit is not the expected value data to be compared with the data. They are always compared. Therefore, unlike the conventional case, the output data of the integrated circuit is not compared with the expected value data to be compared, so that a problem that the integrated circuit is determined to be defective even though it is operating normally occurs. do not do. The test pattern memory, the result memory, and the expected value memory only need to operate in synchronization with the reference clock signal, and the integrated circuit tester of the present invention and the integrated circuit tester of the present invention that operate based on the integrated circuit test method of the present invention Need only have a performance level comparable to that of a conventional low-speed integrated circuit tester. Therefore, a high-speed integrated circuit can be tested at low cost.

[0029]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an LSI according to the present invention.
FIG. 2 is a block diagram showing an example of a tester, and FIG.
FIG. 3 is a timing chart showing the operation of the tester. In the drawing, the same elements as those in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted here. Hereinafter, an example of an integrated circuit tester according to the present invention will be described with reference to these drawings, and at the same time, an embodiment of an integrated circuit test method according to the present invention will be described.

The LSI tester 2 shown in FIG. 1 is particularly different from the LSI tester shown in FIG. 5 in that an expected value memory 4 and a result memory 6 are added, and a strobe signal generated by the LSI 104 is added to the result memory 6. And the point that the comparison circuit 112 compares the expected value data with the data held in the result memory 6.

More specifically, expected value data is stored in the expected value memory 4 under the control of the test control means 106 at the start of the test. The expected value data corresponds to each test pattern data 1 stored in the pattern memory 110.
When 24 is given to the LSI 104, the data should be output when the LSI 104 operates normally. The test control means 106 generates such expected value data by simulating the operation of the LSI 104 for each test pattern data 124.

The LSI 104 operates based on an internal clock signal 122 generated internally by frequency multiplication of a reference clock signal 120 supplied from the outside by using a PLL circuit 118. When data is supplied in synchronization with the reference clock signal 120, the LSI 104 converts the data 104 A corresponding to the data into the reference clock signal 12.
The strobe signal 8 is output in synchronization with 0 and indicates that data has been output.

The result memory 6 includes a pattern memory 11
0 supplies the test pattern data 124 to the LSI 104, and when the LSI 104 outputs data corresponding to the test pattern data, acquires and holds the data 104A output by the LSI 104 in synchronization with the strobe signal 8 output by the LSI 104. .

Next, the operation of the LSI tester 2 configured as described above will be described with reference to FIGS. The test control unit 106 first controls the test pattern file device 108 and the pattern memory 110 to output a large number of test pattern data stored in the test pattern file device 108 from the test pattern file device 108 to the pattern memory 110, The pattern is stored in the pattern memory 110. Further, the test control means 106 creates expected value data and stores it in the expected value memory 4.
To be stored.

After that, the test control means 106
In order to start the test of No. 4, the reference clock generation circuit 114 is activated to generate the reference clock signal 120 (step S10). When the reference clock generation circuit 114 generates the reference clock signal 120, the LSI 104
The L circuit 118 operates and the reference clock generation circuit 114
The frequency of the reference clock signal 120 is multiplied to generate an internal clock signal 122 having a higher frequency (step S11). At this time, the PLL circuit 118 locks,
Internal clock signal 1 synchronized with reference clock signal 120
Until 22 is generated, the LSI 104 does not perform an operation related to data processing.

When the PLL circuit 118 locks, the LSI
The operation of the LSI 104 starts, and when, for example, “1” is supplied as the first test pattern data 124 from the pattern memory 110 in the cycle P1 of the reference clock signal 120 (step S12), the LSI 104 synchronizes with the internal clock signal 122. It operates and processes the supplied test pattern data 124 to obtain, for example, 0
x1111 is generated (step S13). LSI10
4 outputs this data at, for example, the cycle P3 of the reference clock signal 120 (step S14).

Since the LSI 104 has output data, the high-level strobe signal 8 is output at the period P3.
Is output. As a result, the result memory 6 stores the LSI 104
Captures and holds the data output in period P3, for example, at the timing of the falling edge in period 3 of reference clock signal 120.

The test control means 106 determines whether or not the test has been completed based on whether or not all the test pattern data 124 has been supplied from the pattern memory 110 to the LSI 104 (step S15). At this stage, since the test has not been completed, the judgment result is No,
The operation returns to step S12, and steps S12 to S15
Is repeated.

That is, the next test pattern data 124 is supplied from the pattern memory 110 to the LSI 104, and the LSI 104
(Step S13), for example, 0X
2222 to generate the reference clock signal 120
Is output in the cycle P5 (step S14). Then,
The next test pattern data 124 is supplied to the LSI 104, and the LSI 104
4, and generates data of, for example, 0 × 333, and outputs it at a cycle P6. These output data are also output from the LSI 104 simultaneously with the strobe signal 8 each time.
Is output to the result memory 6 and held.

Here, if all the test pattern data 124 held in the pattern memory 110 are
If the data is supplied to the LSI 104, the determination result in the step S15 is Yes, so that the test control unit 106 stops the data supply from the pattern memory 110 to the LSI 104, activates the comparison circuit 112,
By controlling the expected value memory 4 and the result memory 6, the data held in each memory is sequentially output to the comparison circuit 112 in synchronization with the reference clock signal 120.

The expected value memory 4 has the test control means 106
As a result, as shown in FIG. 2, when the LSI 104 is operating normally, the expected value data that the LSI 104 should originally output are 0X1111, 0X2222, and 0X333.
3 are stored in the same order as the order in which the LSI 104 outputs.

Therefore, the result memory 6 is stored in the LSI 10
0X1111 and 0X22 received from 4 and held
When the data 22 and 0X3333 are output from the result memory 6 in this order (the order in which they are held) in synchronization with the reference clock signal 120, the same data 125 is also output from the expected value memory 4 in the same order.

The comparison circuit 112 sequentially receives and compares these data in each cycle of the reference clock signal 120 (step S16). In this case, since the comparison result is Yes in any case, the LSI 104 is determined to be normal and the test ends (step S17). In this comparison, if at least one of the data from the result memory 6 does not match the expected value data 125, the determination result is No in step S16, and at that stage, the operation of the LSI 104 is determined to be abnormal. To end the test (step S17).

As described above, in this embodiment, the LSI
When the LSI 104 outputs the strobe signal 8, the LSI 10
4 stores the data 104A output by the LSI 104 in the result memory 6, so that only the data output as a result of the LSI 104 operating based on the respective test pattern data 124 are stored in the result memory 6 in the order output by the LSI 104.
Is held. Each data held in the result memory 6 is stored in the test pattern data 12
Regardless of the operation timing for each of the four, the data is reliably compared with the corresponding expected value data held in the expected value memory 4.

Therefore, LS is caused by the timing difference between the reference clock signal 120 and the internal clock signal 122.
Even if the timing at which the I104 outputs data is delayed, the data output by the LSI 104 is always compared with expected value data to be compared with the data. Therefore,
Since the output data of the LSI 104 is not compared with the expected value data to be compared as in the related art,
There is no problem of determining that the device 104 is defective even though it is operating normally.

The test pattern memory, the result memory 6 and the expected value memory 4 only need to operate in synchronization with the reference clock signal 120. The LSI tester 2 has the same performance as a conventional low-speed integrated circuit tester. What is necessary is just to have the performance level. Therefore, the LSI 104 operating at high speed can be tested at low cost.

The problem of the conventional timing shift between the reference clock signal 120 and the internal clock signal 122 is as follows.
The frequency of the internal clock signal 122 is
By lowering to about 20 the influence of jitter and the like can be neglected and avoided. However, in that case, the operating speed of the LSI 104 is greatly reduced,
The result is that the test of 104 takes a long time. On the other hand, in the present invention, since the high-speed LSI 104 is operated at high speed as it is, the test can be completed in a short time. For example, assuming that the frequency of the internal clock signal 122 is eight times that of the reference clock signal 120 and the test is performed with the frequency of the internal clock signal 122 set to the same frequency as that of the reference clock signal 120, in this embodiment, the internal Since the frequency of the clock signal 122 can be kept as it is, the time required for the test can be reduced to 1/8.

Further, conventionally, the test pattern data 124 is supplied to the LSI 104 in synchronization with the reference clock signal 120, and as a result, the data output from the LSI 104 is compared with the expected value data also in synchronization with the reference clock signal 120. Therefore, a circuit that performs asynchronous processing such as interrupt processing cannot be tested by an LSI tester. However, in the present invention, LS
Even if the I104 outputs data asynchronously, each data is reliably held in the result memory 6 at the timing when the LSI 104 outputs the strobe signal 8 and in the order in which the LSI 104 outputs data. Therefore, in this embodiment, it is possible to test an LSI that performs asynchronous processing. In the present embodiment, the number of test pattern data 124 is assumed to be 3 for the sake of explanation.
Usually, a large amount of test pattern data 12
4 is used.

Next, a second embodiment of the present invention will be described. FIG. 4 is a block diagram showing an LSI tester 10 according to the second embodiment. The LSI tester 10 of the second embodiment shown in FIG.
4 in that the pattern memory 110, the result memory 6, and the expected value memory 4 are all configured by different storage areas in the same storage device as shown in FIG.

Therefore, the LSI of the second embodiment
In the tester 10, it is not necessary to provide the dedicated expected value memory 4 and the result memory 6, and it is possible to avoid the cost increase caused by adding the dedicated memory by sharing the memory resources. In addition, as the storage device 12, what has been conventionally used as a pattern memory can be used. The storage area can be divided into three, and each storage area can be used as the above three memories. It is also possible to configure two of the above three memories with the same storage device, and in that case, the cost can be reduced.

[0051]

As described above, the present invention operates in accordance with an internal clock signal having a higher frequency than the reference clock signal in synchronization with an externally applied reference clock signal, and in synchronization with the reference clock signal. An integrated circuit tester for testing an integrated circuit that outputs data corresponding to the data in synchronization with the reference clock signal when the data is supplied and outputs a strobe signal indicating that the data has been output. A pattern memory that holds test pattern data and sequentially supplies the held test pattern data to the integrated circuit in synchronization with the reference clock signal; and the pattern memory supplies the test pattern data to the integrated circuit. And when the integrated circuit outputs data corresponding to the test pattern data, A result memory that captures and holds the data output by the integrated circuit in synchronization with the strobe signal output by the integrated circuit; and the integrated circuit when the plurality of test pattern data is supplied to the integrated circuit. Is an expected value memory that holds expected value data that should be originally output for each test pattern data, and a comparison circuit that receives and compares the data held in the result memory and the data held in the expected value memory from each memory. After the result memory fetches and holds all the data output from the integrated circuit corresponding to the plurality of test pattern data, the result memory and the expected value memory are controlled and held by each memory. Test control means for sequentially outputting data to the comparison circuit. That.

Further, according to the present invention, data is supplied in synchronization with an externally supplied reference clock signal, operating based on an internal clock signal having a higher frequency than the reference clock signal, and in synchronization with the reference clock signal. A method for testing an integrated circuit that outputs data corresponding to the same data in synchronization with the reference clock signal and outputs a strobe signal indicating that the data has been output,
A plurality of test pattern data are sequentially supplied to the integrated circuit in synchronization with the reference clock signal, and when the integrated circuit outputs data corresponding to each test pattern data, the integrated circuit outputs the strobe signal. Synchronously, the data output by the integrated circuit is held in a result memory, and when the plurality of test pattern data is supplied to the integrated circuit, an expected value that the integrated circuit should originally output for each test pattern data After holding the data in the expected value memory in advance and holding all the data output by the integrated circuit corresponding to the plurality of test pattern data in the result memory, the data held in the result memory It is characterized by sequentially comparing the expected value data stored in the expected value memory with the expected value data.

In the integrated circuit tester of the present invention, when test pattern data is supplied to the integrated circuit from the pattern memory in synchronization with the reference clock signal, the integrated circuit operates based on the supplied test pattern data, and performs the test. It outputs data corresponding to the pattern data and outputs a strobe signal. At this time, the result memory is
In synchronization with the strobe signal, the data output from the integrated circuit is captured and held. Then, the test control means controls the result memory and the expected value memory to hold the data output from the integrated circuit corresponding to each of the plurality of test pattern data, and the result memory and the expected value memory. The data is sequentially output to the comparison circuit. The comparing circuit receives the data held in the result memory and the data held in the expected value memory from each memory and compares them.

In the integrated circuit test method of the present invention, a plurality of test pattern data are sequentially supplied to the integrated circuit in synchronization with the reference clock signal, and the integrated circuit outputs data corresponding to each test pattern data. The data output from the integrated circuit is held in the result memory in synchronization with the strobe signal output from the integrated circuit. Then, after all the data output from the integrated circuit corresponding to each of the plurality of test pattern data are held in the result memory, the data held in the result memory and the expected value data held in the expected value memory are compared. Compare sequentially.

As described above, according to the present invention, when the integrated circuit outputs the strobe signal, the data output from the integrated circuit is held in the result memory, so that the integrated circuit operates based on each test pattern data. Only the data to be output is stored in the result memory in the order output by the integrated circuit. Each data held in the result memory is reliably compared with the corresponding expected value data held in the expected value memory independently of the operation timing of each test pattern data of the integrated circuit.

Therefore, even if the timing at which the integrated circuit outputs data is delayed due to a timing difference between the reference clock signal and the internal clock signal, the data output by the integrated circuit is not the expected value data to be compared with the data. They are always compared. Therefore, unlike the conventional case, the output data of the integrated circuit is not compared with the expected value data to be compared, so that a problem that the integrated circuit is determined to be defective even though it is operating normally occurs. do not do. The test pattern memory, the result memory, and the expected value memory only need to operate in synchronization with the reference clock signal, and the integrated circuit tester of the present invention and the integrated circuit tester of the present invention that operate based on the integrated circuit test method of the present invention Need only have a performance level comparable to that of a conventional low-speed integrated circuit tester. Therefore, a high-speed integrated circuit can be tested at low cost.

Further, the problem of the conventional timing deviation between the reference clock signal and the internal clock signal can be avoided by reducing the frequency of the internal clock signal to the same level as that of the reference clock signal so that the influence of jitter and the like can be ignored. can do. However, in that case, the operation speed of the integrated circuit is significantly reduced, and the test of the integrated circuit takes a long time. On the other hand, according to the present invention, the test can be completed in a short time because the high-speed integrated circuit is operated at high speed as it is.

Further, conventionally, test pattern data is supplied to an integrated circuit in synchronization with a reference clock signal, and as a result, data output from the integrated circuit is compared with expected value data also in synchronization with the reference clock signal. For example, a circuit that performs asynchronous processing such as interrupt processing cannot be tested by an LSI tester.
However, in the present invention, even if the integrated circuit outputs data asynchronously, each data is reliably held in the result memory at the timing when the integrated circuit outputs the strobe signal and in the order in which the integrated circuit outputs data. You. Therefore, according to the present invention, it is possible to test an integrated circuit that performs asynchronous processing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of an LSI tester according to the present invention.

FIG. 2 is a timing chart showing the operation of the LSI tester of FIG.

FIG. 3 is a flowchart illustrating an operation of the LSI tester of FIG. 1;

FIG. 4 is a block diagram illustrating an LSI tester according to a second embodiment;

FIG. 5 is a block diagram showing a conventional LSI tester.

FIG. 6 is a timing chart showing the operation of the LSI tester of FIG.

FIG. 7 is a flowchart showing an operation of the LSI tester of FIG. 5;

[Explanation of symbols]

2 ... LSI tester, 4 ... Expected value memory, 6 ...
Result memory, 8 ... Strobe signal, 10 ... LSI
Tester 12, storage device 102, LSI tester 104, LSI 106, test control means 10,
Reference numeral 8: a test pattern file device; 110, a pattern memory; 112, a comparison circuit; 114, a reference clock generation circuit; 116, a strobe signal generation circuit;
18 PLL circuit, 120 reference clock signal, 1
22 ... internal clock signal, 124 ... test pattern data.

Claims (7)

[Claims] 1. An operation which is synchronized with an externally applied reference clock signal and operates on the basis of an internal clock signal having a higher frequency than the reference clock signal. When data is supplied in synchronization with the reference clock signal, the data is converted to the same data. An integrated circuit tester for testing an integrated circuit that outputs corresponding data in synchronization with the reference clock signal and that outputs a strobe signal indicating that the data has been output, and holds and holds a plurality of test pattern data. A pattern memory for sequentially supplying the test pattern data to the integrated circuit in synchronization with the reference clock signal; and the pattern memory supplying the test pattern data to the integrated circuit. When the data corresponding to the data is output, the integrated circuit outputs the switch. In synchronization with a lobe signal, a result memory that captures and holds the data output by the integrated circuit; and, when the plurality of test pattern data is supplied to the integrated circuit, the integrated circuit performs the processing for each of the test pattern data. An expected value memory that holds expected value data that should be output, a comparison circuit that receives the data held in the result memory and the data held in the expected value memory from each memory and compares the data, and the plurality of test patterns After the result memory fetches and holds all the data output by the integrated circuit corresponding to the data, the result memory and the expected value memory are controlled to sequentially store the data held by each memory. An integrated circuit tester, comprising: test control means for outputting a test signal to a test circuit. 2. The memory according to claim 2, wherein said pattern memory, said result memory, and said expected value memory are provided.
2. The integrated circuit tester according to claim 1, wherein one or all of the integrated circuit testers are configured by different storage areas in the same storage device. 3. The integrated circuit includes a PLL circuit.
2. The integrated circuit tester according to claim 1, wherein the internal clock signal is generated by multiplying the frequency of the reference clock signal using an LL circuit. 4. The integrated circuit is an LSI, and the LS
2. The integrated circuit tester according to claim 1, wherein I is a CPU or a DSP. 5. An apparatus operates in accordance with an internal clock signal having a frequency higher than that of the reference clock signal in synchronization with an externally applied reference clock signal. When data is supplied in synchronization with the reference clock signal, the data is converted to the same data. A method for testing an integrated circuit that outputs corresponding data in synchronization with the reference clock signal and outputs a strobe signal indicating that the data has been output, comprising: synchronizing a plurality of test pattern data with the reference clock signal. When the integrated circuit outputs data corresponding to each test pattern data, the data output by the integrated circuit is synchronized with the strobe signal output by the integrated circuit when the integrated circuit outputs data corresponding to each test pattern data. And storing the plurality of test pattern data in the integrated circuit when the plurality of test pattern data are supplied to the integrated circuit. An expected value data that the circuit should originally output for each test pattern data is held in an expected value memory in advance, and all the data output by the integrated circuit corresponding to each of the plurality of test pattern data are held in the result memory. And after that, sequentially compares the data held in the result memory with the expected value data held in the expected value memory. 6. The test pattern data is held in a pattern memory, read out from the pattern memory and supplied to the integrated circuit, and any two of the pattern memory, the result memory, and the expected value memory, 6. The integrated circuit test method according to claim 5, wherein all or all are configured by different storage areas in the same storage device. 7. The integrated circuit includes a PLL circuit.
6. The integrated circuit test method according to claim 5, wherein the internal clock signal is generated by multiplying the frequency of the reference clock signal using an LL circuit.