JPH08250615A - Ceramic package for semiconductor chip - Google Patents
Ceramic package for semiconductor chipInfo
- Publication number
- JPH08250615A JPH08250615A JP7081973A JP8197395A JPH08250615A JP H08250615 A JPH08250615 A JP H08250615A JP 7081973 A JP7081973 A JP 7081973A JP 8197395 A JP8197395 A JP 8197395A JP H08250615 A JPH08250615 A JP H08250615A
- Authority
- JP
- Japan
- Prior art keywords
- cap
- layer
- copper plating
- package
- plating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
- H01L2924/1617—Cavity coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体チップ用セラミ
ックパッケージに係り、より詳細には、携帯電話等のマ
イクロ波通信機器に用いられるＳＡＷフィルタ素子等の
半導体チップを封止でき、マイクロ波特性に優れ、生産
性が良好で、安価に製造できる半導体チップ用セラミッ
クパッケージに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip ceramic package, and more particularly to a semiconductor package such as a SAW filter element used in a microwave communication device such as a mobile phone, which is capable of sealing a microwave chip. TECHNICAL FIELD The present invention relates to a ceramic package for semiconductor chips, which is excellent in productivity, has good productivity, and can be manufactured at low cost.
【０００２】[0002]
【従来の技術】ＳＡＷフィルタ素子等の半導体チップ
は、従来、金属製パッケージに封入されている。しか
し、近年の通信機器の小型化、薄型化に伴い、図３、図
４に示すように、半導体チップをセラミック製のパッケ
ージ基体の表面に実装するタイプのパッケージの形態に
変遷している。2. Description of the Related Art A semiconductor chip such as a SAW filter element is conventionally sealed in a metal package. However, with the recent miniaturization and thinning of communication devices, as shown in FIGS. 3 and 4, the form of a package in which a semiconductor chip is mounted on the surface of a ceramic package base has been changed.
【０００３】図３に示すパッケージは、キャップ３１と
して金属板を用い、セラミック製のパッケージ基体３２
の周縁封止面にコバーリング３３をろう付けし、該コバ
ーリング３２と金属製キャップ３１をシームウェルディ
ングすることで実装した半導体チップ３４を封止するタ
イプである。また図４に示すパッケージは、キャップ４
１としてアルミナセラミック製のキャップを用い、セラ
ミック製のパッケージ基体４２とキャップ４１を低融点
ガラス、半田、あるいは樹脂等４３で、パッケージ基体
４２に実装した半導体チップ４４を封止するタイプであ
る。The package shown in FIG. 3 uses a metal plate as the cap 31 and a ceramic package base 32.
The semiconductor chip 34 is sealed by brazing the cover ring 33 to the peripheral sealing surface of the above and seam welding the cover ring 32 and the metal cap 31. Also, the package shown in FIG.
1 is a type in which a cap made of alumina ceramic is used, and a semiconductor package 44 mounted on the package base 42 is sealed with a ceramic package base 42 and a cap 41 by low melting glass, solder, resin or the like 43.
【０００４】しかし、前者のパッケージの場合、コバー
リングを用いるため価格面で高価になり、また後者の場
合は、高強度でかつ安価であるものの、キャップがセラ
ミック製であるため導電性がなく、電磁シールド効果が
得られず、実装した半導体チップが外部からの電気的ノ
イズによって誤動作・故障するおそれがある。However, in the case of the former package, the cost is expensive because the cover ring is used, and in the latter case, although the cap is made of ceramic, it is not electrically conductive because of its high strength and is inexpensive. The shielding effect cannot be obtained, and the mounted semiconductor chip may malfunction or fail due to electrical noise from the outside.
【０００５】そこで、近年では、図４に示すパッケージ
を改良して、図５に示すように、セラミック製キャップ
５１の内表面５２および／又は外表面５３に電磁シール
ド層５４を設けたパッケージ用のセラミックキャップが
提案されている（特開平４−１５１８５８号公報参
照）。該セラミックキャップは、電磁シールド層５４を
無電解銅めっきによって封止面５５を除くキャップ表面
に形成している。そして、このセラミックキャップによ
れば、外部からの電磁波・電気的ノイズの影響による実
装した半導体チップの誤動作・故障を防止できる。Therefore, in recent years, the package shown in FIG. 4 has been improved, and as shown in FIG. 5, the package is provided with an electromagnetic shield layer 54 on the inner surface 52 and / or the outer surface 53 of the ceramic cap 51. A ceramic cap has been proposed (see Japanese Patent Laid-Open No. 4-151858). In the ceramic cap, the electromagnetic shield layer 54 is formed on the cap surface excluding the sealing surface 55 by electroless copper plating. With this ceramic cap, it is possible to prevent malfunction and failure of the mounted semiconductor chip due to the influence of external electromagnetic waves and electrical noise.
【０００６】[0006]
【発明が解決しようとする課題】しかし、前述した半導
体チップ用セラミックパッケージの場合、『パッケージ
をプリント基板等に装着（実装）した際、前記キャップ
の電磁シールド層をグランド電位とすることが難しく、
十分な電磁シールド効果が得られない。』という課題が
ある。However, in the case of the above-mentioned ceramic package for semiconductor chips, it is difficult to set the electromagnetic shield layer of the cap to the ground potential when the package is mounted (mounted) on a printed circuit board or the like.
It is not possible to obtain a sufficient electromagnetic shield effect. There is a problem called ".
【０００７】本発明は、以上のような課題に対処して創
作したものであって、その目的とする処は、キャップの
内表面をグランド電位とすることが簡単で、優れた電磁
シールド効果が得られ、また生産性が良好で、安価に製
造できる半導体チップ用セラミックパッケージを提供す
ることにある。The present invention has been made in response to the above-mentioned problems, and the purpose thereof is to easily set the inner surface of the cap to the ground potential and to obtain an excellent electromagnetic shield effect. An object of the present invention is to provide a ceramic package for a semiconductor chip, which is obtained, has good productivity, and can be manufactured at low cost.
【０００８】[0008]
【課題を解決するための手段】そして、上記課題を解決
するための手段としての本発明の請求項１の半導体チッ
プ用セラミックパッケージは、半導体チップを搭載する
セラミック製のパッケージ基体と、該パッケージ基体に
被着するセラミック製のキャップを有する半導体チップ
用セラミックパッケージにおいて、該キャップの内表面
に銅めっき層を設け、また該キャップの封止面に銅めっ
き層を介して封止用半田層を設け、該封止面の銅めっき
層は内表面の銅めっき層と電気的に接続されていて、ま
た前記パッケージ基体の封止面にグランド電極を設け、
該キャップを該パッケージ基体に被着すると共に、該封
止用半田層を介して封止した際、該キャップの封止面の
銅めっき層が該パッケージ基体のグランド電極と電気的
に接続されてグランド電極層を形成し、前記キャップの
内表面の銅めっき層が電磁シールド層を形成してなる構
成としている。A ceramic package for a semiconductor chip according to claim 1 of the present invention as a means for solving the above problems is a ceramic package base on which a semiconductor chip is mounted, and the package base. In a ceramic package for semiconductor chips having a ceramic cap to be adhered to, a copper plating layer is provided on the inner surface of the cap, and a sealing solder layer is provided on the sealing surface of the cap via the copper plating layer. The copper plating layer on the sealing surface is electrically connected to the copper plating layer on the inner surface, and a ground electrode is provided on the sealing surface of the package base.
When the cap is applied to the package base and sealed with the sealing solder layer, the copper plating layer on the sealing surface of the cap is electrically connected to the ground electrode of the package base. A ground electrode layer is formed, and the copper plating layer on the inner surface of the cap forms an electromagnetic shield layer.
【０００９】請求項２の半導体チップ用セラミックパッ
ケージは、前記請求項１の半導体チップ用セラミックパ
ッケージにおいて、前記キャップの外側周面に銅めっき
層を設けてなる構成としている。According to a second aspect of the present invention, there is provided a ceramic package for a semiconductor chip according to the first aspect, wherein a copper plating layer is provided on an outer peripheral surface of the cap.
【００１０】[0010]
【作用】本発明の請求項１の半導体チップ用セラミック
パッケージは、パッケージ基体の半導体チップ搭載部に
ＳＡＷフィルタ素子等の半導体チップを実装し、該パッ
ケージ基体にキャップを被着し、該キャップの封止面の
封止用半田層を介して封止した後、これをプリント基板
等に実装し、通信機器等に組み込み、かつ該通信機器の
電源を投入すると、前記封止用半田層は導電性を有する
ので、前記キャップの封止面の銅めっき層は、前記パッ
ケージ基体の封止面のグランド電極と電気的に接続され
てグランド電極層を形成する。また該グランド電極層を
形成する銅めっき層は、前記キャップの内表面の銅めっ
き層と電気的に接続されているので、該内表面の銅めっ
き層がグランド電位にされて電磁シールド層を形成す
る。In the ceramic package for a semiconductor chip according to claim 1 of the present invention, a semiconductor chip such as a SAW filter element is mounted on the semiconductor chip mounting portion of the package base, a cap is attached to the package base, and the cap is sealed. After sealing through the sealing solder layer on the stop surface, mounting this on a printed circuit board, etc., incorporating it in communication equipment, etc., and turning on the power of the communication equipment, the sealing solder layer becomes conductive. Therefore, the copper plating layer on the sealing surface of the cap is electrically connected to the ground electrode on the sealing surface of the package base to form a ground electrode layer. Moreover, since the copper plating layer forming the ground electrode layer is electrically connected to the copper plating layer on the inner surface of the cap, the copper plating layer on the inner surface is set to the ground potential to form an electromagnetic shield layer. To do.
【００１１】請求項２の半導体チップ用セラミックパッ
ケージは、前記キャップの外側周面に銅めっき層を設け
てあるので、前記パッケージ基体にキャップを被着し、
該キャップの封止面の封止用半田層を溶融した際、該封
止用半田層を形成する半田が前記銅めっき層を流れてメ
ニスカスを形成する。In the ceramic package for a semiconductor chip according to the present invention, since the copper plating layer is provided on the outer peripheral surface of the cap, the cap is attached to the package base,
When the sealing solder layer on the sealing surface of the cap is melted, the solder forming the sealing solder layer flows through the copper plating layer to form a meniscus.
【００１２】[0012]
【実施例】以下、図面を参照しながら、本発明を具体化
した実施例について説明する。ここに、図１〜図２は、
本発明の実施例を示し、図１は封止前のセラミックパッ
ケージの断面図、図２は封止後のセラミックパッケージ
の断面図である。Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are as follows.
FIG. 1 is a sectional view of a ceramic package before sealing, and FIG. 2 is a sectional view of a ceramic package after sealing.
【００１３】本実施例の半導体チップ用セラミックパッ
ケージは、図１〜図２に示すように、半導体チップａを
搭載（実装）するセラミック製のパッケージ基体１と、
パッケージ基体１に被着するセラミック製のキャップ１
０を有している。As shown in FIGS. 1 and 2, a ceramic package for a semiconductor chip of this embodiment includes a ceramic package base 1 on which a semiconductor chip a is mounted (mounted),
Ceramic cap 1 attached to the package base 1
Has 0.
【００１４】パッケージ基体１は、上面の半導体チップ
搭載部２の周囲の封止面３にグランド電極（メタライズ
層）４を有し、また底面５に信号用電極と電源用電極
（図示せず）、およびグランド電極６を有し、封止面３
のグランド電極４はスルーホール等７を介して底面５の
グランド電極６と電気的に接続されている。The package base 1 has a ground electrode (metallized layer) 4 on a sealing surface 3 around the semiconductor chip mounting portion 2 on the upper surface, and a signal electrode and a power electrode (not shown) on the bottom surface 5. , And the ground electrode 6, and the sealing surface 3
The ground electrode 4 is electrically connected to the ground electrode 6 on the bottom surface 5 through a through hole 7 or the like.
【００１５】キャップ１０は、中央内側に凹部を備えた
キャップであって、セラミック製のキャップ本体１１の
内表面１２には銅めっき層１３、封止面１４には銅めっ
き層１５、外側周面１６の下端側縁には銅めっき層１７
が設けられていて、銅めっき層１３，１５，１７は電気
的に接続されている。また封止面１４の銅めっき層１５
の上には半田層１８が設けられている。The cap 10 is a cap having a concave portion inside the center, and the inner surface 12 of the ceramic cap body 11 is a copper plating layer 13, the sealing surface 14 is a copper plating layer 15, and the outer peripheral surface. A copper plating layer 17 is provided on the lower end side edge of 16.
Are provided, and the copper plating layers 13, 15, and 17 are electrically connected. Further, the copper plating layer 15 on the sealing surface 14
A solder layer 18 is provided on the above.
【００１６】ところで、キャップ１０は、原料アルミ
ナ、フラックスの混合・粉砕物にバインダーを添加、攪
拌、乾燥すると共に、粉体プレス成形、焼成して作製し
たキャップ本体１１の表面に無電解銅めっき処理をして
厚みが０．５〜１．０μｍの無電解銅めっき層を形成
し、該無電解銅めっき層に電解銅めっき処理により厚み
が５〜１０μｍの電解銅めっき層を形成し、更にキャッ
プ本体１１の内表面１２，封止面１４および外側周面１
６を除く部位の銅めっき層部分をエッチングや研磨等で
取り除きいた後、銅めっき層１３，１５，１７を有する
キャップ本体１１の封止面１４の銅めっき層１５に厚み
が５０〜１５０μｍの半田層１８を形成することで作製
している。By the way, as for the cap 10, a binder is added to a mixture and pulverized material of raw material alumina and flux, and the mixture is stirred and dried, and the surface of the cap body 11 produced by powder press molding and firing is electroless copper plated. To form an electroless copper plating layer having a thickness of 0.5 to 1.0 μm, an electrolytic copper plating layer having a thickness of 5 to 10 μm is formed on the electroless copper plating layer by electrolytic copper plating, and a cap is further formed. Inner surface 12, sealing surface 14 and outer peripheral surface 1 of body 11
After removing the copper plating layer portion other than 6 by etching, polishing or the like, solder having a thickness of 50 to 150 μm is formed on the copper plating layer 15 of the sealing surface 14 of the cap body 11 having the copper plating layers 13, 15 and 17. It is manufactured by forming the layer 18.
【００１７】そして、本実施例のパッケージは、パッケ
ージ基体１の半導体チップ搭載部２に半導体チップａを
実装し、パッケージ基体１にキャップ１０を被着し、キ
ャップ１０の封止面１４の半田層１８を溶融すること
で、半導体チップａを封止することができる。ここで、
キャップ１０の外側周面１６に銅めっき層１７による下
地金属層が設けてあるので、前記溶融した半田が銅めっ
き層１７を流れてメニスカスが形成され、封止性を良好
にできる。また、半田層１８は導電性を有するので、キ
ャップ１０の封止面１４の銅めっき層１５は、パッケー
ジ基体１の封止面３のグランド電極４と電気的に接続さ
れてグランド電極層を形成することになる。また該グラ
ンド電極層を形成する銅めっき層１５は、キャップ１０
の内表面１２の銅めっき層１３と電気的に接続されてい
るので、内表面１２の銅めっき層１３は、グランド電極
４と同電位（グランド電位）になり、電磁シールド層を
形成することになる。In the package of this embodiment, the semiconductor chip a is mounted on the semiconductor chip mounting portion 2 of the package base 1, the cap 10 is attached to the package base 1, and the solder layer on the sealing surface 14 of the cap 10 is attached. By melting 18 the semiconductor chip a can be sealed. here,
Since the base metal layer made of the copper plating layer 17 is provided on the outer peripheral surface 16 of the cap 10, the molten solder flows through the copper plating layer 17 to form a meniscus, and the sealing performance can be improved. Moreover, since the solder layer 18 has conductivity, the copper plating layer 15 on the sealing surface 14 of the cap 10 is electrically connected to the ground electrode 4 on the sealing surface 3 of the package base 1 to form a ground electrode layer. Will be done. Further, the copper plating layer 15 forming the ground electrode layer is the cap 10
Since it is electrically connected to the copper plating layer 13 on the inner surface 12, the copper plating layer 13 on the inner surface 12 has the same potential as the ground electrode 4 (ground potential), so that the electromagnetic shield layer is formed. Become.
【００１８】次に、本実施例の半導体チップ用セラミッ
クパッケージの作用・効果を確認するために、パッケー
ジにＳＡＷフィルタ素子を実装・封止し、これをプリン
ト基板の所定の位置に実装し、通信機器に組み込み、外
部からの電磁波・電気的ノイズの影響を調べた処、この
パッケージに実装・封止したＳＡＷフィルタ素子には誤
動作・故障が認められず、また、該ＳＡＷフィルタ素子
から外部への電気的ノイズの発生も確認できなかった。
これは、キャップ１０の内表面１２の銅めっき層１３
が、グランド電位にされて、電磁シールド効果を発揮し
たことによる。Next, in order to confirm the operation and effect of the ceramic package for a semiconductor chip of this embodiment, a SAW filter element is mounted and sealed in the package, and this is mounted at a predetermined position on a printed board for communication. When the influence of electromagnetic waves and electric noise from the outside on the SAW filter element incorporated in the equipment was examined, no malfunction or failure was found in the SAW filter element mounted / sealed in this package. The generation of electrical noise could not be confirmed.
This is the copper plating layer 13 on the inner surface 12 of the cap 10.
However, it was caused by the fact that it was brought to the ground potential and exhibited the electromagnetic shielding effect.
【００１９】なお、本発明は、上述した実施例に限定さ
れるものでなく、本発明の要旨を変更しない範囲内で変
形実施できる構成を含む。因みに、前述した実施例で
は、キャップの外側周面に下地金属層を形成する銅めっ
き層を設けた構成で説明したが、該銅めっき層は、キャ
ップの内表面と封止面にのみ設けた構成としてもよいこ
とは当然である。It should be noted that the present invention is not limited to the above-described embodiments, but includes configurations that can be modified and implemented within the scope of the present invention. Incidentally, in the above-mentioned embodiment, the description has been given with the configuration in which the copper plating layer for forming the base metal layer is provided on the outer peripheral surface of the cap, but the copper plating layer is provided only on the inner surface and the sealing surface of the cap. As a matter of course, it may be configured.
【００２０】[0020]
【発明の効果】以上の説明より明らかなように、本発明
の請求項１の半導体チップ用セラミックパッケージによ
れば、キャップの封止面の封止用半田層は導電性を有す
るので、該キャップの封止面の銅めっき層が、パッケー
ジ基体の封止面のグランド電極と電気的に接続されてグ
ランド電極層を形成することになり、また該グランド電
極層を形成する銅めっき層は、前記キャップの内表面の
銅めっき層と電気的に接続されているので、該内表面の
銅めっき層がグランド電位にされて電磁シールド層を形
成することになることから、該内表面の銅めっき層の電
磁シールド効果をいっそう良好にでき、マイクロ波特性
に優れた半導体チップ用セラミックパッケージを提供で
きるという効果を有する。As is apparent from the above description, according to the ceramic package for a semiconductor chip of claim 1 of the present invention, since the sealing solder layer on the sealing surface of the cap is conductive, The copper plating layer on the sealing surface of is electrically connected to the ground electrode on the sealing surface of the package base to form a ground electrode layer, and the copper plating layer forming the ground electrode layer is Since it is electrically connected to the copper plating layer on the inner surface of the cap, the copper plating layer on the inner surface is set to the ground potential to form an electromagnetic shield layer. The electromagnetic shield effect can be further improved, and a ceramic package for semiconductor chips having excellent microwave characteristics can be provided.
【００２１】請求項２の半導体チップ用セラミックパッ
ケージによれば、前記キャップの外側周面に銅めっき層
を設けてあるので、前記パッケージ基体にキャップを被
着し、該キャップの封止面の封止用半田層を溶融した
際、該封止用半田層を形成する半田が前記銅めっき層を
流れてメニスカスを形成することから、封止性をいっそ
う良好にすることができるという効果を有する。According to the ceramic package for a semiconductor chip of claim 2, since the copper plating layer is provided on the outer peripheral surface of the cap, the cap is adhered to the package base, and the sealing surface of the cap is sealed. When the stopping solder layer is melted, the solder forming the sealing solder layer flows through the copper plating layer to form a meniscus, so that the sealing property can be further improved.
【図１】 本発明の実施例を示し、封止前のセラミック
パッケージの断面図である。FIG. 1 is a cross-sectional view of a ceramic package before sealing, showing an embodiment of the present invention.
【図２】 封止後のセラミックパッケージの断面図であ
る。FIG. 2 is a cross-sectional view of the ceramic package after sealing.
【図３】 従来例の断面図である。FIG. 3 is a sectional view of a conventional example.
【図４】 従来例の断面図である。FIG. 4 is a sectional view of a conventional example.
【図５】 従来例の断面図である。FIG. 5 is a sectional view of a conventional example.
ａ・・・半導体チップ、１・・・パッケージ基体、２・
・・半導体チップ搭載部、３・・・パッケージ基体の封
止面、４・・・グランド電極（メタライズ層）、５・・
・パッケージ基体の底面、６・・・グランド電極、７・
・・スルーホール等、１０・・・キャップ、１１・・・
キャップ本体、１２・・・内表面、１３・・・銅めっき
層（電磁シールド層）、１４・・・封止面、１５・・・
銅めっき層（グランド電極層）、１６・・・外側周面、
１７・・・銅めっき層（下地金属層）、１８・・・半田
層、３１，４１・・・キャップ、３２，４２・・・パッ
ケージ基体、３３・・・コバーリング、３４，４４・・
・半導体チップ、４３・・・低融点ガラス、半田、ある
いは樹脂等、５１・・・キャップ、５２・・・キャップ
の内表面、５３キャップの外表面、５４・・・電磁シー
ルド層、５５・・・封止面a ... Semiconductor chip, 1 ... Package base, 2 ...
..Semiconductor chip mounting portion, 3 ... Sealing surface of package base, 4 ... Ground electrode (metallized layer), 5 ...
・ Bottom of package base, 6 ・ ・ ・ Ground electrode, 7 ・
..Through holes, etc., 10 ... Caps, 11 ...
Cap body, 12 ... Inner surface, 13 ... Copper plating layer (electromagnetic shield layer), 14 ... Sealing surface, 15 ...
Copper plating layer (ground electrode layer), 16 ... Outer peripheral surface,
17 ... Copper plating layer (base metal layer), 18 ... Solder layer, 31, 41 ... Cap, 32, 42 ... Package base, 33 ... Kober ring, 34, 44 ...
・ Semiconductor chip, 43 ... Low melting point glass, solder, resin, etc., 51 ... Cap, 52 ... Inner surface of cap, 53 Outer surface of cap, 54 ... Electromagnetic shield layer, 55 ...・ Sealing surface
Claims (2)
パッケージ基体と、該パッケージ基体に被着するセラミ
ック製のキャップを有する半導体チップ用セラミックパ
ッケージにおいて、該キャップの内表面に銅めっき層を
設け、また該キャップの封止面に銅めっき層を介して封
止用半田層を設け、該封止面の銅めっき層は内表面の銅
めっき層と電気的に接続されていて、また前記パッケー
ジ基体の封止面にグランド電極を設け、該キャップを該
封止用半田層を介して該パッケージ基体に封止した際、
該キャップの封止面の銅めっき層が該パッケージ基体の
グランド電極と電気的に接続されてグランド電極層を形
成し、前記キャップの内表面の銅めっき層が電磁シール
ド層を形成してなることを特徴とする半導体チップ用セ
ラミックパッケージ。1. A ceramic package for semiconductor chips, comprising a ceramic package base on which a semiconductor chip is mounted and a ceramic cap adhered to the package base, wherein a copper plating layer is provided on the inner surface of the cap, A sealing solder layer is provided on the sealing surface of the cap via a copper plating layer, and the copper plating layer on the sealing surface is electrically connected to the copper plating layer on the inner surface. When a ground electrode is provided on the sealing surface and the cap is sealed to the package base through the sealing solder layer,
The copper plating layer on the sealing surface of the cap is electrically connected to the ground electrode of the package base to form a ground electrode layer, and the copper plating layer on the inner surface of the cap forms an electromagnetic shield layer. A ceramic package for semiconductor chips.
設けてなる請求項１に記載の半導体チップ用セラミック
パッケージ。2. The ceramic package for a semiconductor chip according to claim 1, wherein a copper plating layer is provided on an outer peripheral surface of the cap.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7081973A JPH08250615A (en) | 1995-03-13 | 1995-03-13 | Ceramic package for semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7081973A JPH08250615A (en) | 1995-03-13 | 1995-03-13 | Ceramic package for semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08250615A true JPH08250615A (en) | 1996-09-27 |
Family
ID=13761442
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7081973A Pending JPH08250615A (en) | 1995-03-13 | 1995-03-13 | Ceramic package for semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08250615A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11274344A (en) * | 1998-03-20 | 1999-10-08 | Nec Kansai Ltd | Package for sealing electronic element and electronic element sealing structure thereof |
| US6822880B2 (en) | 2001-09-28 | 2004-11-23 | Raytheon Company | Multilayer thin film hydrogen getter and internal signal EMI shield for complex three dimensional electronic package components |
| JP2005244214A (en) * | 2004-02-24 | 2005-09-08 | Samsung Electronics Co Ltd | Semiconductor element and method for preventing electrostatic discharge |
| KR100519750B1 (en) * | 2001-05-10 | 2005-10-07 | 삼성전자주식회사 | Chip scale packaging structure sealed with low temperature Co-fired ceramic and the method thereof |
| JP2008047701A (en) * | 2006-08-16 | 2008-02-28 | Nippon Telegr & Teleph Corp <Ntt> | Optical module |
| US7557307B2 (en) | 2004-12-02 | 2009-07-07 | Murata Manufacturing Co., Ltd. | Electronic component and its manufacturing method |
| CN105304618A (en) * | 2015-12-04 | 2016-02-03 | 贵州振华风光半导体有限公司 | Integration method of anti-interference and anti-corrosion semiconductor integrated circuit |
| CN105489545A (en) * | 2015-12-04 | 2016-04-13 | 贵州振华风光半导体有限公司 | Integration method for anti-interference and corrosion-resistant thin film hybrid integrated circuit |
| CN105489505A (en) * | 2015-12-04 | 2016-04-13 | 贵州振华风光半导体有限公司 | Integration method for anti-interference and corrosion-resistant thin film hybrid integrated circuit |
| CN108063130A (en) * | 2017-12-29 | 2018-05-22 | 江苏长电科技股份有限公司 | There is electromagnetic shielding encapsulating structure and its manufacturing process that pin side wall climbs tin |
| WO2020022278A1 (en) * | 2018-07-27 | 2020-01-30 | Ａｇｃ株式会社 | Optical package |
-
1995
- 1995-03-13 JP JP7081973A patent/JPH08250615A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11274344A (en) * | 1998-03-20 | 1999-10-08 | Nec Kansai Ltd | Package for sealing electronic element and electronic element sealing structure thereof |
| KR100519750B1 (en) * | 2001-05-10 | 2005-10-07 | 삼성전자주식회사 | Chip scale packaging structure sealed with low temperature Co-fired ceramic and the method thereof |
| US6822880B2 (en) | 2001-09-28 | 2004-11-23 | Raytheon Company | Multilayer thin film hydrogen getter and internal signal EMI shield for complex three dimensional electronic package components |
| JP2005244214A (en) * | 2004-02-24 | 2005-09-08 | Samsung Electronics Co Ltd | Semiconductor element and method for preventing electrostatic discharge |
| US7557307B2 (en) | 2004-12-02 | 2009-07-07 | Murata Manufacturing Co., Ltd. | Electronic component and its manufacturing method |
| JP2008047701A (en) * | 2006-08-16 | 2008-02-28 | Nippon Telegr & Teleph Corp <Ntt> | Optical module |
| CN105304618A (en) * | 2015-12-04 | 2016-02-03 | 贵州振华风光半导体有限公司 | Integration method of anti-interference and anti-corrosion semiconductor integrated circuit |
| CN105489545A (en) * | 2015-12-04 | 2016-04-13 | 贵州振华风光半导体有限公司 | Integration method for anti-interference and corrosion-resistant thin film hybrid integrated circuit |
| CN105489505A (en) * | 2015-12-04 | 2016-04-13 | 贵州振华风光半导体有限公司 | Integration method for anti-interference and corrosion-resistant thin film hybrid integrated circuit |
| CN108063130A (en) * | 2017-12-29 | 2018-05-22 | 江苏长电科技股份有限公司 | There is electromagnetic shielding encapsulating structure and its manufacturing process that pin side wall climbs tin |
| WO2020022278A1 (en) * | 2018-07-27 | 2020-01-30 | Ａｇｃ株式会社 | Optical package |
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