KR100519750B1 - Chip scale packaging structure sealed with low temperature Co-fired ceramic and the method thereof - Google Patents
Chip scale packaging structure sealed with low temperature Co-fired ceramic and the method thereof Download PDFInfo
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- KR100519750B1 KR100519750B1 KR10-2001-0025571A KR20010025571A KR100519750B1 KR 100519750 B1 KR100519750 B1 KR 100519750B1 KR 20010025571 A KR20010025571 A KR 20010025571A KR 100519750 B1 KR100519750 B1 KR 100519750B1
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- 239000000919 ceramic Substances 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims description 10
- 238000004806 packaging method and process Methods 0.000 title abstract description 9
- 238000007789 sealing Methods 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 229910000679 solder Inorganic materials 0.000 claims abstract description 16
- 229910010293 ceramic material Inorganic materials 0.000 claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 5
- 239000006071 cream Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 2
- 238000005406 washing Methods 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 2
- 230000035939 shock Effects 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 31
- 239000010931 gold Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 7
- 238000000635 electron micrograph Methods 0.000 description 4
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 3
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
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Abstract
본 발명은 저온소결 세라믹으로 실링된 칩 스케일 패키지 구조체 및 그 제조방법에 관하여 개시한다. 저온소결 세라믹으로 실링된 칩 스케일 패키지 구조체는, MEMS 소자 또는 전자회로가 집적되어 있는 반도체칩; 상기 반도체칩의 상방에서 위치하는 저온소결 세라믹 소재; 및 상기 세라믹 소재와 상기 반도체칩 사이에 개재하여 그들간의 전기적 신호를 접속시키며 그중 외부에 형성된 것은 그들을 외부로부터 밀봉실링하는 실링부를 형성하는 솔더범프들;을 구비한다. 이에 따르면, 웨이퍼 레벨에서 칩스케일의 패키징이 가능해지고 밀봉실링이 되므로 습기의 영향을 방지할 수 있으며 낮은 온도에서의 본딩으로 열적 충격에 약한 제품에도 적용이 가능하며, 칩온칩(Chip On Chip) 기술에 의해 소형의 모듈의 구성이 가능해지는 효과가 있다.The present invention discloses a chip scale package structure sealed with low temperature sintered ceramic and a method of manufacturing the same. A chip scale package structure sealed with low temperature sintered ceramic includes: a semiconductor chip in which an MEMS element or an electronic circuit is integrated; A low temperature sintered ceramic material positioned above the semiconductor chip; And solder bumps interposed between the ceramic material and the semiconductor chip to connect electrical signals therebetween, the solder bumps forming a sealing part sealingly sealing them from the outside. This enables chip-scale packaging and sealing sealing at the wafer level to prevent the effects of moisture, and can be applied to products that are susceptible to thermal shock by bonding at low temperatures, and chip on chip technology. This makes it possible to configure a small module.
Description
본 발명은 저온소결 세라믹으로 실링된 칩 스케일 패키지 구조체 및 그 제조방법에 관한 것으로서, 더욱 상세하게는 MEMS(Micro Electro Mechanical System) 소자 또는 집적회로소자를 포함하는 반도체칩 상에 저온소결 세라믹을 적층하고 그들간을 실링한 칩 스케일 패키지 구조체 및 그 제조방법에 관한 것이다.The present invention relates to a chip scale package structure sealed with a low temperature sintered ceramic and a method of manufacturing the same. More particularly, the low temperature sintered ceramic is laminated on a semiconductor chip including a micro electro mechanical system (MEMS) device or an integrated circuit device. It relates to a chip scale package structure sealed between them and a method of manufacturing the same.
RF(Radio Frequency) 집적회로 또는 RF MEMS 소자와 같이 RF 또는 밀리미터파 대역의 신호를 다루는 소자들을 일반적인 집적회로 패키징 방법을 사용시 높은 Q-값과 낮은 손실(Loss)를 구현하기가 어려우며, 또 개별 칩을 패키징하는 경우 다이싱(dicing) 과정중 오염 또는 파손이 일어날 수 있으며, 제조단가가 상승한다. 또한, MEMS 소자를 패키징하기 위한 통상의 기계적인 패키징 방법은 칩의 손상을 가져올 우려가 있다. Devices that handle signals in the RF or millimeter-wave bands, such as radio frequency (RF) integrated circuits or RF MEMS devices, are difficult to achieve high Q-values and low losses when using conventional integrated circuit packaging methods. In the case of packaging, contamination or breakage may occur during the dicing process, and the manufacturing cost increases. In addition, conventional mechanical packaging methods for packaging MEMS devices may cause chip damage.
도 1에는 미국특허 제6,062,461호에 따른 MEMS 구조를 패키징 하기 위해서 별도의 캐핑 웨이퍼(capping wafer)를 사용하는 발명이 개시되어 있다. 도면을 참조하면, MEMS 구조의 작동공간을 위해서 공동(cavity: 16)이 형성된 캐핑 웨이퍼(12)와 소자 웨이퍼(10)간의 밀봉실링을 위해서 솔더러블 링(18)과 솔더러블 층(20) 사이의 용융을 이용하여 MEMS구조(14)를 그 안에 실링하는 것이다.FIG. 1 discloses an invention using a separate capping wafer to package a MEMS structure according to US Pat. No. 6,062,461. Referring to the drawings, between the solderable ring 18 and the solderable layer 20 for sealing sealing between the device wafer 10 and the capping wafer 12 in which the cavity 16 is formed for the working space of the MEMS structure. The MEMS structure 14 is sealed therein using the melting of.
그러나, 이러한 기술은 외부와의 전기적 연결을 위해서 밀봉되지 않은 외부에 전극(22)을 형성하므로 인터커넥션을 위한 실장면적이 늘어나는 문제와 캐핑웨이퍼를 이용한 고밀도 집적 모듈을 이용하지 못하는 문제가 있다.However, this technique has a problem in that the mounting area for the interconnection is not formed for the electrical connection with the outside, so that the mounting area for the interconnection is increased and the high density integrated module using the capping wafer cannot be used.
따라서 본 발명은 상기의 문제점을 개선하고자 창출된 것으로서, 본 발명의 목적은 캐핑웨이퍼로서 내부 또는 외부에 수동소자를 구비하는 저온소결 세라믹 소재와 MEMS소자 또는 집적회로소자를 가진 반도체칩을 적층하여 실링된 칩 스케일 패키지 구조체를 제공하는 것이다.Accordingly, the present invention was created to improve the above problems, and an object of the present invention is to seal a low-temperature sintered ceramic material having a passive element inside or outside as a capping wafer and a semiconductor chip having a MEMS device or an integrated circuit device. To provide a chip scale package structure.
본 발명의 다른 목적은 상기 패키지의 실링을 웨이퍼 레벨에서 행하는 제조방법을 제공하는 것이다. Another object of the present invention is to provide a manufacturing method for sealing the package at the wafer level.
상기의 목적을 달성하기 위하여 본 발명의 저온소결 세라믹으로 실링된 칩 스케일 패키지 구조체는, MEMS 소자 또는 전자회로가 집적되어 있는 반도체칩; 상기 반도체칩의 상방에서 위치하는 저온소결 세라믹 소재; 및 상기 세라믹 소재와 상기 반도체칩 사이에 개재하여 그들간의 전기적 신호를 접속시키며 그중 외부에 형성된 것은 그들을 외부로부터 밀봉실링하는 실링부를 형성하는 솔더범프들;을 구비한다. In order to achieve the above object, a chip scale package structure sealed with a low-temperature sintered ceramic of the present invention includes a semiconductor chip in which an MEMS device or an electronic circuit is integrated; A low temperature sintered ceramic material positioned above the semiconductor chip; And solder bumps interposed between the ceramic material and the semiconductor chip to connect electrical signals therebetween, the solder bumps forming a sealing part sealingly sealing them from the outside.
상기 저온소결 세라믹 소재는 다층구조로서, 그 내부에 위치하는 비아홀들; 상기 비아홀안을 채운 도전체; 상기 도전체의 상부에 연결되어 외부와의 전기적 연결을 제공하는 전극들; 및 상기 저온소결 세라믹 소재 내부 또는 외부에 집적되어 형성된 수동소자;를 구비하는 것이 바람직하다. The low-temperature sintered ceramic material has a multilayer structure, via holes located therein; A conductor filling the via hole; Electrodes connected to the top of the conductor to provide electrical connection with the outside; And a passive element formed by being integrated inside or outside the low-temperature sintered ceramic material.
또한, 상기 외부연결전극 상에 위치하는 BGA들(Ball grid arrays); 및 상기 BGA들에 연결되어 그 위에 집적된 능동소자;를 더 구비할 수도 있다.In addition, ball grid arrays (BGAs) disposed on the external connection electrode; And an active device connected to and integrated on the BGAs.
상기의 다른 목적을 달성하기 위하여 본 발명의 웨이퍼 레벨에서 저온소결 세라믹으로 실링하는 칩 스케일 패키지 구조체 제조방법은, (가) 저온소결 세라믹 웨이퍼에 비아홀들을 형성하는 단계; (나) 상기 비아홀들을 도전성 페이스트로 채우는 단계; (다) 상기 저온소결 세라믹 웨이퍼의 양면을 Cr/Au 증착한 후, 형성된 Cr/Au 막을 패터닝하는 단계; (라) 상기 저온소결 세라믹 웨이퍼의 하부에 라미네이터 필름을 붙인 후, 패터닝하는 단계; (마) 상기 패턴된 필름 사이로 크림 솔더(cream solder)를 채운 후, 리플로우(reflow)시키는 단계; (바) 상기 필름을 아세톤으로 제거한 후, 세척액으로 세척하는 단계; 및 (사) 상기 저온소결 세라믹 웨이퍼를 MEMS 스위치 및/또는 집적회로소자를 구비한 반도체 웨이퍼상에 본딩하는 단계;를 구비한다. In order to achieve the above object, the chip scale package structure manufacturing method of sealing with low temperature sintered ceramic at the wafer level of the present invention, (A) forming via holes in the low temperature sintered ceramic wafer; (B) filling the via holes with a conductive paste; (C) Cr / Au deposition of both surfaces of the low-temperature sintered ceramic wafer, and then patterning the formed Cr / Au film; (D) attaching a laminator film to the lower portion of the low-temperature sintered ceramic wafer and then patterning it; (E) filling a cream solder with the patterned film and then reflowing it; (F) removing the film with acetone and then washing with a wash solution; And (g) bonding the low-temperature sintered ceramic wafer onto a semiconductor wafer having a MEMS switch and / or an integrated circuit device.
상기 (가) 단계에서 상기 저온소결 세라믹 웨이퍼의 각 소자는 그 내부 또는 외부에 수동소자를 포함하는 것이 바람직하다.In the step (a), each element of the low-temperature sintered ceramic wafer preferably includes a passive element inside or outside thereof.
또한, 상기 (다) 단계 이후에 상기 저온소결 세라믹 웨이퍼의 상부의 Cr/Au 막 상부에 BGA를 형성하는 단계; 및 상기 BGA 상부에 집적된 능동소자를 마련하는 단계;를 더 구비할 수 있다.In addition, after the step (c) to form a BGA on top of the Cr / Au film of the low-temperature sintered ceramic wafer; And providing an active device integrated on the BGA.
이하 첨부도면을 참조하여 본 발명의 저온소결 세라믹으로 실링된 칩 스케일 패키지 구조체에 따른 실시예를 상세히 설명한다. Hereinafter, embodiments of the chip scale package structure sealed with the low-temperature sintered ceramic of the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명의 일 실시예에 의한 저온소결 세라믹으로 실링된 칩 스케일 패키지 구조체의 단면도를 나타낸 것이다. 2 illustrates a cross-sectional view of a chip scale package structure sealed with low temperature sintered ceramic according to an embodiment of the present invention.
도면을 참조하면, 소자웨이퍼(100) 상에 다수의 제1전극(102)과 MEMS소자(104)가 형성되어 있다. 상기 제1전극(102)은 Cr/Au막이 300Å/200㎛ 증착된 것이며, MEMS소자로서는 외팔보 또는 양팔보, 스프링 등으로 다양하게 기판(100) 상에 지지될 수 있으며, 집적회로소자도 이용가능하다. Referring to the drawings, a plurality of first electrodes 102 and a MEMS device 104 are formed on the device wafer 100. The first electrode 102 is a 300 / 200㎛ deposited Cr / Au film, can be supported on the substrate 100 in a variety of cantilever, cantilever, spring, etc. as a MEMS device, an integrated circuit device is also available Do.
상기 제1전극(102) 상에는 상방에 형성되는 저온소결 세라믹 기판(140)과의 전기적 연결(122)과 외부 밀봉실링부(124)를 제공하는 다수의 솔더범프(120)가 형성되어 있으며, 상기 솔더범프(120) 상에는 제1전극(102)과 같은 Cr/Au 막인 제2전극(126)이 형성되어 있다. A plurality of solder bumps 120 are formed on the first electrode 102 to provide an electrical connection 122 and an external sealing seal 124 with the low temperature sintered ceramic substrate 140 formed thereon. The second electrode 126, which is a Cr / Au film, such as the first electrode 102, is formed on the solder bumps 120.
상기 제2전극(126) 상에는 캐핑웨이퍼인 저온소결 세라믹 기판(140)이 형성되어 있다. 상기 저온소결 세라믹기판(140)은 듀퐁사의 상품명 "Green Tape"로 불리는 저온소결 세라믹 재료(141)가 여러장 겹쳐져 형성되어 그 내부에는 다수의 비아홀(142)과 그를 채운 전기적 도전체(144)가 형성되어 있으며, 상기 비아홀 상에는 외부와의 전기적 연결을 하는 외부전극(146)이 형성되어 있다. 또한 상기 저온소결 세라믹 기판(140)의 내부에는 릴레이, 가변 커패시터 또는 가변 인덕터와 같은 수동소자(148)가 형성될 수도 있다.The low temperature sintered ceramic substrate 140, which is a capping wafer, is formed on the second electrode 126. The low-temperature sintered ceramic substrate 140 is formed by stacking a plurality of low-temperature sintered ceramic materials 141 called DuPont's trade name "Green Tape", and a plurality of via holes 142 and electrical conductors 144 filled therein are formed therein. The external electrode 146 is formed on the via hole to be electrically connected to the outside. In addition, a passive element 148 such as a relay, a variable capacitor, or a variable inductor may be formed in the low temperature sintered ceramic substrate 140.
상기와 같이 구성된 본 발명의 칩 스케일 패키지 구조체는 반도체칩의 크기로 반도체 패키지를 형성할 수 있는 것으로, 그 작용은 소자 웨이퍼(100)로부터 출력된 신호가 제1전극(102)과 솔더 범프(120)를 통해 제2전극(126) 및 외부전극(146)으로 전달되며, 상기 외부전극(146)으로 전달된 신호는 주기판(Mother Board)로 전달되어 주변소자로 전달된다. 주변소자에서 발생된 신호가 소자 웨이퍼(100)로 전달되는 경우에는 위에서 설명한 경우의 역순으로 신호가 전달되는 것이다. The chip scale package structure of the present invention configured as described above can form a semiconductor package in the size of a semiconductor chip, the function of which is that the signal output from the device wafer 100 is the first electrode 102 and the solder bumps 120 The second electrode 126 and the external electrode 146 are transferred to the second electrode 126 and the external electrode 146, and the signal transmitted to the external electrode 146 is transferred to the mother board and transferred to the peripheral device. When the signal generated from the peripheral device is transferred to the device wafer 100, the signal is transmitted in the reverse order as described above.
도 3은 도 2의 소자 상부에 능동소자가 집적되는 다른 실시예를 도시한 것이며, 상기 일 실시예에서와 같은 구성요소에 대해서는 같은 참조번호를 사용한다. FIG. 3 illustrates another embodiment in which an active device is integrated on the device of FIG. 2, and the same reference numerals are used for the same components as in the above embodiment.
도면을 참조하면, 외부전극(146) 상부에 BGA(150)가 형성되며, BGA(150) 상부에는 능동소자(160)가 형성되어 있다. 상기 구조의 작용은 상기 실시예에서 설명한 것과 동일하므로 여기서는 생략한다. Referring to the drawings, the BGA 150 is formed on the external electrode 146, and the active element 160 is formed on the BGA 150. Since the operation of the structure is the same as described in the above embodiment, it is omitted here.
이와 같은 본 발명의 저온소결 세라믹 기판으로 실링한 칩 스케일 패키지의 제조방법을 도 4a 내지 도 4g에 개략 단면도로 나타내었다.Such a method of manufacturing a chip scale package sealed with a low temperature sintered ceramic substrate of the present invention is shown in schematic cross-sectional views in FIGS. 4A to 4G.
먼저 도 4a에 도시한 바와 같이, 저온소결 세라믹 웨이퍼(140)를 마련하고 비아홀들(142)을 형성한다. 이때 저온소결 세라믹 웨이퍼(140) 내부에 또는 외부에 수동소자를 형성할 수도 있다.First, as shown in FIG. 4A, a low-temperature sintered ceramic wafer 140 is prepared and via holes 142 are formed. In this case, a passive element may be formed inside or outside the low-temperature sintered ceramic wafer 140.
다음 단계로 상기 비아홀(142)을 금 또는 은과 같은 도전성 페이스트(144)로 채운다(도 4b 참조).Next, the via hole 142 is filled with a conductive paste 144 such as gold or silver (see FIG. 4B).
다음에, 상기 저온소결 세라믹 웨이퍼(140)의 상하면에 Cr/Au를 증착한 후 패터닝하여 제1전극(102) 및 제2전극(122)을 형성하며(도 4c 참조), 본 실시예에서는 Cr/Au막을 300Å/200㎛로 증착하였다. Next, Cr / Au is deposited on the upper and lower surfaces of the low-temperature sintered ceramic wafer 140 and then patterned to form the first electrode 102 and the second electrode 122 (see FIG. 4C). A / Au film was deposited at 300 μs / 200 μm.
또한, 상기 단계 이후에 도 3에서 보듯이 상기 저온소결 세라믹 웨이퍼(140)의 상부의 제2전극(122) 상에 BGA(150)를 형성한 후, BGA(150) 상부에 집적된 능동소자(160)를 마련하는 단계를 더 구비할 수도 있다.In addition, after the step, as shown in FIG. 3, the BGA 150 is formed on the second electrode 122 on the low-temperature sintered ceramic wafer 140, and then the active device integrated on the BGA 150 is formed. 160 may be further provided.
다음으로 저온소결 세라믹 웨이퍼(140)의 하부에 100㎛의 라미네이터 필름(143)을 붙인 후 패터닝한다(도 4d 참조). Next, a 100 μm laminator film 143 is attached to the lower portion of the low temperature sintered ceramic wafer 140 and then patterned (see FIG. 4D).
상기 패턴된 필름(143) 사이로 크림 솔더(145)를 채운후 180 ℃ 정도에서 리플로우(reflow) 시키며, 그에 따라 크림 솔더(145)는 75㎛ 정도로 줄어들면서 제2전극(122) 상에 정렬된다(도 4e 참조).The cream solder 145 is filled between the patterned film 143 and then reflowed at about 180 ° C., so that the cream solder 145 is reduced to about 75 μm and aligned on the second electrode 122. (See FIG. 4E).
다음에 상기 필름(도 4e의 참조번호 143)을 아세톤으로 제거한 후, 이소프로필 알콜 등으로 세척시킨다(도 4f 참조).Next, the film (reference number 143 in FIG. 4E) is removed with acetone and then washed with isopropyl alcohol or the like (see FIG. 4F).
다음으로 MEMS스위치(104)를 구비한 반도체 웨이퍼(100) 상에 상기 저온소결 세라믹 웨이퍼(140)를 정렬시켜서 본딩을 시킨다. 본 실시예에서는 테스트용 공면 도파관(Coplanar Waveguide: CPW) 패턴을 정렬시켜서 약 200 ℃에서 본딩을 시켰다. Next, the low temperature sintered ceramic wafer 140 is aligned and bonded on the semiconductor wafer 100 including the MEMS switch 104. In this embodiment, the test coplanar waveguide (CPW) pattern was aligned and bonded at about 200 ° C.
도 5 내지 도 7은 캐핑웨이퍼로서, 도 5는 라미네이터 필름이 패턴된 상태의 저면을 나타내는 전자현미경 사진이며, 도 6은 도 5에서 솔더 범프를 채우고 리플로우시킨 후 필름이 제거된 상태의 저면을 나타내는 전자현미경 사진이며, 도 7은 캐핑 웨이퍼의 평면을 나타내는 전자현미경 사진이다. 5 to 7 are capping wafers, and FIG. 5 is an electron micrograph showing a bottom surface of a laminator film patterned. FIG. 6 is a bottom surface of a film removed state after filling and reflowing solder bumps in FIG. 5. It is an electron microscope photograph shown, and FIG. 7 is an electron microscope photograph showing the plane of a capping wafer.
표1은 본 발명의 바람직한 실시예에 의해 제조된 샘플을 사용하여 RF측정기계인 HP8510 network analyser로 측정한 RF특성치를 나타낸 것이다. Table 1 shows the RF characteristics measured with the HP8510 network analyzer, an RF measuring machine, using the samples prepared according to the preferred embodiment of the present invention.
표 1에서 보면, 테스트용 CPW 패턴의 경우 주파수 2 GHz에서 삽입손실이 0.1431 dB이었으며, 이를 상기 제조방법으로 패키징하였을 때 삽입손실이 0.2226 dB 이었다. 따라서 패키징 손실은 이들의 차로서 구하면 0.0795 dB로서 매우 양호한 결과를 나타내었다. In Table 1, in the case of the test CPW pattern, the insertion loss was 0.1431 dB at a frequency of 2 GHz, and when it was packaged by the manufacturing method, the insertion loss was 0.2226 dB. Thus, the packaging loss was 0.0795 dB, which is very good result.
이상에서 설명한 바와 같이 본 발명에 따르면, 웨이퍼 레벨에서 칩스케일의 패키징이 가능해지고 밀봉실링이 되므로 외기의 영향을 방지할 수 있으며 낮은 온도에서의 본딩으로 열적 충격에 약한 제품에도 적용이 가능하며, 칩온칩(Chip On Chip) 기술에 의해 소형의 모듈의 구성이 가능해지는 효과가 있다. As described above, according to the present invention, chip-scale packaging and sealing sealing are possible at the wafer level, thereby preventing the influence of outside air, and bonding to a product that is susceptible to thermal shock by bonding at a low temperature is possible. The chip on chip technology enables the configuration of a small module.
본 발명은 도면을 참조하여 실시예를 참고로 설명되었으나, 이는 예시적인 것에 불과하며, 당해 분야에서 통상의 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 실시예가 가능하다는 점을 이해할 것이다. 따라서, 본 발명의 진정한 기술적 보호범위는 첨부된 특허청구범위에 한해서 정해져야 할 것이다. Although the present invention has been described with reference to the embodiments with reference to the drawings, this is merely exemplary, it will be understood by those skilled in the art that various modifications and equivalent embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined only by the appended claims.
도 1은 종래의 MEMS 구조가 밀봉실링되는 구조체를 보여주는 분해 단면도,1 is an exploded cross-sectional view showing a structure in which a conventional MEMS structure is sealed sealed;
도 2는 본 발명의 일 실시예에 의한 저온소결 세라믹으로 실링된 칩 스케일 패키지 구조체의 단면도,2 is a cross-sectional view of a chip scale package structure sealed with low temperature sintered ceramic according to an embodiment of the present invention;
도 3은 본 발명의 다른 실시예에 의한 저온소결 세라믹으로 실링된 칩 스케일 패키지 구조체의 단면도,3 is a cross-sectional view of a chip scale package structure sealed with low temperature sintered ceramic according to another embodiment of the present invention;
도 4a 내지 도 4g는 본 발명에 따른 웨이퍼 레벨에서 저온소결 세라믹으로 실링하는 칩 스케일 패키지 구조체 제조방법을 단계별로 개략적으로 보여주는 단면도,4A to 4G are cross-sectional views schematically illustrating a method of manufacturing a chip scale package structure for sealing with low temperature sintered ceramic at a wafer level according to the present invention;
도 5는 라미네이터 필름이 패턴된 상태의 저면을 나타내는 전자현미경 사진, 5 is an electron micrograph showing the bottom surface of the laminator film patterned state,
도 6은 도 5에서 솔더 범프를 채우고 리플로우시킨 후 필름이 제거된 상태의 저면을 나타내는 전자현미경 사진, 6 is an electron micrograph showing the bottom surface of the film is removed after filling and reflowing the solder bump in Figure 5,
도 7은 캐핑 웨이퍼의 평면을 나타내는 전자현미경 사진.7 is an electron micrograph showing a plane of a capping wafer.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on main parts of drawing
100: 소자 웨이퍼 102: 제1전극100: device wafer 102: first electrode
104: MEMS 소자 120: 솔더 범프104: MEMS device 120: solder bump
124: 밀봉실링부 126: 제2전극124: sealing seal 126: second electrode
140: 저온소결 세라믹 기판 142: 비아홀140: low-temperature sintered ceramic substrate 142: via hole
146: 외부전극 148: 수동소자146: external electrode 148: passive element
150: BGA 160: 능동소자150: BGA 160: active element
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| KR100791061B1 (en) | 2007-03-21 | 2008-01-04 | 이명준 | Electric magnet heater and warm mat by telectric magnet |
| US9764946B2 (en) | 2013-10-24 | 2017-09-19 | Analog Devices, Inc. | MEMs device with outgassing shield |
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| JPH08250615A (en) * | 1995-03-13 | 1996-09-27 | Sumitomo Kinzoku Electro Device:Kk | Ceramic package for semiconductor chip |
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| KR19990079130A (en) * | 1998-04-01 | 1999-11-05 | 김영환 | Ceramic package |
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| JPH0878476A (en) * | 1994-09-08 | 1996-03-22 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPH08250615A (en) * | 1995-03-13 | 1996-09-27 | Sumitomo Kinzoku Electro Device:Kk | Ceramic package for semiconductor chip |
| JPH09232904A (en) * | 1996-02-28 | 1997-09-05 | Oki Electric Ind Co Ltd | Ceramic package for saw filter |
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