JPH0878476A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH0878476A
JPH0878476A JP6214388A JP21438894A JPH0878476A JP H0878476 A JPH0878476 A JP H0878476A JP 6214388 A JP6214388 A JP 6214388A JP 21438894 A JP21438894 A JP 21438894A JP H0878476 A JPH0878476 A JP H0878476A
Authority
JP
Japan
Prior art keywords
bump
integrated circuit
circuit device
semiconductor element
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6214388A
Other languages
Japanese (ja)
Inventor
Tetsuji Obara
哲治 小原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi ULSI Engineering Corp
Hitachi Ltd
Original Assignee
Hitachi ULSI Engineering Corp
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi ULSI Engineering Corp, Hitachi Ltd filed Critical Hitachi ULSI Engineering Corp
Priority to JP6214388A priority Critical patent/JPH0878476A/en
Publication of JPH0878476A publication Critical patent/JPH0878476A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To prolong the service life of a bump at an electrode connecting part of a semiconductor element. CONSTITUTION: The semiconductor integrated circuit device comprises a board 3 made of a ceramic material, e.g. mullite, and mounting a semiconductor element 2 through a solder bump 1, for example, butter members 4 disposed at an electrode connecting part 2a on the semiconductor element 2 side and at an electrode connecting part 3a on the board 3 side and connected with the bumps 1, and a cap member 7 composed of a ceramic having high thermal conductivity, e.g. aluminum nitride, and connected through a sealing solder 5 and a metallize layer 6 with the major surface of the board 3. The semiconductor element 2 is face down bonded to the board 3 and the butter member 4 is formed into dish shape having an inclining part 4a on the outer periphery. The butter member 4 is connected, at the bottom part and the inner circumferential face thereof, with the bump 1.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体集積回路装置に
関し、特に、はんだバンプを介して半導体素子を基板に
フェイスダウンボンディングする半導体集積回路装置に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device for face down bonding a semiconductor element to a substrate via solder bumps.

【0002】[0002]

【従来の技術】以下に説明する技術は、本発明を研究、
完成するに際し、本発明者によって検討されたものであ
り、その概要は次のとおりである。
2. Description of the Related Art The techniques described below are for studying the present invention,
The present invention was studied by the present inventors upon completion, and its outline is as follows.

【0003】半導体素子を該半導体素子搭載用の基板に
フェイスダウンボンディングする半導体集積回路装置に
おいては、前記半導体素子の電極接続部にはんだなどに
よるバンプが用いられるのが一般的である。
In a semiconductor integrated circuit device in which a semiconductor element is face-down bonded to a substrate for mounting the semiconductor element, bumps made of solder or the like are generally used for electrode connecting portions of the semiconductor element.

【0004】また、前記フェイスダウンボンディングに
よる接続方法は、CCB(Controlled Collapse Bondin
g)バンプ接続として知られている。
The connection method by the face-down bonding is based on CCB (Controlled Collapse Bondin).
g) Known as bump connection.

【0005】なお、半導体素子を基板に接続するバンプ
については、例えば、特開昭59−35439号公報に
開示されている。
A bump for connecting a semiconductor element to a substrate is disclosed in, for example, Japanese Patent Laid-Open No. 59-35439.

【0006】[0006]

【発明が解決しようとする課題】ところが、前記した技
術によるCCBバンプ接続においては、温度サイクルや
パワーサイクルなどの寿命評価時に、はんだなどによる
CCBバンプの電極端部に応力が掛かり、CCBバンプ
が損傷する。その結果、CCBバンプの寿命が短くなる
という問題が発生する。
However, in the CCB bump connection by the above-mentioned technique, stress is applied to the electrode end of the CCB bump due to solder or the like at the time of life evaluation such as temperature cycle or power cycle, and the CCB bump is damaged. To do. As a result, there arises a problem that the life of the CCB bump is shortened.

【0007】また、CCBバンプには、半導体集積回路
装置を使用している時に発生する機械的振動によっても
応力が掛かるため、これによって、CCBバンプを損傷
する場合もある。
Further, the CCB bumps are also stressed by mechanical vibrations generated when the semiconductor integrated circuit device is used, which may damage the CCB bumps.

【0008】また、CCBバンプは、その大きさにもば
らつきがあるため、個々のバンプ形状に差があり、結果
的に、CCBバンプの寿命もばらつくという問題も発生
する。
Since the CCB bumps also vary in size, there is a difference in the shape of individual bumps, and as a result, the life of the CCB bumps also varies.

【0009】そこで、本発明の目的は、半導体素子の電
極接続部におけるバンプの長寿命化を図る半導体集積回
路装置を提供することにある。
Therefore, an object of the present invention is to provide a semiconductor integrated circuit device for extending the life of the bumps in the electrode connecting portion of the semiconductor element.

【0010】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

【0011】[0011]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。
Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

【0012】すなわち、半導体素子側の電極接続部、も
しくはバンプを介して半導体素子を接続する基板側の電
極接続部、あるいはその両方にバンプと接続する緩衝部
材が設置されているものである。
That is, a cushioning member for connecting to the bump is provided on the electrode connecting portion on the semiconductor element side, the electrode connecting portion on the substrate side for connecting the semiconductor element via the bump, or both.

【0013】また、前記緩衝部材が外周に傾斜部を有す
る皿状であり、該緩衝部材の底部および内周面と、前記
バンプとが接続されているものである。
Further, the cushioning member is dish-shaped having an inclined portion on the outer periphery, and the bottom portion and the inner peripheral surface of the cushioning member are connected to the bumps.

【0014】さらに、前記緩衝部材が導電性ゴムまたは
薄膜化された金属板によって形成されているものであ
る。
Further, the buffer member is formed of conductive rubber or a thin metal plate.

【0015】また、前記緩衝部材が、半導体素子のバン
プ接続面角部または該バンプ接続面角部を含むバンプ接
続面外周部に相当する位置に設置されているものであ
る。
Further, the buffer member is installed at a position corresponding to a corner portion of the bump connecting surface of the semiconductor element or an outer peripheral portion of the bump connecting surface including the corner portion of the bump connecting surface.

【0016】[0016]

【作用】上記した手段によれば、半導体素子側の電極接
続部、もしくはバンプを介して半導体素子を接続する基
板側の電極接続部、あるいはその両方にバンプと接続す
る緩衝部材が設置されていることにより、バンプの端部
に応力が掛かっても前記緩衝部材がバンプの変形に追従
して変形する。
According to the above-mentioned means, the buffer member for connecting to the bump is provided on the electrode connecting portion on the semiconductor element side, the electrode connecting portion on the substrate side for connecting the semiconductor element via the bump, or both. As a result, even if stress is applied to the ends of the bumps, the buffer member deforms following the deformation of the bumps.

【0017】これにより、バンプに掛かる応力が低減さ
れ、バンプの長寿命化を図ることができる。
As a result, the stress applied to the bumps is reduced and the life of the bumps can be extended.

【0018】また、前記緩衝部材が外周に傾斜部を有す
る皿状であり、該緩衝部材の底部および内周面と、前記
バンプとが接続され、さらに、前記緩衝部材が導電性ゴ
ムまたは薄膜化された金属板によって形成されることに
より、前記緩衝部材とバンプとの接続性を向上すること
ができる。
Further, the cushioning member is in the shape of a dish having an inclined portion on the outer periphery, the bottom portion and the inner peripheral surface of the cushioning member are connected to the bumps, and the cushioning member is made of a conductive rubber or a thin film. Since it is formed of the formed metal plate, the connectivity between the buffer member and the bump can be improved.

【0019】これにより、バンプが熱などの影響を受け
て変形した時の緩衝部材の追従性も向上することができ
る。
As a result, the followability of the cushioning member when the bump is deformed under the influence of heat can be improved.

【0020】なお、前記緩衝部材が、半導体素子のバン
プ接続面角部または前記バンプ接続面角部を含むバンプ
接続面外周部に相当する位置に設置されることにより、
応力が掛かりやすい箇所だけのバンプに対して前記緩衝
部材を設置することができる。
The cushioning member is installed at a position corresponding to a corner portion of the bump connecting surface of the semiconductor element or an outer peripheral portion of the bump connecting surface including the corner portion of the bump connecting surface,
The cushioning member can be installed on the bumps only at places where stress is easily applied.

【0021】その結果、前記緩衝部材の設置数を削減す
ることができ、また、半導体集積回路装置の製造コスト
を低減することができる。
As a result, the number of the buffer members to be installed can be reduced and the manufacturing cost of the semiconductor integrated circuit device can be reduced.

【0022】[0022]

【実施例】以下、本発明の実施例を図面に基づいて詳細
に説明する。
Embodiments of the present invention will now be described in detail with reference to the drawings.

【0023】図1は本発明による半導体集積回路装置の
構造の一実施例を示す断面図、図2は本発明による半導
体集積回路装置に搭載される半導体素子の電極接続部に
用いられる緩衝部材の構造の一実施例を示す拡大部分断
面図、図3は本発明による半導体集積回路装置に搭載さ
れる半導体素子のバンプ接続面の構造の一実施例を示す
平面図である。
FIG. 1 is a sectional view showing an embodiment of the structure of a semiconductor integrated circuit device according to the present invention, and FIG. 2 shows a buffer member used for an electrode connecting portion of a semiconductor element mounted on the semiconductor integrated circuit device according to the present invention. FIG. 3 is an enlarged partial sectional view showing an example of the structure, and FIG. 3 is a plan view showing an example of the structure of the bump connection surface of the semiconductor element mounted on the semiconductor integrated circuit device according to the present invention.

【0024】まず、図1および図2を用いて、本実施例
の半導体集積回路装置の構成について説明すると、はん
だなどによるバンプ1を介して半導体素子2を搭載しか
つムライトなどのセラミック材料からなる基板3と、半
導体素子2側の電極接続部2aおよび基板3側の電極接
続部3aに設置されかつバンプ1に接続する緩衝部材4
と、窒化アルミニウム(AlN)などの高熱伝導性セラ
ミックからなりかつ封止用はんだ5およびメタライズ層
6を介して基板3の主面に接続されるキャップ部材7と
から構成されている。
First, the structure of the semiconductor integrated circuit device of this embodiment will be described with reference to FIGS. 1 and 2. The semiconductor element 2 is mounted via the bump 1 made of solder or the like and is made of a ceramic material such as mullite. The substrate 3, the electrode connecting portion 2a on the semiconductor element 2 side, and the buffer member 4 installed on the electrode connecting portion 3a on the substrate 3 side and connected to the bump 1
And a cap member 7 made of high thermal conductivity ceramic such as aluminum nitride (AlN) and connected to the main surface of the substrate 3 via the sealing solder 5 and the metallized layer 6.

【0025】つまり、前記半導体集積回路装置は、半導
体素子2が基板3に対してバンプ1を用いてフェイスダ
ウンボンディング、すなわち、CCBバンプ接続された
ものである。
That is, in the semiconductor integrated circuit device, the semiconductor element 2 is face down bonded to the substrate 3 using the bumps 1, that is, CCB bump connection is performed.

【0026】ここで、本実施例の緩衝部材4は、薄膜構
造でかつその外周に傾斜部4aを有した皿状を形成する
ものであり、緩衝部材4の底部4bおよび内周面4c
と、バンプ1とが接続されている。
Here, the cushioning member 4 of this embodiment has a thin film structure and forms a dish having an inclined portion 4a on the outer periphery thereof, and the bottom portion 4b and the inner peripheral surface 4c of the cushioning member 4 are formed.
And the bump 1 are connected.

【0027】なお、緩衝部材4は半導体素子2側の電極
接続部2aか、あるいは基板3側の電極接続部3aのど
ちらか一方にだけ設置されるものであってもよい。
The buffer member 4 may be installed only on one of the electrode connecting portion 2a on the semiconductor element 2 side and the electrode connecting portion 3a on the substrate 3 side.

【0028】また、緩衝部材4は導電性の部材であり、
例えば、導電性ゴム、あるいは銅製の薄膜化された金属
板などによって形成されている。
The cushioning member 4 is a conductive member,
For example, it is formed of a conductive rubber or a thin metal plate made of copper.

【0029】さらに、半導体素子2および基板3の表面
には、Cr、Cu、Auなどの合金からなる下地電極で
ある素子上下地電極2bおよび基板上下地電極3bがそ
れぞれ設けられており、そこへ緩衝部材4が設置されて
いる。
Further, on the surfaces of the semiconductor element 2 and the substrate 3, there are provided an on-element underlying electrode 2b and an on-substrate underlying electrode 3b, which are underlying electrodes made of an alloy of Cr, Cu, Au, etc., respectively. The cushioning member 4 is installed.

【0030】ここで、緩衝部材4が導電性ゴムの場合、
前記導電性ゴムをスクリーン印刷方式などを利用して設
置し、また、銅製などの薄膜化された金属板の場合、前
記金属板をプレスなどによって設置する。
Here, when the buffer member 4 is a conductive rubber,
The conductive rubber is installed using a screen printing method or the like, and in the case of a thin metal plate made of copper or the like, the metal plate is installed by a press or the like.

【0031】また、緩衝部材4は半導体素子2上の全て
の電極接続部2aに対して設置してもよいが、図3に示
すように、緩衝部材4を半導体素子2のバンプ接続面角
部2cまたはバンプ接続面角部2cを含むバンプ接続面
外周部2dに相当する位置にだけ設置してもよい。
Although the cushioning member 4 may be installed on all the electrode connecting portions 2a on the semiconductor element 2, as shown in FIG. 2c or the bump connection surface peripheral portion 2d including the bump connection surface corner portion 2c may be installed only at a position corresponding to the bump connection surface outer peripheral portion 2d.

【0032】次に、本実施例による半導体集積回路装置
の作用および効果について説明する。
Next, the operation and effect of the semiconductor integrated circuit device according to this embodiment will be described.

【0033】まず、半導体素子2側の電極接続部2a、
もしくはCCBバンプであるバンプ1を介して半導体素
子2を接続する基板3側の電極接続部3a、あるいはそ
の両方にバンプ1と接続する緩衝部材4が設置されてい
ることにより、温度サイクルやパワーサイクルなどの評
価時に、バンプ1の端部に熱などによる応力が掛かり、
変形バンプ1aとなっても、緩衝部材4がバンプ1の変
形に追従して変形緩衝部材4dとなって変形する。
First, the electrode connecting portion 2a on the semiconductor element 2 side,
Alternatively, the buffer member 4 for connecting to the bump 1 is installed on the electrode connecting portion 3a on the side of the substrate 3 for connecting the semiconductor element 2 via the bump 1 which is a CCB bump, or both of them, so that the temperature cycle and the power cycle can be improved. When evaluating, etc., stress due to heat is applied to the end of the bump 1,
Even when the bumps 1a are deformed, the buffer member 4 follows the deformation of the bumps 1 and deforms as the deformation buffer member 4d.

【0034】これにより、バンプ1の端部に掛かる応力
が低減され、該バンプ1の長寿命化を図ることができる
とともに、評価時などのデータの信頼性を向上させるこ
とができる。
As a result, the stress applied to the end portion of the bump 1 can be reduced, the life of the bump 1 can be extended, and the reliability of data at the time of evaluation can be improved.

【0035】また、半導体集積回路装置を使用している
時に、バンプ1に機械的振動によって応力が掛かって
も、該応力が低減されることにより、バンプ1の長寿命
化を図ることができる。
Further, when the semiconductor integrated circuit device is used, even if stress is applied to the bump 1 due to mechanical vibration, the stress is reduced, so that the life of the bump 1 can be extended.

【0036】さらに、緩衝部材4が外周に傾斜部4aを
有する皿状を形成し、該緩衝部材4の底部4bおよび内
周面4cと、バンプ1とが接続され、さらに、緩衝部材
4が導電性ゴムまたは薄膜化された金属板によって形成
されることにより、緩衝部材4とバンプ1との接続性を
向上することができる。
Further, the cushioning member 4 is formed in a dish shape having an inclined portion 4a on the outer periphery, the bottom 4b and the inner peripheral surface 4c of the cushioning member 4 are connected to the bumps 1, and the cushioning member 4 is electrically conductive. The connection between the cushioning member 4 and the bump 1 can be improved by forming the elastic member or the thin metal plate.

【0037】つまり、バンプ1に応力が掛かることによ
って、該バンプ1が変形した時に、緩衝部材4の傾斜部
4aがバンプ1に追従することができる。
That is, when the bump 1 is deformed by the stress applied to the bump 1, the inclined portion 4a of the buffer member 4 can follow the bump 1.

【0038】これにより、バンプ1が変形した時の緩衝
部材4の追従性も向上することができ、その結果、前記
同様にバンプ1の長寿命化を図ることができる。
As a result, the followability of the cushioning member 4 when the bump 1 is deformed can be improved, and as a result, the life of the bump 1 can be extended similarly to the above.

【0039】また、半導体素子2の中心付近から離れた
位置のバンプ1ほど、半導体素子2と基板3との間の熱
に対する収縮率の差が大きいことにより、バンプ1に掛
かる応力も大きい。
Further, as the bump 1 located farther from the vicinity of the center of the semiconductor element 2 has a larger difference in contraction rate with respect to heat between the semiconductor element 2 and the substrate 3, the stress applied to the bump 1 is also larger.

【0040】したがって、緩衝部材4が、半導体素子2
の中心付近から離れた位置、つまり、半導体素子2のバ
ンプ接続面角部2cまたはバンプ接続面角部2cを含む
バンプ接続面外周部2dに相当する位置のバンプ1に対
してだけ接続されることにより、熱による応力が掛かり
やすい箇所だけのバンプ1に対して緩衝部材4を設置す
ることができる。
Therefore, the buffer member 4 is used as the semiconductor element 2.
Connected only to the bump 1 at a position distant from the vicinity of the center, that is, at a position corresponding to the bump connection surface corner portion 2c of the semiconductor element 2 or the bump connection surface outer peripheral portion 2d including the bump connection surface corner portion 2c. Thus, the cushioning member 4 can be installed on the bumps 1 only at locations where heat stress is likely to be applied.

【0041】その結果、緩衝部材4の設置数を削減する
ことができ、また、半導体集積回路装置の製造コストも
低減することができる。
As a result, the number of buffer members 4 to be installed can be reduced, and the manufacturing cost of the semiconductor integrated circuit device can be reduced.

【0042】以上、本発明者によってなされた発明を実
施例に基づき具体的に説明したが、本発明は前記実施例
に限定されるものではなく、その要旨を逸脱しない範囲
で種々変更可能であることは言うまでもない。
The invention made by the inventor of the present invention has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

【0043】例えば、前記実施例で説明した半導体集積
回路装置においては、半導体素子側の電極接続部(また
は基板側の電極接続部)に設置される緩衝部材が、外周
に傾斜部を有する皿状を形成するものであったが、図4
の本発明の他の実施例である半導体集積回路装置に搭載
される半導体素子の電極接続部に用いられる緩衝部材の
拡大部分断面図に示すように、緩衝部材8は薄膜構造の
円板状を形成するものであってもよい。
For example, in the semiconductor integrated circuit device described in the above embodiment, the cushioning member installed in the electrode connecting portion on the semiconductor element side (or the electrode connecting portion on the substrate side) has a dish shape having an inclined portion on the outer periphery. Was formed, but FIG.
As shown in the enlarged partial sectional view of the cushioning member used for the electrode connecting portion of the semiconductor element mounted on the semiconductor integrated circuit device according to another embodiment of the present invention, the cushioning member 8 has a disk-like thin film structure. It may be formed.

【0044】つまり、薄膜構造による円板状の緩衝部材
8が設置されたことによって、バンプ1の端部に熱など
による応力が掛かり、変形バンプ1aとなっても、緩衝
部材8がバンプ1の変形に追従して変形緩衝部材8aと
なって変形する。
In other words, since the disk-shaped cushioning member 8 having the thin film structure is installed, stress is applied to the ends of the bump 1 due to heat or the like, and even if the deformed bump 1a is formed, the cushioning member 8 will not be affected by the bump 1. Following the deformation, the deformation buffer member 8a is deformed.

【0045】これにより、前記実施例と同様に、バンプ
1の端部に掛かる応力が低減され、該バンプ1の長寿命
化を図ることができるとともに、評価時などのデータの
信頼性を向上させることができる。
As a result, similarly to the above-mentioned embodiment, the stress applied to the end portion of the bump 1 can be reduced, the life of the bump 1 can be extended, and the reliability of data at the time of evaluation can be improved. be able to.

【0046】ここで、緩衝部材8は前記実施例と同様
に、導電性ゴムであっても、また、銅などからなる薄膜
化された金属板などでもよい。
Here, the cushioning member 8 may be a conductive rubber or a thin metal plate made of copper or the like, as in the above embodiment.

【0047】さらに、緩衝部材8は半導体素子2側の電
極接続部2aに設置されても、また、基板3側の電極接
続部3aに設置されても、あるいはその両者に設置され
てもよい。
Further, the buffer member 8 may be installed on the electrode connecting portion 2a on the semiconductor element 2 side, on the electrode connecting portion 3a on the substrate 3 side, or on both of them.

【0048】また、図1に示した緩衝部材4を半導体素
子2側の電極接続部2aに設置し、図4に示した緩衝部
材8を基板3側の電極接続部3aに設置してもよく、あ
るいはその反対の組み合わせであってもよい。
The buffer member 4 shown in FIG. 1 may be installed in the electrode connecting portion 2a on the semiconductor element 2 side, and the buffer member 8 shown in FIG. 4 may be installed in the electrode connecting portion 3a on the substrate 3 side. , Or vice versa.

【0049】[0049]

【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下のとおりである。
Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

【0050】(1).半導体素子側の電極接続部、もし
くはバンプを介して半導体素子を接続する基板側の電極
接続部、あるいはその両方にバンプと接続する緩衝部材
が設置されていることにより、温度サイクルやパワーサ
イクルなどの評価時に、バンプの端部に熱などによる応
力が掛かっても緩衝部材がバンプの変形に追従して変形
する。
(1). By providing a buffer member for connecting to the bump on the electrode connecting portion on the semiconductor element side, or on the substrate side connecting the semiconductor element through the bump, or both, temperature cycle, power cycle, etc. At the time of evaluation, the buffer member is deformed following the deformation of the bumps even if stress is applied to the ends of the bumps due to heat or the like.

【0051】これにより、バンプに掛かる応力が低減さ
れ、該バンプの長寿命化を図ることができるとともに、
評価時などのデータの信頼性を向上させることができ
る。
As a result, the stress applied to the bumps is reduced, the life of the bumps can be extended, and
The reliability of data at the time of evaluation can be improved.

【0052】(2).半導体集積回路装置を使用してい
る時に、バンプに機械的振動によって応力が掛かって
も、該応力が低減されることにより、バンプの長寿命化
を図ることができる。
(2). When the semiconductor integrated circuit device is used, even if stress is applied to the bump due to mechanical vibration, the stress is reduced, so that the life of the bump can be extended.

【0053】(3).前記緩衝部材が外周に傾斜部を有
する皿状を形成し、該緩衝部材の底部および内周面と、
前記バンプとが接続され、さらに、緩衝部材が導電性ゴ
ムまたは薄膜化された金属板によって形成されることに
より、緩衝部材とバンプとの接続性を向上することがで
きる。
(3). The cushioning member forms a dish having an inclined portion on the outer periphery, and a bottom portion and an inner peripheral surface of the cushioning member,
Since the bumps are connected to each other and the cushioning member is formed of conductive rubber or a thin metal plate, the connectivity between the cushioning member and the bumps can be improved.

【0054】したがって、バンプに応力が掛かり、該バ
ンプが変形した時に、緩衝部材の傾斜部がバンプに追従
することができる。これにより、バンプが変形した時の
緩衝部材の追従性も向上させることができ、その結果、
前記同様にバンプの長寿命化を図ることができる。
Therefore, when a stress is applied to the bump and the bump is deformed, the inclined portion of the cushioning member can follow the bump. This can improve the followability of the cushioning member when the bump is deformed, and as a result,
Similar to the above, the life of the bump can be extended.

【0055】(4).前記緩衝部材を薄膜化された円板
状とすることにより、前記(1)と同様の効果を得るこ
とができる。
(4). By forming the buffer member into a thin disk shape, the same effect as the above (1) can be obtained.

【0056】(5).前記緩衝部材が、半導体素子の中
心付近から離れた位置、つまり、半導体素子のバンプ接
続面角部または該バンプ接続面角部を含むバンプ接続面
外周部に相当する位置にだけ設置されることにより、熱
による応力が掛かりやすい箇所だけのバンプに対して緩
衝部材を設置することができる。
(5). By providing the buffer member only at a position away from the vicinity of the center of the semiconductor element, that is, at a position corresponding to a bump connection surface corner portion of the semiconductor element or a bump connection surface outer peripheral portion including the bump connection surface corner portion. It is possible to install the cushioning member on the bumps only at locations where heat stress is likely to be applied.

【0057】その結果、前記緩衝部材の設置数を削減す
ることができ、また、半導体集積回路装置の製造コスト
も低減することができる。
As a result, the number of the buffer members to be installed can be reduced, and the manufacturing cost of the semiconductor integrated circuit device can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による半導体集積回路装置の構造の一実
施例を示す断面図である。
FIG. 1 is a sectional view showing an embodiment of the structure of a semiconductor integrated circuit device according to the present invention.

【図2】本発明による半導体集積回路装置に搭載される
半導体素子の電極接続部に用いられる緩衝部材の構造の
一実施例を示す拡大部分断面図である。
FIG. 2 is an enlarged partial cross-sectional view showing an embodiment of the structure of a buffer member used for an electrode connecting portion of a semiconductor element mounted on a semiconductor integrated circuit device according to the present invention.

【図3】本発明による半導体集積回路装置に搭載される
半導体素子のバンプ接続面の構造の一実施例を示す平面
図である。
FIG. 3 is a plan view showing an example of a structure of a bump connection surface of a semiconductor element mounted on a semiconductor integrated circuit device according to the present invention.

【図4】本発明の他の実施例である半導体集積回路装置
に搭載される半導体素子の電極接続部に用いられる緩衝
部材の構造の一例を示す拡大部分断面図である。
FIG. 4 is an enlarged partial cross-sectional view showing an example of a structure of a buffer member used for an electrode connecting portion of a semiconductor element mounted in a semiconductor integrated circuit device which is another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 バンプ 1a 変形バンプ 2 半導体素子 2a 電極接続部 2b 素子上下地電極 2c バンプ接続面角部 2d バンプ接続面外周部 3 基板 3a 電極接続部 3b 基板上下地電極 4 緩衝部材 4a 傾斜部 4b 底部 4c 内周面 4d 変形緩衝部材 5 封止用はんだ 6 メタライズ層 7 キャップ部材 8 緩衝部材 8a 変形緩衝部材 DESCRIPTION OF SYMBOLS 1 bump 1a deformed bump 2 semiconductor element 2a electrode connecting portion 2b element upper base electrode 2c bump connecting surface corner portion 2d bump connecting surface outer peripheral portion 3 substrate 3a electrode connecting portion 3b substrate lower electrode 4 buffer member 4a inclined portion 4b bottom portion 4c Circumferential surface 4d Deformation buffer member 5 Sealing solder 6 Metallization layer 7 Cap member 8 Buffer member 8a Deformation buffer member

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 バンプを介して半導体素子を基板に接続
する半導体集積回路装置であって、前記半導体素子側の
電極接続部、もしくは前記基板側の電極接続部、あるい
はその両方に前記バンプと接続する緩衝部材が設置され
ていることを特徴とする半導体集積回路装置。
1. A semiconductor integrated circuit device for connecting a semiconductor element to a substrate via a bump, wherein the bump is connected to an electrode connection portion on the semiconductor element side, an electrode connection portion on the substrate side, or both. A semiconductor integrated circuit device, in which a buffer member is installed.
【請求項2】 請求項1記載の半導体集積回路装置であ
って、前記緩衝部材が外周に傾斜部を有する皿状であ
り、前記緩衝部材の底部および内周面と、前記バンプと
が接続されていることを特徴とする半導体集積回路装
置。
2. The semiconductor integrated circuit device according to claim 1, wherein the buffer member has a dish shape having an inclined portion on an outer periphery, and a bottom portion and an inner peripheral surface of the buffer member are connected to the bump. And a semiconductor integrated circuit device.
【請求項3】 請求項1記載の半導体集積回路装置であ
って、前記緩衝部材が円板状であることを特徴とする半
導体集積回路装置。
3. The semiconductor integrated circuit device according to claim 1, wherein the buffer member has a disk shape.
【請求項4】 請求項1,2または3記載の半導体集積
回路装置であって、前記緩衝部材が導電性ゴムによって
形成されていることを特徴とする半導体集積回路装置。
4. The semiconductor integrated circuit device according to claim 1, wherein the buffer member is made of conductive rubber.
【請求項5】 請求項1,2または3記載の半導体集積
回路装置であって、前記緩衝部材が薄膜化された金属板
によって形成されていることを特徴とする半導体集積回
路装置。
5. The semiconductor integrated circuit device according to claim 1, wherein the buffer member is formed of a thin metal plate.
【請求項6】 請求項1,2,3,4または5記載の半
導体集積回路装置であって、前記緩衝部材が、前記半導
体素子のバンプ接続面角部または該バンプ接続面角部を
含むバンプ接続面外周部に相当する位置に設置されてい
ることを特徴とする半導体集積回路装置。
6. The semiconductor integrated circuit device according to claim 1, 2, 3, 4, or 5, wherein the buffer member has a bump connection surface corner portion of the semiconductor element or a bump including the bump connection surface corner portion. A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is installed at a position corresponding to an outer peripheral portion of a connection surface.
JP6214388A 1994-09-08 1994-09-08 Semiconductor integrated circuit device Pending JPH0878476A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6214388A JPH0878476A (en) 1994-09-08 1994-09-08 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6214388A JPH0878476A (en) 1994-09-08 1994-09-08 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH0878476A true JPH0878476A (en) 1996-03-22

Family

ID=16654970

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6214388A Pending JPH0878476A (en) 1994-09-08 1994-09-08 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0878476A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002043364A (en) * 2000-07-21 2002-02-08 Matsushita Electric Ind Co Ltd Flip chip mounting body and mounting method
KR100519750B1 (en) * 2001-05-10 2005-10-07 삼성전자주식회사 Chip scale packaging structure sealed with low temperature Co-fired ceramic and the method thereof
JP2012142436A (en) * 2010-12-28 2012-07-26 Toshiba Corp Mounting structure and mounting method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002043364A (en) * 2000-07-21 2002-02-08 Matsushita Electric Ind Co Ltd Flip chip mounting body and mounting method
US6750132B2 (en) 2000-07-21 2004-06-15 Matsushita Electric Industrial Co., Ltd. Flip chip package, circuit board thereof and packaging method thereof
US7034389B2 (en) 2000-07-21 2006-04-25 Matsushita Electric Industrial Co., Ltd. Flip chip package, circuit board thereof and packaging method thereof
KR100519750B1 (en) * 2001-05-10 2005-10-07 삼성전자주식회사 Chip scale packaging structure sealed with low temperature Co-fired ceramic and the method thereof
JP2012142436A (en) * 2010-12-28 2012-07-26 Toshiba Corp Mounting structure and mounting method

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