JPH08250503A - Etching method - Google Patents

Abstract

PURPOSE: To obtain a highly reliable device having a high dielectric constant thin film capacitor at high yield by selectively etching a noble metallic thin film used as an electrode or a wiring layer by using a specified mask material by using etchant containing at least halogen only, salt halide and inducing solvent. CONSTITUTION: After performing RF sputtering for a Pt film 242, a dielectric film 243 and a W film 244 continuously, a photoresist film 51 is formed by photolithography and an upper electrode of the W film 244 is formed by RIE method wherein CF4 is used. Then, a dielectric film 243 is formed of H2 O2 , NH4 OH, EDTA mixture water solution by using the upper electrode as a mask layer and then a Pt film 242 which becomes a lower electrode is etched by 60 deg.C mixture solution of iodine, cetylpyridinium iodide and benzene and a capacitor cell is readily formed on an n<+> source region 231. A noble metallic thin film can be used as a wiring metal by adopting the noble metal etching method and high integration and rapid operation of an integrated circuit become possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fine processing technique for a noble metal thin film used as a surface wiring metal or an electrode material of a semiconductor device.

[0002]

2. Description of the Related Art The progress toward higher integration and higher performance of semiconductor integrated circuits such as LSI, VLSI, and ULSI is rapid, and for example, the development of a typical MOS / dynamic RAM (DRAM) as a volatile memory is 3 It is expected that the same trend will continue in the future, supported by the ever-increasing needs, as the integration continues to be four times higher in a year. A semiconductor memory device represented by a DRAM has been miniaturized with each generation, and has played a role as a so-called "process driver". Various technological innovations have been made in the background of the high integration of such LSIs, and the semiconductor device cannot be further developed without such progress. Regarding the cell structure of a semiconductor memory device, the charge storage layer (capacitor part) has been three-dimensionalized from a planar type to a stack type or a trench type in the generation from 1 MbDRAM to 4 MbDRAM. That is, up to 1 Mb DRAM, even a thin silicon oxide film (SiO ₂ ) of about 10 nm can be used as a capacitor insulating film with sufficient reliability, and a planar structure can be maintained. In a 4 Mb DRAM, the capacitor area cannot be secured with a planar structure due to the reduction of the cell size, and a trench type in which a capacitor is buried in the hole or a stack type in which a capacitor having a two-layer structure is stacked on a transistor is roughly divided into three types. The dimensional capacitor structure had to be adopted. But 256
In the MbDRAM or the 1GbDRAM, even if these structures are used, it is extremely difficult to use the SiO ₂ film as the capacitor insulating film. The situation was the same even if the Si ₃ N ₄ film and the Al ₂ O ₃ film which were conventionally used other than the SiO ₂ film had a dielectric constant of about 10 at most. On the other hand, SrTiO that is a perovskite type oxide
₃ , BaTiO ₃ , PbTiO ₃ , PbZrO _{3 and the} like have a single composition as well as a mutual solid-liquid composition of 100 or more and 10 or more.
It is known to have a dielectric constant as high as 00, and is widely used in the field of ceramic capacitors, which is a field different from semiconductor devices. Thinning of these materials is extremely effective for miniaturization of the above-mentioned thin film capacitor, and research has been conducted for a long time in fields other than semiconductor devices, and relatively good characteristics have been obtained.
Only a few attempts have been made in the field of semiconductor devices such as I and ULSI that require fine processing. This has a problem with the film quality of these perovskite type oxides, but the other main cause is a problem in processing technology in which the precious metal thin film used as an electrode cannot be finely processed.

Further, since the noble metal thin film has a smaller specific resistance than Al or Al alloy currently used as the main wiring metal of an integrated circuit and can shorten the propagation delay time, it becomes more important as the integration density becomes higher. Further, in order to improve the contact resistance between Al and silicon, P is added at the interface between Al and Si.
The precious metal electrode material for forming the tSi ₂ layer becomes important.

That is, in the field of semiconductor devices such as LSIs, sub-micron order ultrafine processing is realized by selective etching using various mask materials combined with so-called photolithography technology, and 1 GbDRA
It is decided that M etc. will appear, but 1 GbDR
The processing technology such as etching technology of a noble metal thin film, which is expected for a semiconductor device having a high integration density of AM or more, has not yet been developed.

[0005]

In the general semiconductor process, the photolithography technique is specifically carried out according to the following process. That is, first, a photoresist film (hereinafter abbreviated as resist) which is a photosensitive composition is formed on a substrate such as a silicon single crystal wafer by, for example, a spin coating method. Next, this photosensitive film is exposed to ultraviolet rays, electron beams, X-rays, etc., and then subjected to processing such as development and rinsing to form a resist pattern. Then, using the resist pattern film as an etching resistant mask, the exposed substrate surface is subjected to etching treatment to open lines and windows having a minute width, and a desired pattern is transferred onto the substrate. In the coating process of the photosensitive composition, the spin coating method is mainly used because it can be uniformly coated on the entire surface of the substrate with good workability. Then, using this resist as a mask, the target thin film is finely processed by dry etching such as RIE or ECR ion etching, or other wet etching.

However, the above-mentioned SrTiO ₃
Since a high dielectric constant thin film such as, for example, usually requires an oxidizing atmosphere and a high temperature when producing a high dielectric constant thin film, all of them are noble metals such as platinum (Pt), palladium (Pd), gold (Au), or the like. It is generally formed on the lower electrode made of the oxide. Except for special cases, it is difficult to apply electrodes of such noble metal materials to various integrated circuits including storage elements, most of which are currently made by using a silicon substrate. The reason for this is that a reliable fine processing technique for these precious metals has not been established. That is, since noble metals such as platinum are chemically stable, etching with wet etching using well-known aqua regia etches both the photosensitive composition formed as the etching resistant film and the high dielectric constant film. Therefore, the electrode pattern cannot be formed. Another reason is that dry etching such as RIE is difficult because the vapor pressures of these noble metal halides are extremely low. After all, there is little knowledge of dry etchant and wet etchant etchants for these precious metals, and no known resist or other masking material suitable for these etchants is used, so reliability, yield, and fineness are improved. There was a problem that the processing technology was not developed.

For example, as a known manufacturing method using such a high dielectric thin film as a capacitor film, a lower electrode, a high dielectric constant thin film are formed along an element isolation insulating film, an interlayer insulating film formed on a bit line or a word line. , A method for forming a thin film capacitor by sequentially depositing upper electrodes (Patent Document 1)
4-80952) or a method of forming a thin film capacitor on a flattened insulating film (Japanese Patent Laid-Open No. 03-256).
358), and a method of forming a thin film capacitor by flattening the upper surface of the lower electrode (Japanese Patent Laid-Open No. 04-20656).
No. 9), etc., but all of them have a problem that when a noble metal or an oxide thereof is used for the lower electrode, it is difficult to manufacture it as an integrated circuit in consideration of reliability and yield.

In order to further increase the degree of integration in the future, it is necessary to have a three-dimensional structure in order to earn storage capacity even if thin film capacitors made of these high dielectric constant materials are used. At the same time, the fine processing technology of the lower electrode becomes an obstacle.

The present invention, Pt, provides selective etching technique of a noble metal thin film such as Pd, thereby SrTiO ₃
Aims at implementing various highly reliable semiconductor device such as a semiconductor memory device having a thin film capacitor using a high dielectric constant thin film typified by and BaTiO ₃ in high yield.

[0010]

In order to solve the above-mentioned problems, the features of the present invention are: a simple substance of halogen, a halogenated salt,
An etching solution containing at least an organic solvent is used to selectively etch a noble metal thin film used as an electrode, an electrode material or a wiring layer of a semiconductor device as illustrated in FIGS. 1 and 7 using a predetermined mask material. That is, the etching method can obtain a desired pattern of a noble metal thin film. That is, this noble metal thin film pattern means at least one electrode 242, 342, 344 of the charge storage capacitor portion of the semiconductor memory device as shown in FIGS.
Or a pattern made of an electrode material for ohmic contact or a metal material for wiring.

Preferably, the noble metal thin film is a platinum (Pt) thin film.

Preferably, the predetermined mask material is an unnecessary mask material for the etching solution selected from the group consisting of oxides, nitrides, carbides, inorganic thin films, metal thin films, and photosensitive compositions. That is. SiO ₂ as the oxide, Si ₃ N ₄ or TiN as the nitride,
The carbide is WC, TaC, SiC, etc., the inorganic thin film is polycrystalline silicon, etc., and the metal film is Al, Ti, N.
Typical examples are b, Mo, Ta and W.

[0013]

In order for the noble metal thin film etching method to be applicable to the semiconductor device manufacturing process, it is not enough that the etching solution dissolves the noble metal thin film.
In other words, in order to realize a fine pattern that is essential for a semiconductor device, compatibility with a photolithography process, specifically, a selection ratio with a mask material for etching, and a selection ratio with a substance of a base of the noble metal thin film are required. Is required to be high enough. The second requirement is whether or not a sufficiently high etching rate with high reproducibility and suitable for practical use can be obtained in the above-described high selection ratio state. The features of the present invention satisfy these needs.

Pt is soluble in aqua regia, which is oxidised (PtO) on the surface by nitric acid to make it easily soluble, and then dissolved by hydrochloric acid to give hexachloroplatinic acid (H ₂ [H ₂ [ This is to generate PtCl ₆ ]). In the case of the etching solution of the present invention, that is, when 1 mmol, 2 mmol and 5 mmol of Br ₂ having an oxidizing power are added to 10 g of benzene and 1 mmol of CPB, the etching rate of the Pt plate is 0. 8 nm / hr, 2.2 nm / hr and 3.5 nm / hr.

Further, benzene, as an organic solvent, dissolves various organic substances well. The higher the temperature during dissolution, the faster the dissolution rate. Br _{2 of} Pt plate: 5 mmol, CPB: 1
The etching rate with an etching solution consisting of mmol and benzene: 10 g is 0.6 nm / hr at room temperature (20 ° C.), 50
The speed changes by several orders of magnitude depending on the etching temperature: 3.5 nm / hr at 37 ° C, 37 nm / hr at 75 ° C, and 430 nm / hr at the boiling temperature (80 ° C) of the etching solution.

By using the etching solution of the present invention, an inorganic thin film of oxide, nitride, carbide, silicon or the like, a metal thin film or a mask material made of a photosensitive composition and an oxide film or a barrier metal film as an underlayer, etc. Does not dissolve, and only noble metals such as Pt, Au, Ag, and Pd can be easily dissolved. Therefore, the manufacturing method is simplified and the cost can be reduced.

As the organic solvent for the etching solution, an organic solvent that does not react with halogen is preferable, and aromatic hydrocarbons, alcohols, esters, nitriles, halogenated hydrocarbons of nitro compounds and the like are suitable, for example, acetonitrile, xylene, toluene and benzene. Is good. Further, the halogenated salt is preferably one having a surfactant-like property, for example, cetylpyridinium iodide, and the cation may be a halogenated salt such as an alkali metal ion, an alkaline earth metal ion or a quaternary ammonia ion. good. The simple substance of halogen preferably has a high electronegativity, and a component that does not react with an organic solvent is suitable. It is possible to selectively select the etching rates of the noble metal film, the mask material and the high dielectric constant film by combining the three kinds. Further, other components such as gold may be mixed in order to improve the characteristics due to the effect of the catalyst and the like. At this time, as a method of contacting the sample with the etching solution, the sample may be immersed in the etching solution, the etching solution may be vaporized, a spin coater, a spray, ultrasonic waves, pressure or the like may be used.

Next, the photosensitive composition is characterized in that it is not dissolved or exfoliated in the organic solvent-based etching solution. Specific examples of the positive resist include a resist having an alkali-soluble compound as a base polymer and a quinonediazide compound as a photosensitizer, and a chemically amplified positive resist. When a positive resist is used, it is desirable to perform a curing treatment called UV cure by irradiation with ultraviolet rays. The irradiation temperature and time are, for example, about 100 ° C. to 250 ° C. depending on the type of resist.
It can be appropriately selected from the range of 30 seconds to 20 minutes.

On the other hand, examples of the negative resist include isoprene-based resists and phenol-based resists which use an azide-type processed product as a photosensitizer. A negative resist generally has higher resistance to an organic solvent than a positive resist, but post-baking may be performed after development in order to further improve resistance to an organic solvent. if needed,
Irradiate ultraviolet rays to cure. The ultraviolet irradiation time is preferably less than 30 minutes, more preferably less than 15 minutes, further preferably less than 5 minutes.

In both cases of positive type and negative type resists, high dose ion implantation completes the curing and increases the etching resistance. ¹¹ B ⁺ , ³¹ P ⁺ , ⁷⁵ As ⁺
Ions that are normally used in the MOS process may be used, but the acceleration voltage is 100 to 200 KeV and the dose is Φ = 1 ×.
When it is carried out at 10 ¹⁵ cm ^-2 to 1 × 10 ¹⁶ cm ^-2 , the resist is hardened and the etching resistance becomes extremely strong. Also,
The compositions of the positive type and negative type resists are not limited to the above-mentioned systems. Further, although it has a drawback of low sensitivity, the inorganic resist is excellent in resistance as the etching mask of the present invention.

Further, as the mask material in the feature of the present invention, other than this, an inorganic thin film or metal thin film of oxide, nitride, carbide or the like which is not dissolved or exfoliated in the organic solvent type etching solution is used as a mask for fine processing. can do. For example, when a Br ₂ / CPB (cetylpyridinium bromide) / benzene system is used as the organic solvent-based etching solution, noble metals such as Pt, Au, and Pd dissolve well but oxides and nitrides hardly dissolve, The Pt lower electrode film can be processed using silicon oxide, titanium nitride, or the like, which has excellent processability by reactive ion etching, as a mask. Further, the perovskite crystal-based oxide high-dielectric thin film used as a high-dielectric constant capacitor material is also resistant to the Br ₂ / CPB / benzene-based etching solution, and the oxide high-dielectric thin film itself is used as a mask to form the lower electrode. Fine processing is also possible.

Further, the Br ₂ / CPB / benzene system is T
Since metals such as i, W, Ta and Al do not dissolve, the Pt lower electrode film can be processed by using these metals as a mask. These metal films can be used as the upper electrode of the charge storage capacitor and the wiring material, and the lower electrode and the dielectric film can be finely processed using the upper electrode as a mask.

An important point is that the above organic solvent-based etching solution does not etch single crystal silicon, polycrystalline silicon (polysilicon) and silicon oxide film (SiO ₂ ) at all. This fact makes the etchant highly compatible with silicon processes.

Further, as described above, these inorganic thin films and metal thin films are resistant to the above-mentioned organic solvent type etchant having a specific selective solubility, but the known lithography technique and plasma etching or wet etching are used. It can be microfabricated using technology.

Further, as a method of cleaning the etching solution,
Use sulfuric acid, hydrogen peroxide mixed acid solution, nitric acid, hydrochloric acid, hydrofluoric acid, etc. as the acidic solution, and alkali hydroxide, choline, MABT, etc. and alcohol as the alkaline solution so that no trouble occurs in the electric element. , Wash. At this time, go in the form of steam, apply ultrasonic waves and pressure,
The pressure may be reduced or heated.

Finally, it can be confirmed by the Auger electron spectroscopic analysis or the ion chromatograph analysis after the hot water extraction whether the halogen simple substance remains in the capacitor film. Is 0.
It can be 1 ppm or less.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. 2 is a plan view of a DRAM according to the first embodiment of the present invention, and FIG. 1 is a sectional view taken along line AA of FIG. The DRAM of the first embodiment of the present invention has a one-cell one-transistor structure as shown in the equivalent circuit of FIG. 3, and has barium strontium titanate (BST) 243 as an upper part in the storage capacitor portion (capacitor portion) of each cell. Tungsten (W) layer 244 serving as an electrode and platinum (Pt) layer 2 serving as a lower electrode
It has a structure sandwiched between 42. As shown in FIG. 1, the DRAM according to the first embodiment of the present invention has an impurity density of 1 × 10 ^{16 to} 5 × 10 ¹⁷ cm formed on the surface of the n-type substrate 12.
^A switching MOS transistor (selection transistor) and a capacitor portion are formed on the surface of the ⁻³ p well 19 to form an XY matrix as shown in FIG. Figure 2
, The word line 251 is an A1 wiring, and the bit line 2
Reference numeral 32 is an n ⁺ buried diffusion layer. That is, as shown in FIG. 1, the select transistor has an impurity density of 1 × 10 ^{19 to} 5 × 10 ²¹ cm ⁻³ formed on the surface of the p-well 19.
^{The +} region 231 serves as a source region, the n ⁺ region 232 also serving as a bit line serves as a drain region, and a thickness of 300 to 500 n formed on the gate oxide film 29 having a thickness of 30 to 50 nm.
Polysilicon (doped polysilicon; DOPOS) doped with m of arsenic (As) is used as the gate electrode 25. A capacitor portion is formed in an opening portion of interlayer insulating films 167 and 168 such as SiO ₂ / PSG or BPSG formed on the n ⁺ source region 231 of the select transistor. That is, an As-doped DOPOS layer and Ti are formed on the n ⁺ source region 231.
/ TiN barrier metal layer composite film layer (hereinafter referred to as DOP
An OS / barrier metal layer) 255 is formed by extending a part thereof onto the interlayer insulating film 167, and a thickness of 5 is formed thereon.
Lower electrode film 242 made of 0 nm Pt film, thickness 30 n
A BST film 243 of m and an upper electrode 244 of a W film serving as a storage electrode having a thickness of 150 nm are continuously deposited to form a storage capacitance of the capacitor part. The DOPOS / barrier metal layer has a 200 nm-thick DOPOS layer formed as a lower layer and a 50 nm-thick Ti / TiN layer formed thereon to prevent the reaction between the Pt film 242 and the DOPOS film. That is, the lower electrode 242 is electrically connected to the n ⁺ source region 231 of the switching MOS transistor (selection transistor) via the DOPOS / barrier metal layer 255, and the upper electrode 244 is the DOPOS or WS.
It is electrically connected to the plate electrode 245 made of a silicide film of i ₂ , MoSi ₂ , TiSi _2, or the like. A
The word line 251 made of Al, Al—Si, Al—Cu—Si film, or the like is gated through the openings (contact holes) of the interlayer insulating films 167, 168, 169 formed on the DOPOS gate electrode 25. It is electrically connected to the electrode 25. According to the present invention, a capacitance 100 times or more that of a conventional capacitor using a silicon oxide film (SiO ₂ ) can be obtained, so that the inside of a contact hole of about 0.5 μm × 0.5 μm or 0.2 μm × 0.2 μm can be obtained. Even if a capacitor is formed only in 256Mb DRAM, 1
The capacity required for GbDRAM or the like can be easily obtained.

The DRAM of the first embodiment of the present invention is shown in FIGS.
It can be manufactured by a method as shown in FIG.

(1) First, n is formed by an ordinary MOS process.
A p-well is formed in the substrate, an element isolation region (FOX) is formed by the LOCOS method or the like, and a polysilicon gate electrode 2 is formed.
N ⁺ by the self-alignment method using the pattern 5
A source region 231 and an n ⁺ drain region 232 are formed. For example, the thickness of the polysilicon layer 25 serving as DOPOS is set to 300 nm, ⁷⁵ As ^{+ is set} to the acceleration voltage of 50 KeV,
Dose amount Φ = 3 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻² If ion implantation is performed, n ⁺ source region 231 and n ⁺ drain region 232
Can be formed. As is apparent from FIGS. 1 and 2, the n ⁺ drain region 232 operates as a bit line of DRAM. After this, a SiO ₂ / PSG film is formed by CVD to a thickness of 300 n.
Then, the interlayer insulating film 167 is deposited to obtain the shape shown in FIG. The formation of the p ⁺ channel stop region, the channel-doped ion implantation, etc. are carried out as necessary, as in the process of the standard MOS DRAM, and the description thereof is omitted here.

(2) Next, a contact hole as shown in FIG. 4B is formed in the SiO ₂ / PSG film 167, and a 200 nm-thick As-doped n ⁺ DOPOS film is formed on the contact hole.
A layer is deposited by a CVD method, a Ti / TiN layer is deposited on the same by RF sputtering, a DOPOS / barrier metal layer 255 is formed, and a photolithography method is used to form a DOPOS / barrier metal layer 255 corresponding to the capacitor portion. A photoresist 51 is formed on.

(3) B using this photoresist as a mask
The DOPOS / barrier metal layer 255 is formed by RIE using Cl ₃ , CF ₄ , SF ₆ , or CCl ₄ as shown in FIG.
Patterning is performed as shown in FIG. Then, after removing this photoresist and washing, as shown in FIG.
A Pt film 242 having a thickness of 50 nm, a BST film 243 having a thickness of 30 nm, and a W film 244 having a thickness of 150 nm are continuously formed by an RF sputtering method. A CVD method may be used instead of RF sputtering. BST is a solid solution of barium titanate (BaTiO ₃ ) and strontium titanate (SrTiO ₃ ). As another method, as shown in FIG. 5A, only the DOPOS layer may be locally formed on the n ⁺ source region 231, and the Ti / TiN layer may be formed on the entire surface under the Pt film 242. Good. Adhesion between Pt and the SiO ₂ / PSG film 167 is better when it is formed on the entire surface. Next, as shown in FIG. 5A, a photoresist film 51 is formed by photolithography.

(4) Next, using the photoresist film 51 as a mask, reactive ion etching (RI) using CF ₄ is performed.
The W film 244 is etched by E) as shown in FIG.

(5) Then, as shown in FIG. 5 (c), the PZT layer is formed by using a predetermined etching solution such as a mixed aqueous solution of hydrogen peroxide, ammonia water and EDTA, using the W film 244 serving as an upper electrode as a mask layer. 243 is etched and patterned.

(6) Next, the BST formed in this step
As shown in FIG. 5D, using the layer 243 as a mask, iodine is used as a simple substance of halogen, cetylpyridinium iodide is used as a halide salt, and benzene is used as an organic solvent as an etching solution, and the etching solution is heated to 60 ° C. Then, the platinum layer 242 to be the lower electrode is patterned. After the treatment as described above, the Si substrate 1 is immersed in alcohol to wash the etching liquid. Then, using choline as the alkali hydroxide, the etching solution is thoroughly washed. As the choline, a cleaning solution known under the trade name of Shika Clean may be used. By performing the treatment as described above, the Pt lower electrode 24 can be easily formed on the n ⁺ source region 231 at low cost.
2. A capacitor cell as shown in FIG. 5D using the high dielectric film 243 and the W upper electrode 244 can be formed. Note that alkali hydroxide other than choline, MABT, or various alcohols may be used for cleaning the etching solution. At this time, it is preferable to perform it in a vapor state or to apply ultrasonic waves and pressure. Dry cleaning can be performed by using the cleaning liquid as vapor, that is, as gas, and heating it under reduced pressure.

(7) Next, SiO ₂ , PSG or B
An interlayer insulating film 168 such as a PSG film is deposited by a CVD method, a contact hole is formed above the W upper electrode 244, a DOPOS film or a WSi ₂ film is formed by a CVD method, and a photolithography and RIE method is used. 6
The plate electrode 245 is patterned as shown in FIG.

(8) After that, Si as shown in FIG.
Interlayer insulating film 1 such as O ₂ / PSG or Si ₃ N ₄ film
If the word line 251 is formed by forming 96 and further using Al, Al-Si, Al-Cu-Si, or the like on the upper part, a cross-sectional shape as shown in FIG. 1 is obtained.

7 and 8 are a sectional view of a nonvolatile memory according to the second embodiment of the present invention and its equivalent circuit.

In the second embodiment of the present invention, as shown in FIG. 7, a plurality of MOS transistors isolated from each other by an element isolation region 103 formed of a thermal oxide film of Si formed by a method such as LOCOS are n It is formed in a matrix on the surface of the p well 19 formed on the mold substrate 12. FIG. 7 is a sectional view taken along the drive line 222 shown in FIG. The MOS transistor shown in FIG.
03 on the gate oxide film 29, the gate electrode 25, the source region 231 and the drain region 232, which are n ⁺ regions in the p well 19, and the like. Here, the gate electrode 25 forms a part of the word line. In addition, a bit line 233 is formed on the drain region 232, and the source region 231 has a lead-out electrode 341 for connection with a thin film capacitor via a plug-shaped contact portion 355.
Connected to In the figure, 167 and 168 are interlayer insulating films,
Reference numeral 169 is a planarizing interlayer insulating film. Contact part 35
5 is a selection C of refractory metal such as DOPOS or W
It may be done by VD. The extraction electrode 341 is Ti / Ti
A refractory metal such as N may be used. Extraction electrode 341
Acts as a barrier metal and at the same time Pt lower electrode 342
And the interlayer insulating film 169.
A lower electrode 342 made of a Pt film having a thickness of 200 nm, a lead zircon titanate titanate film (PZT film) 343 having a thickness of 300 nm, and an upper electrode 344 made of a Pt film having a thickness of 200 nm are formed on the extraction electrode 235 to form a capacitor. Forming a part. PZT is lead zirconate (PbZrO
₃ ) and lead titanate (PbTiO ₃ ) solid solution.

FIG. 8 is an equivalent circuit diagram of the nonvolatile memory according to the second embodiment of the present invention. As shown in the figure, here, a 1-bit memory cell is composed of one switching transistor 901 and one thin film capacitor 902 and arranged in a matrix. Gate electrode 25 of switching transistor 901 is coupled to word line 251, and drain region 232 is coupled to bit line 233. Further, a pair of electrodes of the thin film capacitor 902 are connected to the source region 231 of the switching transistor 901 and the drive line 222, respectively. At this time, the word line 251
And the drive line 222 are orthogonal to each other and are coupled to the word line selection circuit 26 and the drive line drive circuit 27, respectively, and two bit lines 233 form a bit line pair to form one drive line 222. It is arranged on both sides of the pinch and is coupled to the sense amplifier 28.

When writing to this semiconductor memory device, for example, the word line selecting circuit 26 selects the word line 251 of a predetermined row address, and the selected word line 2 is selected.
After activating 51 and turning on the switching transistor 901 coupled thereto, a potential corresponding to information "1" or "0" is applied to the bit line 233 for a predetermined column address, and a drive line drive circuit is provided. The drive line 222 is activated by 27 and the write signal is transmitted. Next, when the activation of the word line 251 is stopped and the switching transistor 901 is returned to the OFF state, "1" or "1" is given to the thin film capacitor 902 in the memory cell selected by the product of the row address and the column address as described above. Information of "0" is accumulated and held, and information is written. After this, the switching transistor 90 of the memory cell in which the information is written is
The written information is not lost even if one of the word line 251 and the drive 222, which are connected to the 1 or the thin film capacitor 902, is activated.

On the other hand, when reading the semiconductor memory device, the word line selecting circuit 26 first selects the word line 251 of a predetermined row address, and the selected word line 25.
1 is activated and the switching transistor 901 connected to this is turned on. Subsequently, the drive line drive circuit 27, which precharges the bit line pair for a predetermined column address to bring it into a floating state, activates the drive line 222 to apply a predetermined potential. Here, the thin film capacitor 90 of the memory cell selected by the product of the row address and the column address as described above.
The information stored and held in 2 is taken out to one bit line 251 of the precharged bit line pair through the switching transistor 901, and a minute potential difference according to the taken out information is taken out to the bit line 251. Then, a minute potential difference according to the extracted information is formed between the bit line pair. Therefore, by amplifying this potential difference by the sense amplifier 28, it becomes possible to read the information stored and held in the thin film capacitor 902 in the memory cell. Further, the same information as before reading is written by a predetermined operation to the thin film capacitor 902 in the memory cell from which the information is taken out as described above, and the information is written.

Here, a method of manufacturing the nonvolatile memory of FIG. 7 will be described with reference to FIG. The step of forming a MOSFET composed of the n ⁺ drain region 232, the DOPOS gate electrode 25 and the like on the p well 19 in FIG.
Similar to the first embodiment of the present invention, a normal standard MOS process, for example, a self-alignment process using a DOPOS goethe electrode may be used, and a description thereof will be omitted. Here, these MOSFETs are almost formed and a thickness of 1 μm is formed on them.
The description will be made after the interlayer insulating film 169 of m PSG, SiO ₂ , or BPSG film is accumulated.

(1) After depositing the interlayer insulating film 169 by the CVD method or the like, a contact hole is opened in the upper portion of the n ⁺ source region 231, and a selective CVD process of a refractory metal such as W or Ti or DOPOS is performed in the opening. The contact portion 355 is formed. Then, a thickness of 50 is formed on the contact portion 355 and the interlayer insulating film 169 by an ordinary sputtering film forming method.
nm barrier metal layer 341 made of titanium and titanium nitride thin film and a thickness of 200 serving as a lower electrode of a capacitor.
nm platinum layer 342 and then conventional plasma CVD
A silicon oxide film 59 having a thickness of 300 nm is formed by a photolithography method, the resist 51 is covered at a desired position by ordinary photolithography, and the silicon oxide film is formed by a plasma etching method using CF ₄ / H ₂ or the like using the resist 51 as a mask. 51 is etched and patterned as shown in FIG.

(2) Resist 5 after plasma etching
1 is removed, the substrate 19 is washed, and then the platinum layer 342 is removed with an etching solution containing a simple substance of halogen, a halogenated salt and an organic solvent using the silicon oxide film 59 as a mask, as shown in FIG. Etching. For example, as an etching solution at this time, bromine is used as a simple substance of halogen, cetylpyridinium bromine is used as a halogenated salt, and benzene is used as an organic solvent.
This etching solution is heated to 30 ° C. to etch the platinum layer 342. After the treatment as described above, the Si substrate 19 is immersed in alcohol to wash the etching liquid. Then,
As the cleaning with the acidic solution, the etching solution is completely cleaned by immersing it in a mixed oxygen solution of sulfuric acid and hydrogen peroxide. In addition,
At least three kinds of halogen simple substance, halogenated salt and organic solvent are indispensable for the etching solution, and further, other components such as gold may be mixed in order to improve the characteristics due to the effect of the catalyst and the like. At this time, as a method of contacting the sample with the etching solution, the sample may be immersed in the etching solution, the etching solution may be vaporized, a spin coater, a spray, ultrasonic waves, pressure or the like may be used.

(3) Next, the platinum lower electrode 34 is formed by ordinary plasma etching using, for example, CF ₄ / H ₂ or the like.
The silicon oxide film 59 on 2 is removed. Further, the titanium and titanium nitride layers 341 which are the barrier metal layers are removed by plasma etching using the platinum lower electrode 342 as a mask as shown in FIG. 9C.

(4) After this, the thickness is set to 30 by the sputtering method.
By forming the PZT film 343 which is a 0 nm ferroelectric thin film and the platinum upper plate electrode 344 having a thickness of 200 nm, a nonvolatile memory having a ferroelectric capacitor portion can be prepared. The upper platinum electrode 344
Since it is a plate electrode, it is generally unnecessary to perform fine processing, but it is possible to perform processing by using the same method as in the case of etching the lower electrode 342, if necessary.

FIG. 10 is a diagram for explaining the third embodiment of the present invention, which relates to another method of manufacturing the nonvolatile memory (FIG. 7) described in the second embodiment of the present invention. . Similar to the second embodiment of the present invention, a MOSFET is almost formed,
1 μm thick PSG, SiO ₂ or BP
The description will be made after the interlayer insulating film 169 made of an SG film or the like is accumulated.

(1) After depositing an interlayer insulating film 169 by a CVD method or the like, a contact hole is formed in the upper portion of the n ⁺ source region 231, and a selective CVD method of a refractory metal such as W or Ti or DOPOS is formed in the opening. The contact portion 355 is formed. Then, a barrier metal layer 341 made of titanium and titanium nitride thin film and a platinum layer 342 serving as a lower electrode of the capacitor are formed on the contact portion 355 and the interlayer insulating film 169 by a normal sputtering film forming method, and then as a positive resist. A novolak resin 51 using a quinonediazide derivative as a photosensitizer is applied, and after a normal pre-baking process, a resist pattern as shown in FIG.
UV cure at 70 ° C. for 3 minutes. Then ³¹ P ⁺ or
¹¹ B ⁺ acceleration voltage 150 keV, dose 1 × 10 ¹⁵
8 × 10 ¹⁵ cm ^-2 , resist surface and platinum layer 342
The entire surface is ion-implanted. By this ion implantation, the resist is hardened and the etching resistance is improved.

(2) FIG. 10B is a cross-sectional view after etching when the ion implantation resist 52 is used as a mask. The etching solution at this time is
Bromine was used as a simple substance of halogen, cetylpyridinium bromine was used as a halogenated salt, and benzene was used as an organic solvent, and the platinum layer 3 was etched by heating at 30 ° C. After processing in this way, Si
The substrate is dipped in alcohol to wash the etching solution. Then, as a cleaning with an acidic solution, it is immersed in a mixed oxygen solution of sulfuric acid and hydrogen peroxide solution to completely clean the etching solution.
The etching solution is composed of at least three kinds of simple substance of halogen, halogenated salt and organic solvent, but other components may be mixed in order to enhance the effect as a catalyst. Other components such as gold may be mixed as the catalyst. At this time, as a method of contacting the sample with the etching solution,
The sample may be dipped in the etching solution, the etching solution may be vaporized, and a spin coater, atomization, ultrasonic waves, pressure or the like may be used.

(3) In FIG. 10C, subsequently, the pattern of the ion implantation resist 52 is continuously used as a mask layer.
The barrier metal layer of titanium and titanium nitride layer 341 has just been removed by ordinary reactive ion etching (RIE). CCl as an etchant for RIE
₄ or CF ₄ may be used.

(4) After that, the ion-implanted resist 52 is removed by using oxygen plasma, and a zircon / lead titanate (PZT) film 343 which is a ferroelectric thin film is formed by a sputtering method.
By forming the platinum upper plate electrode 344 and the non-volatile memory having the high dielectric capacitor shown in FIG. 10D. Since the upper platinum electrode 344 is a plate electrode, it is generally unnecessary to perform fine processing, but it is possible to perform processing by using a method exactly the same as the above-described steps, if necessary.

Further, it can be confirmed by the Auger electron spectroscopic analysis or the ion chromatograph analysis after the extraction with hot water whether or not the simple substance of halogen remains in the capacitor film. According to the above washing method, the residual halogen is 0.1 ppm. Can be

FIG. 11 is a schematic cross-sectional view in order of the steps, showing a method for manufacturing a dielectric capacitor cell according to the fourth embodiment of the present invention. The capacitor cell of the fourth embodiment of the present invention is shown in FIG.
As shown in (e), a thermal oxidation film 469 of Si is formed on a Si substrate 468, a barrier metal layer 442 made of Ti and TiN is formed thereon, and a platinum lower electrode 242 and PZT are further formed thereon. A dielectric thin film (hereinafter referred to as a dielectric thin film) 243 made of a ferroelectric substance or a high dielectric substance made of STO, and a capacitor made of a platinum upper electrode 444 are formed.

The dielectric capacitor cell of the fourth embodiment of the present invention is manufactured by the following steps.

(1) First, an oxide film 469 is formed on the Si substrate 468 by a thermal oxidation method or the like. Then, on the Si thermal oxide film 469, Ti / Ti is formed by a normal sputtering film forming method.
N layer 442, platinum layer 24 serving as the lower electrode of the capacitor
2. Dielectric thin film 243 and platinum 444 to be the upper electrode
Are sequentially formed, a silicon-based inorganic resist is applied, and a photolithography process is performed. That is, after a normal pre-baking, exposure using a predetermined mask, and a developing process, post-baking is performed at 130 ° C. for 30 minutes.
A sectional shape as shown in (a) is obtained.

(2) Next, iodine is used as a simple substance of halogen, cetylpyridinium iodide is used as a halide salt, and benzene is used as an organic solvent as an etching solution, and the mixture is heated to 60 ° C. and, as shown in FIG. The platinum layer of the electrode 444 is patterned.

(3) Thereafter, as shown in FIG. 11C, the inorganic resist pattern 53 is used as a mask layer to perform a predetermined etching such as a mixed aqueous solution of hydrogen peroxide solution, ammonia water and EDTA (ethylenediamine acetic acid). The dielectric thin film 243 is patterned by the liquid.

(4) Iodine, cetylpyridinium iodide, and benzene are used again as an etching solution, and the etching solution is heated to 60 ° C. to perform patterning by etching the platinum layer 242 of the lower electrode. Finally CCl ₄
Alternatively, the Ti / TiN layer 442 is formed by using RIE of CF _4.
Is etched as shown in FIG.

(5) After the above processing, the Si substrate is immersed in alcohol to wash the etching solution. further,
The etching solution is thoroughly washed with alkali hydroxide, choline and MABT. At this time, ultrasonic cleaning, preferably 2
Frequency ultrasonic cleaning. If the resist remaining as the mask is removed by ashing with an asher, the result shown in FIG.
A capacitor cell as shown in (e) is completed.

By carrying out such a treatment, it is possible to easily form a capacitor cell using a ferroelectric film or a high dielectric film on the SiO ₂ film at low cost.

In the first to fourth embodiments of the present invention, the example in which the noble metal thin film is used as the electrode of the capacitor has been shown, but the present invention is not limited to these embodiments, and an individual device (discrete device). It can be used for semiconductor devices using various noble metal thin films, such as logic integrated circuits. According to the present invention, since the noble metal thin film can be patterned by using photolithography, the noble metal thin film itself can be used as a wiring metal, and has much higher resistance than Al and Al-Si which have been mainly used conventionally. A small wiring is possible. The fact that the wiring resistance is small makes it possible to increase the operation speed in a memory such as a 1 Gb DRAM or a semiconductor device having a high integration density such as a logic integrated circuit corresponding thereto. When a noble metal is used as a raw material of silicide, for example, PtSi ₂ silicide is used as a wiring material or an electrode contact portion, a Pt film is formed on a silicon surface and then formed into a desired pattern by the Pt etching method of the present invention. Then, heat treatment is performed thereafter to form a silicide film. At the time of etching the Pt film, the underlying silicon surface is not etched at all. Further, when a noble metal is used for improving the characteristics of metal / semiconductor interfaces such as various ohmic contacts and Schottky contacts, for example, even when it is used as a barrier metal, the noble metal layer can be easily patterned by using the etching method of the present invention. .

In the description of the first embodiment of the present invention, FIG.
In (d), the n ⁺ source region 231 of the MOS transistor
DRA with a capacitor part made of BST243
Although the structure of M is shown, the source electrode of the compound semiconductor device,
Contact electrode metal such as drain electrode, for example, gold-germanium alloy (Au
The etching technique of the present invention can also be used when patterning a composite film including a (Ge alloy) and a gold (Au) film. For example, GaAs-MESFET Au-Ge
The patterning of the / Au contact electrode may be performed as follows.

(1) First, a predetermined field oxide film is formed on the surface of the p-type GaAs substrate other than the active region by the CVD method or the like, and the n ⁺ source is formed by the self-alignment method using the pattern of the gate electrode 25 made of TiW / Ti. Area 2
A 31, n ⁺ drain region 232 is formed in the same manner as in FIG. Semi-insulating GaAs instead of p-type GaAs substrate
It may be a substrate. The p well portion 19 in FIG. 4A is made of GaAs.
Corresponds to the substrate. For example, ⁷⁹ Se ⁺ or ³² S ⁺ is used as the acceleration voltage of 50 KeV and the dose amount is Φ = 3 × 10 ¹⁵ to 1 × 10.
If ion implantation is performed at ¹⁶ cm ⁻² , n ⁺ source regions 231 and n
^{+ A} drain region 232 can be formed. When a breakdown voltage is required, side walls of SiO ₂ or the like may be formed on both sides of the gate electrode 25 and then ion implantation may be performed. (MESF
Since it is ET, it goes without saying that the gate oxide film 29 of FIG. An n-type channel layer is formed on the surface of the GaAs substrate below the gate electrode. After that, a SiO ₂ film is deposited to a thickness of 300 nm by a CVD method to form an interlayer insulating film 167, and a shape similar to that shown in FIG. 4A is obtained.

(2) Next, the SiO ₂ film 167 is formed as shown in FIG.
Similar contact hole that shown in n ⁺ source region 23
A hole is formed only in the upper part of the 1, n ⁺ drain region 232, and an Au layer having a thickness of 200 nm is formed thereon by a normal EB vapor deposition method.
A contact electrode layer made of a Ge alloy and a gold film is formed, and a Ti film having a thickness of 5 nm is further formed. FIG.
Although the DOPOS / barrier metal layer 255 is formed in (b), in the present embodiment, instead of the DOPOS / barrier metal layer 255, an Au—Ge alloy, a gold film, and a Ti film are formed.
Form a composite membrane of membranes.

(3) Next, as shown in FIG. 4B, only the Ti film is removed by ordinary photolithography, that is, by the plasma etching method using the photoresist 51 as a mask and BCl ₃ -based gas. Patterning is performed so that only the peripheral portion of the contact hole remains.

(4) Next, using the Ti film as a mask, Au-G
Etching of e-alloy and gold film. The etching solution used at this time is bromine as a simple substance of halogen, cetylpyridinium bromide as a halide salt, and benzene as an organic solvent. The etching liquid is heated to 30 ° C. before use. This etching solution has the ability to dissolve gold or gold-germanium alloy, which is the contact electrode, but titanium as a mask material,
The silicon oxide film and tungsten as the gate electrode are not dissolved. Therefore, it is possible to selectively remove the portion covered with the mask by etching.
In FIG. 4B, the TiW / Ti gate electrode 25 is SiO ₂
Although it is covered with the film 167, it is not etched even if the gate electrode 25 is exposed. Note that the titanium layer used as a mask can be used as an adhesive layer when wiring is further formed. Further, in order to prevent the compound semiconductor substrate from being dissolved by the etching solution, a silicon oxide film may be previously formed on the back surface of the substrate. Thus, Au-Ge / is formed only inside the contact hole on the surface of the n ⁺ source / drain region or only inside and around the contact hole.
An Au contact electrode layer can be formed. In addition, MESFE
Although T has been described as an example, it goes without saying that the etching technique of the present invention can be used for patterning the contact electrode layer of another compound semiconductor device such as HEMT or HBT. It will be apparent from the above description that it can also be used for patterning various wiring layers of a compound semiconductor device. Further, the contact electrode is not limited to Au-Ge / Au, but Ti / Pt / Au, AuGe / Ni /
Ti / Au, TiWSi _x / Au or Pd / Ge,
Etc., the pattern formation by selective etching of these various precious metals becomes possible without using the lift-off process.

[0067]

As described above in detail, according to the present invention, high integration having a thin film capacitor composed of a noble metal electrode and a high dielectric constant film, which has been difficult to perform fine processing in both wet etching and dry etching, has been achieved. Various semiconductor devices using semiconductor memory elements and other noble metal thin films as wiring materials and electrode materials can be realized, and the industrial value of the present invention is extremely high.

According to the present invention, the noble metal thin film can be easily used as the wiring layer, the delay caused by the resistance of the wiring layer can be reduced, and the speed of the semiconductor integrated circuit can be increased. As the integration of semiconductor integrated circuits progresses, each cell is miniaturized and the operating speed of the cell itself becomes extremely high, but the propagation delay due to the wiring connecting the cells becomes a very serious problem. By using the noble metal etching method of the present invention, it becomes possible to use the noble metal thin film as a wiring metal, and it is possible to achieve high integration and high speed operation of a semiconductor integrated circuit.

According to the present invention, the noble metal thin film can be easily formed on the metal / semiconductor interface, and the metal / semiconductor interface can be stabilized and highly reliable. Therefore, the ohmic contact resistance can be easily reduced, and the semiconductor device can be operated at high speed, high frequency, and low noise.

[Brief description of drawings]

FIG. 1 is a sectional view of a DRAM according to a first embodiment of the present invention.

FIG. 2 is a plan view of a DRAM according to the first embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram of the DRAM according to the first embodiment of the present invention.

FIG. 4 is a view (No. 1) showing a manufacturing process of the DRAM according to the first embodiment of the present invention.

FIG. 5 is a view (No. 2) showing the manufacturing process of the DRAM according to the first embodiment of the present invention.

FIG. 6 is a view (No. 3) showing the process of manufacturing the DRAM according to the first embodiment of the present invention.

FIG. 7 is a sectional view of a nonvolatile memory according to a second embodiment of the present invention.

FIG. 8 is an equivalent circuit diagram of a nonvolatile memory according to a second embodiment of the present invention.

FIG. 9 is a view showing the manufacturing process of the nonvolatile memory according to the second embodiment of the present invention.

FIG. 10 is a view showing the manufacturing process of the nonvolatile memory according to the third embodiment of the present invention.

FIG. 11 is a view showing a manufacturing process of the ferroelectric capacitor according to the fourth embodiment of the present invention.

[Explanation of symbols]

12 n substrate 19 p well 25,251 word line 26 word line selection circuit 27 drive line drive circuit 28 sense up 29 gate oxide film 51 photoresist 52 ion implantation resist 53 inorganic resist 59 CVDSiO ₂ 103,196 insulating film 166,167, 168, 169 Interlayer insulating film 231 Source region 232 Drain region 222 Drive line 233 Bit line 242 Lower Pt electrode 243 Dielectric layer (dielectric thin film) 244 Upper W electrode 245 Plate electrode 255 Dopos layer and Ti / TiN barrier metal layer Composite film layer 342 Lower Pt electrode 343 Dielectric layer (dielectric thin film) 344 Upper Pt electrode 355 Contact part 442 Ti / TiN layer 444 Upper Pt electrode 468 Si substrate 469 Oxide film 901 Switching transistor Star 902 capacitor

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Motoo Yabuki 1 Komukai Toshiba-cho, Kouki-ku, Kawasaki-shi, Kanagawa Toshiba Research & Development Center

Claims (4)

[Claims] 1. A noble metal thin film formed on the surface of a semiconductor device is selectively etched using a predetermined mask material by using an etching solution containing at least a halogen simple substance, a halogenated salt, and an organic solvent, and a desired mask is formed. An etching method characterized by obtaining a pattern of a noble metal thin film. 2. The etching method according to claim 1, wherein the noble metal thin film is at least one electrode of a charge storage capacitor portion of a semiconductor memory device. 3. The etching method according to claim 1, wherein the noble metal thin film is a platinum (Pt) thin film. 4. The predetermined mask material is an oxide, a nitride,
2. The etching method according to claim 1, wherein the mask material is an insoluble mask material selected from the group consisting of a carbide, an inorganic thin film, a metal thin film, and a photosensitive composition.