JPH08249272A - Signal processing processor down-loading circuit - Google Patents

Abstract

PURPOSE: To reduce the time for necessary for transferring data. CONSTITUTION: CPU 1 selects data to send to DSP 4a to 4c corresponding to the kind of a signal processing which each DSP takes in its charge, and sends it. An address decoding circuit 2 divides data sent from CPU 1 toward each DSP into block data and simultaneously transfers them to each DSP. Simultaneous transfer like this can reduce the time for transfer. At the time of receiving a response from each DSP, CPU 1 judges whether a fault is generated based on this response, and at the time of judging the generation of fault, CPU 1 retransfers data. Thus, a fault is judged each time of transferring one block data, and the time for retransfer can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processor download circuit for transferring data to a plurality of signal processors at high speed.

[0002]

2. Description of the Related Art Conventionally, there is an acoustic system such as a sonar (SONAR), and the signal processor of this sonar requires high-speed processing of the received signal obtained from the reflected wave of the transmitted ultrasonic beam. Signal processor (hereinafter D
SP) is used. Then, in order to operate these DSPs, data (program) is stored in each DSP.
Since it is necessary to transfer the data, a download circuit for realizing such transfer is provided. FIG. 5 is a block diagram of a conventional download circuit, and 11 is a plurality of DSPs.
To the CPU, 12 is an interface circuit for performing communication processing between the CPU 11 and a plurality of DSPs,
14a to 14c are DSPs.

First, the CPU 11 selects data to be sent to each of the DSPs 14a to 14c according to the type of signal processing that each DSP handles, and starts data transfer. At this time, there are two types of data transfer: transfer of the same data common to each DSP and transfer of individual data for each DSP. In the case of transfer of the same data, the CPU 11 causes the DSP 14
Data is simultaneously sent to a to 14c. As a result, the data sent from the CPU 11 is transferred to the DSPs 14a to 14c via the interface circuit 12.

When transferring individual data, the CPU 1
The first device 1 first sends the selected individual data to the DSP 14a, and when receiving a response from the DSP 14a indicating the completion of reception, next sends the selected individual data to the DSP 14b. In this way, the transfer of individual data is sequentially performed for each DSP. In this way, the DSPs 14a to 14c that have received the data (program) process received signals and the like input from an external device (not shown) according to the program. Next, the failure processing of the download circuit will be described. FIG. 6 is a flow chart for explaining this failure processing.

When the same data and individual data are transferred by the above-mentioned operation (steps 200 to 203), reception is completed from each DSP every time the same data transfer and the individual data transfer to each DSP are completed. Will be sent back. This response includes error information indicating whether or not the data was successfully received.
Determines whether or not a failure has occurred based on the error information after completion of all data transfer (step 204). If it is determined that a failure has occurred, the data transfer is prepared again (step 201), and the same data and individual data are transferred again (steps 202, 20).
3). Therefore, when a failure occurs, it takes twice as long as in a normal case.

[0006]

The conventional download circuit transfers data to a plurality of DSPs as described above. However, in the case of transferring individual data, transfer is performed to a certain DSP to complete reception. There is a problem in that the time required for the transfer becomes long because the transfer is performed to the next DSP after waiting for the response and receiving the response from this DSP. In addition, since the failure determination is performed after the completion of all data transfer, if a failure occurs, the data is retransferred to
There was a problem that it took twice as long. The present invention has been made to solve the above problems, and an object of the present invention is to provide a download circuit that can reduce the time required for data transfer.

[0007]

SUMMARY OF THE INVENTION According to the present invention, a CPU for sending the same data and individual data to be transferred to a signal processor in a batch and a predetermined data for each signal processor are sent. An address decoding circuit that repeats, for each block data, dividing into block data, which is a unit of, and transferring to each signal processing processor all at once, and provided between the address decoding circuit and each signal processing processor. And a plurality of interface circuits.

Further, the CPU receives the response data returned from each signal processor upon completion of the reception of the block data through the interface circuit and the address decoding circuit, and an abnormality occurs in the transfer of the block data from the response data. When it is determined that the data has been transferred, the current transfer operation is stopped and the data is retransmitted.

[0009]

According to the present invention, the address decoding circuit has the CP
Divide the data sent from U into block data,
Transfers to all signal processors all at once. Also,
When the CPU determines a failure based on the response data returned from each signal processor upon completion of receiving the block data, and determines that an error has occurred in the data transfer,
Retransmit the data.

[0010]

FIG. 1 is a block diagram of a download circuit showing an embodiment of the present invention. 1 is a CPU, DSP4
The same data and individual data to be transferred to a to 4c are sent together and the response data returned from each DSP upon completion of data reception is received, and an abnormality occurs in data transfer from this response data. If so, the current transfer operation is stopped and the data is transferred again.

Further, 2 is an address decoding circuit 3a which repeats, for each block data, dividing the data sent from the CPU 1 for each DSP into block data, which is a predetermined unit, and transferring them all at once to each DSP. ~ 3
c is an interface circuit provided between the address decoding circuit 2 and each DSP, and 4a to 4c are DSPs.
Is.

Next, the operation of such a download circuit will be described. FIG. 2 is a timing chart for explaining the transfer processing of this download circuit.
2 (a) to 2 (c) are the operations of this embodiment, and FIGS. 2 (d) to 2 (f).
Is the operation of the example of FIG. In FIG. 2, D1 is the same data, D2 is individual data, a1, a2, b1, b2, c.
1 and c2 are block data.

First, the CPU 1 selects the data to be sent to each of the DSPs 4a to 4c according to the type of signal processing that each DSP handles, and then the same data D1 that was separately transferred in the example of FIG. The data D2 are collectively sent to the address decoding circuit 2. In addition, CPU1
Identification information indicating which DSP the data is for is added to the data transmitted from the.

Next, the address decoding circuit 2 stores the addresses of the interface circuits 3a to 3c (that is, the addresses of the DSPs 4a to 4c) corresponding to the identification information, and converts the identification information added to the data into the addresses. Then, the data is sent to the interface circuit of the corresponding address. At this time, the CPU 1
2A to 2C, the data sent from is divided into block data, which is a predetermined unit, and sent for each block data.

First, the address decoding circuit 2 is a DSP.
The first block data a1 in the data for 4a is DS
It is sent to P4a, and in parallel with this, the first block data b1 in the data for the DSP4b is sent to the DSP4b, and similarly, the first block data c1 of the data for the DSP4c is sent to the DSP4c. . In this way, the block data a1, b1, c1 sent from the address decoding circuit 2 are sent to the interface circuits 3a, 3b, 3c, respectively, and transferred to the DSPs 4a-4c via the respective interface circuits. In addition, DSP
4a to 4c look at the address added to the data and receive only the data addressed to them.

Next, the address decoding circuit 2 sends the next block data a2 when the sending of the block data a1 is completed, and the data b when the sending of the data b1 is completed.
2 is transmitted, and similarly when the transmission of the data c1 is completed, the data c2 is transmitted. In this way, by transferring the data to the DSPs 4a to 4c all at once in parallel,
Compared with the case where individual data D2 is sequentially transferred for each DSP as in (d) to (f), the time required for transfer is 1 /
It can be shortened to about 2.

Since the transfer time from the CPU 1 to the address decode circuit 2 in this embodiment is substantially the same as the transfer time from the CPU 11 to the interface circuit 12 in the example of FIG. 5, the transfer time is as shown in FIGS. Ignoring these transfer times, the transfer time from the address decode circuit 2 to each DSP is compared with the transfer time from the interface circuit 12 to each DSP.

Next, the failure processing of this embodiment will be described. FIG. 3 is a flow chart for explaining this failure processing. Due to the above-described operation, the DSP 4 in this embodiment is
Block data is transferred one after another without waiting for a response from a to 4c. However, when the block data is transferred (steps 100 to 102), the reception completion from each DSP is completed each time the data reception is completed. The response data to notify is returned.

The interface circuits 3a to 3c are DSPs.
After transferring the block data to 4a to 4c, it waits for a response returned from each DSP, and when there is a response from the DSP, this is sent to the address decoding circuit 2. As a result, this response is sent back to the CPU 1 via the address decoding circuit 2. The response data from each DSP includes error information indicating whether or not the block data can be normally received, and the CPU 1 determines that each DSP
Upon receiving the response from, it is determined whether or not a failure has occurred based on the error information (step 103).

If no failure occurs, the block data transfer is repeated until the end of all data (step 104). Further, for example, when a failure occurs in the block data a2, the response data returned from the DSP 4a upon completion of the reception of the data a2 includes error information notifying the occurrence of the failure. Therefore, the CPU 1 stops the current transfer operation, Prepare for data transfer again (step 101),
The transfer is redone (step 102).

As shown in FIGS. 4D to 4F, in the example of FIG. 5, even if a failure occurs at the position corresponding to the data a2,
After all the transfers are completed, the failure judgment is performed and the retransfer is performed. On the other hand, in this embodiment, since the failure determination is made every transfer of one block data, the block data a2
4A to 4C, the current transfer operation is stopped and the retransfer is started without performing all data transfer. The transfer can be performed.

[0022]

According to the present invention, since the address decoding circuit divides the data sent from the CPU into block data and transfers them to all the signal processors at the same time, the time required for the transfer can be shortened compared to the conventional case. It can be shortened. Also, the CPU makes a failure determination based on the response data,
By re-transferring the data when it is determined that an error has occurred in the data transfer, the failure determination is performed for each transfer of one block of data, so that the re-transfer can be promptly performed when the failure occurs. Therefore, the time required for transfer can be shortened as compared with the conventional case.

[Brief description of drawings]

FIG. 1 is a block diagram of a download circuit showing an embodiment of the present invention.

FIG. 2 is a timing chart diagram for explaining transfer processing of the download circuit of FIG.

3 is a flow chart diagram for explaining failure processing of the download circuit of FIG. 1. FIG.

4 is a timing chart diagram for explaining failure processing of the download circuit of FIG. 1. FIG.

FIG. 5 is a block diagram of a conventional download circuit.

FIG. 6 is a flow chart diagram for explaining failure processing of the download circuit of FIG. 5;

[Explanation of symbols]

1 ... CPU, 2 ... Address decode circuit, 3a to 3c ...
Interface circuits 4a to 4c ... DSP, D1 ... Same data, D2 ... Individual data, a1, a2, b1, b2,
c1, c2 ... Block data.

Claims (2)

[Claims] 1. A signal processor download circuit for transferring, to a plurality of signal processors, the same data common to each processor and individual data for each processor, and the same data to be transferred to the signal processor. A CPU that sends individual data as a group and a unit that divides each data sent from the CPU for each signal processor into block data, which is a predetermined unit, and transfers the data to each signal processor all at once It has an address decode circuit that repeats for each block data, and a plurality of interface circuits provided between the address decode circuit and each signal processor, and transfers the block data to the signal processor via this interface circuit. Signal processing processor characterized by Download circuit. 2. The signal processor download circuit according to claim 1, wherein the CPU receives response data returned from each signal processor upon completion of reception of block data via an interface circuit and an address decode circuit. Then
A signal processor download circuit, characterized in that, when it is determined that an error has occurred in transfer of block data from response data, the current transfer operation is stopped and data is retransmitted.