JPH08244877A - Tray for transport and storage of semiconductor element - Google Patents
Tray for transport and storage of semiconductor elementInfo
- Publication number
- JPH08244877A JPH08244877A JP7044514A JP4451495A JPH08244877A JP H08244877 A JPH08244877 A JP H08244877A JP 7044514 A JP7044514 A JP 7044514A JP 4451495 A JP4451495 A JP 4451495A JP H08244877 A JPH08244877 A JP H08244877A
- Authority
- JP
- Japan
- Prior art keywords
- tray
- semiconductor element
- thickness
- depth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Packaging Frangible Articles (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、上面に半導体素子を収
めるポケットを有し、積層使用を想定した嵌合構造を有
する半導体素子の搬送及び保管用トレイに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tray for transporting and storing semiconductor elements, which has a pocket for accommodating semiconductor elements on its upper surface and has a fitting structure designed for stacking.
【0002】[0002]
【従来の技術】図8はこの種の半導体素子の搬送及び保
管用トレイ(以下トレイとする)の従来例を示す側断面
図である。図において、1はトレイであり、2は該トレ
イの上面に設けたポケット2であり、該ポケット2の中
に半導体素子3が収まる。このトレイ1は積層使用を想
定した嵌合構造を周囲に有する。2. Description of the Related Art FIG. 8 is a side sectional view showing a conventional example of a tray for transporting and storing semiconductor elements of this type (hereinafter referred to as tray). In the figure, 1 is a tray, 2 is a pocket 2 provided on the upper surface of the tray, and the semiconductor element 3 is accommodated in the pocket 2. This tray 1 has a fitting structure on the periphery which is intended for stacking.
【0003】ここで、トレイ1が前述の如く重ねること
を想定してあるため、ポケット2の深さは半導体素子3
の厚み以上なければならず、また、ポケット2の大きさ
も適度な余裕をもって作られている。以上の構成の上記
従来例の作用は以下の如くである。回路形成面3aを表
にして切り出された半導体素子3は、吸引等の方法によ
りこのトレイ1のポケットの中に移載され、搬送・保管
等がなされる。また、この半導体素子3を別の半導体素
子や基板等に搭載して使用する場合には、半導体素子3
は吸引等の方法によりこのトレイ1のポケット2からそ
のまま移載され、ワイヤボンディング等の方法で接続さ
れる。Since it is assumed that the trays 1 are stacked on each other as described above, the depth of the pocket 2 is set to the semiconductor element 3.
The thickness of the pocket 2 must be equal to or greater than the thickness of the pocket 2, and the size of the pocket 2 is made with an appropriate margin. The operation of the above-described conventional example having the above configuration is as follows. The semiconductor element 3 cut out with the circuit forming surface 3a facing up is transferred into the pocket of the tray 1 by a method such as suction, and transported and stored. When the semiconductor element 3 is mounted on another semiconductor element, a substrate or the like for use, the semiconductor element 3
Are transferred from the pocket 2 of the tray 1 as they are by a method such as suction and connected by a method such as wire bonding.
【0004】[0004]
【発明が解決しようとする課題】以上の構成の従来技術
によれば、回路形成面に半田等の突起で形成された電極
(以下半田バンプとする)を持つ半導体素子(以下半田
バンプ付き半導体素子とする)を扱う場合、半田パンプ
付き半導体素子は回路形成面を下にして半導体素子や基
板等に搭載するため、回路形成面を上にして搬送保管す
るトレイから移載するときに、一度機械等によって表裏
を反転させてやらねばならない。According to the prior art having the above-described structure, a semiconductor element (hereinafter referred to as a semiconductor element with a solder bump) having an electrode (hereinafter referred to as a solder bump) formed by a protrusion such as solder on a circuit formation surface is used. When mounting a semiconductor element with a solder pump on a semiconductor element or a substrate with the circuit forming surface facing down, the circuit forming surface should face up. You have to reverse the front and back depending on the situation.
【0005】また、予め回路形成面を下にして半田バン
プ付き半導体素子を切り出し、そのままトレイに移載す
れば半導体素子や基板等に搭載するときに反転させる必
要がないが、この場合、トレイのポケットの中では半田
バンプ付き半導体素子の半田バンプが下になってしま
い、搬送の際に傷がつくおそれがある。本発明は、以上
の問題点に鑑み、搬送保管時には半田バンプ付き半導体
素子の回路形成面が上になり、基板等への搭載時には半
田バンプ付き半導体素子の回路形成面がトレイのポケッ
ト内で既に下になった状態で整列して提供される構成を
得て、搬送保管性が高く、かつ搭載時の作業性を高める
トレイを提供することを目的とする。Also, if the semiconductor element with solder bumps is cut out in advance with the circuit forming surface facing down and transferred to the tray as it is, it is not necessary to reverse it when mounting it on a semiconductor element, a substrate, etc. In the pocket, the solder bumps of the semiconductor element with solder bumps are located underneath, which may cause scratches during transportation. In view of the above problems, the present invention has a circuit forming surface of a semiconductor element with solder bumps facing upward during transportation and storage, and a circuit forming surface of a semiconductor element with solder bumps is already in a tray pocket when mounted on a substrate or the like. An object of the present invention is to provide a tray that has a configuration that is aligned and provided in a downward state, has high transport and storage characteristics, and enhances workability during mounting.
【0006】[0006]
【課題を解決するための手段】上記目的を達成するた
め、本発明は、基板等への搭載時に収納された半田バン
プ付き半導体素子をトレイごと上下反転できるようにす
る。すなわち、本発明は、上面に半導体素子を収めるポ
ケットを有し、積層使用を想定した嵌合構造を有する半
導体素子の搬送及び保管用トレイにおいて、前記ポケッ
ト部分の丁度裏側に同一の縦横形状を持った裏ポケット
を有することを特徴とする。To achieve the above object, the present invention enables a semiconductor element with solder bumps, which is accommodated when it is mounted on a substrate or the like, to be turned upside down together with the tray. That is, the present invention has a pocket for accommodating semiconductor elements on the upper surface thereof, and in a tray for transporting and storing semiconductor elements having a fitting structure that is intended for stacked use, it has the same vertical and horizontal shapes just on the back side of the pocket portion. It is characterized by having a back pocket.
【0007】この場合、表裏両ポケットの深さが同一で
あり、その値は収納する半導体素子の厚み以内であり、
表裏両ポケットの深さを足した値が該半導体素子の厚み
以上とするか、もしくは、表裏いずれかのポケットの深
さを収納する半導体素子の厚み以上にし、他のポケット
の深さを該半導体素子の厚み以下とする。後者の場合、
表ポケットの深さを収納する半導体素子の厚み以上とす
る場合に限って、トレイとトレイの間に静電防止材や緩
衝材のシートを挟むことができる。In this case, the front and back pockets have the same depth, and the value is within the thickness of the semiconductor element to be housed.
The sum of the depths of the front and back pockets is equal to or greater than the thickness of the semiconductor element, or the depth of one of the front and back pockets is equal to or greater than the thickness of the semiconductor element, and the depths of the other pockets are equal to or greater than the semiconductor element. It should be less than the thickness of the element. In the latter case,
Only when the depth of the front pocket is equal to or larger than the thickness of the semiconductor element that houses the front pocket, a sheet of an antistatic material or a cushioning material can be sandwiched between the trays.
【0008】[0008]
【作用】以上の構成の本発明によれば、収納時には、表
ポケットの中に半導体素子を入れてトレイを重ねれば、
半導体素子の回路形成面が上の状態で搬送保管でき、基
板等への搭載時には全体を反転させた後トレイを外せ
ば、回路形成面がトレイのポケット内で既に下になった
状態で半導体素子を整列して提供することができる。し
たがって、この状態であれば、マウンター等の機械にそ
のまま投入しても機械の中で半田バンプ付き半導体素子
の反転等の作業をしないですむ。According to the present invention having the above-mentioned structure, at the time of storage, if the semiconductor elements are put in the front pockets and the trays are stacked,
The semiconductor element can be transported and stored with the circuit forming surface facing up. When mounting it on a substrate, etc., turn the whole over and remove the tray. Can be provided in line. Therefore, in this state, even if it is put into a machine such as a mounter as it is, it is not necessary to invert the semiconductor element with solder bumps in the machine.
【0009】[0009]
【実施例】以下に本発明の実施例を図面に従って説明す
る。図1は本発明の第1の実施例を示す側断面図であ
る。図1において、4はトレイであり、2aは該トレイ
の上面に設けた表ポケットであり、収納時には該表ポケ
ット2aの中に半導体素子3が収まる。このトレイ4は
積層使用を想定した嵌合構造を周囲に有する。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a side sectional view showing a first embodiment of the present invention. In FIG. 1, 4 is a tray, 2a is a front pocket provided on the upper surface of the tray, and the semiconductor element 3 is accommodated in the front pocket 2a during storage. The tray 4 has a fitting structure on the periphery that is intended for stacking.
【0010】2bは該表ポケット2aの丁度裏側に設け
た裏ポケットであり、該裏ポケット2bは前記表ポケッ
ト2aと同一の縦横形状を有する。図2は図1の要部拡
大側断面図である。ここで、表ポケット2aの深さをd
1、裏ポケット2bの深さをd2とし、半田バンプ付き
半導体素子3の厚みをhとする。A back pocket 2b is provided just on the back side of the front pocket 2a, and the back pocket 2b has the same vertical and horizontal shapes as the front pocket 2a. FIG. 2 is an enlarged side sectional view of a main part of FIG. Here, the depth of the front pocket 2a is d
1, the depth of the back pocket 2b is d2, and the thickness of the semiconductor element 3 with solder bumps is h.
【0011】本実施例において、前記表ポケット2aと
裏ポケット2bの2つのポケットの深さは同一である
(d1=d2)。また、トレイ4を重ねた場合に半田バ
ンプ付き半導体素子3が隣り合った上のトレイとぶつか
らないように、表ポケット2aの深さd1と裏ポケット
2bの深さd2を足した値は、半田バンプ付き半導体素
子3の厚みh以上とし(d1+d2>h)、その差は2
00μm程度が望ましい(d1+d2−h=200μ
m)。In this embodiment, the front pocket 2a and the back pocket 2b have the same depth (d1 = d2). Further, the value obtained by adding the depth d1 of the front pocket 2a and the depth d2 of the back pocket 2b is such that the semiconductor element 3 with solder bumps does not collide with the adjacent upper tray when the trays 4 are stacked. The thickness of the bumped semiconductor element 3 is equal to or larger than h (d1 + d2> h), and the difference is 2
About 00 μm is desirable (d1 + d2-h = 200 μm
m).
【0012】図3及び図4は本実施例の作用を示す側断
面図であり、図3はトレイ表側が上面にある状態=状態
1,図4はトレイ裏側が上面にある状態=状態2を示
す。上記構成の本実施例の作用を以下に説明する。ま
ず、回路形成面を上にして、半田バンプ付き半導体素子
3を切り出す。切り出された半田バンプ付き半導体素子
3は、吸引等の方法によりトレイ4の表ポケット2a上
に移載され、トレイ4の表ポケット2aが一杯になり次
第新たなトレイ4をその上に重ね、移載を続ける。搬送
・保管はこのトレイ4の状態(状態1:図3)で行うこ
ととする。次に、半田バンプ付き半導体素子3をチップ
マウンター等の機械に投入して使用する場合、重ねられ
たトレイ4をそのまま上下反転させ(状態2=図4)、
一番上にあるトレイ4を外し、半田バンプ付き半導体素
子3を回路形成面が下になった状態で使用する。このと
き半田バンプ付き半導体素子3は、状態1で天井であっ
た面を、状態2ではポケットの底面として使用すること
となる。FIGS. 3 and 4 are side sectional views showing the operation of this embodiment. FIG. 3 shows a state in which the tray front side is on the upper surface = state 1, and FIG. 4 shows a state in which the tray back side is on the upper surface = state 2. Show. The operation of this embodiment having the above configuration will be described below. First, the semiconductor element 3 with solder bumps is cut out with the circuit forming surface facing upward. The cut semiconductor element 3 with solder bumps is transferred onto the front pocket 2a of the tray 4 by a method such as suction, and when the front pocket 2a of the tray 4 becomes full, a new tray 4 is overlaid thereon and transferred. Continue to post. Transport and storage are performed in the state of the tray 4 (state 1: FIG. 3). Next, when the semiconductor element 3 with solder bumps is put into a machine such as a chip mounter for use, the stacked trays 4 are turned upside down as they are (state 2 = FIG. 4).
The tray 4 on the top is removed, and the semiconductor element 3 with solder bumps is used with the circuit forming surface facing down. At this time, in the semiconductor element 3 with solder bumps, the surface which was the ceiling in the state 1 is used as the bottom surface of the pocket in the state 2.
【0013】表裏両ポケットの深さは同一であるため、
搬送・保管に状態2、マウンターでの使用時に状態1で
使用しても機能に変わりはなく、何ら支障はない。ま
た、上述したごとく、表ポケット2aの深さd1+裏ポ
ケット2bの深さd2とhとの差は微細であるため、半
田バンプ付き半導体素子3は、自らが載っているトレイ
4と隣り合うトレイ4の両方のポケットの壁面が常に当
接に近い状態にあることになる。よってトレイ4を反転
させたときに、半田バンプ付き半導体素子3は隣り合う
トレイ4のポケットの壁面に強い力で衝突することな
く、円滑に隣り合うトレイ4のポケットに収めることが
できる。Since the front and back pockets have the same depth,
There is no problem even if you use it in state 2 for transportation and storage and state 1 when using it with a mounter, there is no change in function. Further, as described above, since the difference between the depth d1 of the front pocket 2a + the depth d2 of the back pocket 2b and h is minute, the semiconductor element 3 with solder bumps is adjacent to the tray 4 on which it is mounted. The wall surfaces of both pockets 4 are always in a state close to abutting. Therefore, when the trays 4 are inverted, the semiconductor elements 3 with solder bumps can be smoothly accommodated in the pockets of the adjacent trays 4 without colliding with the wall surfaces of the pockets of the adjacent trays 4 with a strong force.
【0014】図5は本発明の第2の実施例を示すトレイ
4の構造の側断面図、図6は図5の要部拡大側断面図で
ある。本実施例では、表ポケット2aの深さd1は半田
バンプ付き半導体素子3の厚みh以上になるようにし
(d1>h)、また、裏ポケット2bの深さd2は半田
バンプ付き半導体素子3の厚みh以上にならないように
する(d2>h)。FIG. 5 is a side sectional view of the structure of the tray 4 showing the second embodiment of the present invention, and FIG. 6 is an enlarged side sectional view of the essential parts of FIG. In the present embodiment, the depth d1 of the front pocket 2a is set to be equal to or larger than the thickness h of the semiconductor element 3 with solder bumps (d1> h), and the depth d2 of the back pocket 2b is equal to that of the semiconductor element 3 with solder bumps. Make sure that the thickness is not more than h (d2> h).
【0015】また、トレイ4を上下反転させても同じ機
能が得られるので、図5ではトレイ4の上面に存在する
表ポケット2aの方の深さd1を半田バンプ付き半導体
素子3の厚みh以上に変更したが、トレイ4の下面に存
在する裏ポケット2bの方の深さd2を半田バンプ付き
半導体素子3の厚み以上に変更してもよい。上記構成の
第2の実施例の作用は前述した第1の実施例のものと同
様である。Further, since the same function can be obtained even when the tray 4 is turned upside down, the depth d1 of the front pocket 2a existing on the upper surface of the tray 4 is not less than the thickness h of the semiconductor element 3 with solder bumps in FIG. However, the depth d2 of the back pocket 2b existing on the lower surface of the tray 4 may be changed to be equal to or larger than the thickness of the semiconductor element 3 with solder bumps. The operation of the second embodiment having the above configuration is the same as that of the first embodiment described above.
【0016】図7は本発明の第3の実施例を示す側面図
である。第3の実施例では、図5の構造、すなわち、表
ポケット2aの深さが半田バンプ付き半導体素子3の厚
みh以上である場合において、トレイ4とトレイ4の間
にフィルムや和紙等の静電防止材や緩衝材のシート5を
挟んだものである。なお、半田バンプ付き半導体素子を
チップマウンター等の機械に投入して使用する場合、前
記シート5は事前に外しておく。FIG. 7 is a side view showing a third embodiment of the present invention. In the third embodiment, when the structure of FIG. 5, that is, when the depth of the front pocket 2a is equal to or larger than the thickness h of the semiconductor element 3 with solder bumps, a static film such as a film or Japanese paper is provided between the trays 4. A sheet 5 of antistatic material or cushioning material is sandwiched. When the semiconductor element with solder bumps is put into a machine such as a chip mounter for use, the sheet 5 is removed beforehand.
【0017】以上の構成の第3の実施例によれば、半田
バンプ付き半導体素子3に対する保護機能がより高ま
る。上記各実施例においては、半導体素子の一つとして
半田バンプ付き半導体素子を想定したが、構造をそのま
まで全体的に大きくするだけで、BGA(BallGr
id Array)パッケージの搬送・保管にも適用可
能である。According to the third embodiment having the above construction, the function of protecting the semiconductor element 3 with solder bumps is further enhanced. In each of the above embodiments, a semiconductor element with solder bumps is assumed as one of the semiconductor elements, but the BGA (Ball Gr.
It can also be applied to the transportation and storage of id Array packages.
【0018】[0018]
【発明の効果】以上詳細に説明した如く、本発明によれ
ば、上面に半導体素子を収めるポケットを有し、積層使
用を想定した嵌合構造を有する半導体素子の搬送及び保
管用トレイにおいて、前記ポケット部分の丁度裏側に同
一の縦横形状を持った裏ポケットを有するので、基板等
への搭載時に収納された半田バンプ付き半導体素子をト
レイごと上下反転することができる。As described in detail above, according to the present invention, there is provided a tray for transporting and storing semiconductor elements, which has a pocket for accommodating semiconductor elements on its upper surface and has a fitting structure designed for stacking. Since the back pocket having the same vertical and horizontal shapes is provided just on the back side of the pocket portion, the semiconductor element with solder bumps stored at the time of mounting on a substrate or the like can be turned upside down together with the tray.
【0019】これにより、搬送保管時には半田バンプ付
き半導体素子の回路形成面が上になり、基板等への搭載
時には半田バンプ付き半導体素子の回路形成面がトレイ
のポケット内で既に下になった状態で整列して提供する
ことが可能となり、搬送保管性が高く、かつ搭載時の作
業性を高めるトレイを提供するという効果がある。As a result, the circuit forming surface of the semiconductor element with solder bumps is on the top during transport and storage, and the circuit forming surface of the semiconductor element with solder bumps is already on the bottom in the pocket of the tray when it is mounted on a substrate or the like. It is possible to provide the trays in line with each other, and it is possible to provide a tray that has a high transport and storage property and enhances the workability at the time of mounting.
【図1】本発明の第1の実施例を示す側断面図である。FIG. 1 is a side sectional view showing a first embodiment of the present invention.
【図2】図1の要部拡大側断面図である。FIG. 2 is an enlarged side sectional view of a main part of FIG.
【図3】本実施例の作用を示す側断面図である。FIG. 3 is a side sectional view showing the operation of the present embodiment.
【図4】本実施例の作用を示す側断面図である。FIG. 4 is a side sectional view showing the operation of the present embodiment.
【図5】本発明の第2の実施例を示す側断面図である。FIG. 5 is a side sectional view showing a second embodiment of the present invention.
【図6】図5の要部拡大側断面図である。6 is an enlarged side sectional view of a main part of FIG.
【図7】本発明の第3の実施例を示す側断面図である。FIG. 7 is a side sectional view showing a third embodiment of the present invention.
【図8】従来例を示側す断面図である。FIG. 8 is a sectional view showing a conventional example.
4 トレイ 2a 表ポケット 3b 裏ポケット 3 半導体素子 5 シート 4 Tray 2a Front pocket 3b Back pocket 3 Semiconductor element 5 Sheet
Claims (4)
し、積層使用を想定した嵌合構造を有する半導体素子の
搬送及び保管用トレイにおいて、 前記ポケット部分の丁度裏側に同一の縦横形状を持った
裏ポケットを有することを特徴とする半導体素子の搬送
及び保管用トレイ。1. A tray for transporting and storing semiconductor elements, which has a pocket for accommodating semiconductor elements on the upper surface and has a fitting structure for stacking, and has the same vertical and horizontal shapes just on the back side of the pocket portion. A tray for transporting and storing semiconductor devices, which has a back pocket.
の値は収納する半導体素子の厚み以内であり、表裏両ポ
ケットの深さを足した値が該半導体素子の厚み以上であ
ることを特徴とする請求項1項記載の半導体素子の搬送
及び保管用トレイ。2. The front and back pockets have the same depth, the value is within the thickness of the semiconductor element to be housed, and the value obtained by adding the depths of the front and back pockets is not less than the thickness of the semiconductor element. The tray for transporting and storing a semiconductor device according to claim 1, which is characterized in that.
る半導体素子の厚み以上にし、他のポケットの深さを該
半導体素子の厚み以下とすることを特徴とする請求項1
項記載の半導体素子の搬送及び保管用トレイ。3. The depth of one of the front and back pockets is set to be equal to or larger than the thickness of the semiconductor element to be accommodated, and the depth of the other pockets is set to be equal to or smaller than the thickness of the semiconductor element.
A tray for transporting and storing the semiconductor device according to the item.
の厚み以上とする場合、トレイとトレイの間に静電防止
材や緩衝材のシートを挟むことを特徴とする請求項3項
記載の半導体素子の搬送及び保管用トレイ。4. A sheet of an antistatic material or a cushioning material is sandwiched between the trays when the depth of the front pocket is equal to or larger than the thickness of the semiconductor element to be stored. Tray for transporting and storing semiconductor devices.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7044514A JPH08244877A (en) | 1995-03-03 | 1995-03-03 | Tray for transport and storage of semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7044514A JPH08244877A (en) | 1995-03-03 | 1995-03-03 | Tray for transport and storage of semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH08244877A true JPH08244877A (en) | 1996-09-24 |
Family
ID=12693664
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7044514A Pending JPH08244877A (en) | 1995-03-03 | 1995-03-03 | Tray for transport and storage of semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH08244877A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006341873A (en) * | 2005-06-08 | 2006-12-21 | Toshiba Corp | Tray for electronic component, and method of identifying similar tray for electronic component |
KR100721529B1 (en) * | 2006-12-13 | 2007-05-23 | 한미반도체 주식회사 | reversing apparatus for semiconductor package |
JP2009298446A (en) * | 2008-06-13 | 2009-12-24 | Daishinku Corp | Storage container for optical device |
JP2011155068A (en) * | 2010-01-26 | 2011-08-11 | Oki Semiconductor Co Ltd | Method of manufacturing semiconductor device, and substrate housing structure |
-
1995
- 1995-03-03 JP JP7044514A patent/JPH08244877A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006341873A (en) * | 2005-06-08 | 2006-12-21 | Toshiba Corp | Tray for electronic component, and method of identifying similar tray for electronic component |
KR100721529B1 (en) * | 2006-12-13 | 2007-05-23 | 한미반도체 주식회사 | reversing apparatus for semiconductor package |
JP2009298446A (en) * | 2008-06-13 | 2009-12-24 | Daishinku Corp | Storage container for optical device |
JP2011155068A (en) * | 2010-01-26 | 2011-08-11 | Oki Semiconductor Co Ltd | Method of manufacturing semiconductor device, and substrate housing structure |
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