JPH0824138B2 - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents
Semiconductor integrated circuit device and manufacturing method thereofInfo
- Publication number
- JPH0824138B2 JPH0824138B2 JP26144389A JP26144389A JPH0824138B2 JP H0824138 B2 JPH0824138 B2 JP H0824138B2 JP 26144389 A JP26144389 A JP 26144389A JP 26144389 A JP26144389 A JP 26144389A JP H0824138 B2 JPH0824138 B2 JP H0824138B2
- Authority
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- Japan
- Prior art keywords
- region
- metal
- resist
- etching
- integrated circuit
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Drying Of Semiconductors (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路装置およびその製造方法に関
し、特に半導体集積回路装置の金属配線の断面形状を最
適化できる半導体集積回路装置およびその製造方法に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same, and more particularly to a semiconductor integrated circuit device and a method for manufacturing the same that can optimize the cross-sectional shape of metal wiring of the semiconductor integrated circuit device. Regarding
従来、この種の半導体集積回路装置は、金属配線は所
望のレジストパターンをマスクに、等方性ウェットエッ
チングあるいは異方性ドライエッチングにより金属薄膜
（被エッチング膜）をエッチングして形成する。しかし
ながら、等方性ウェットエッチングの場合、金属膜厚分
以上のサイドエッチングが生じるため、微細な金属配線
形成には適さない問題がある。このため、ほぼ所望のレ
ジストパターン寸法通りに金属配線形成が可能なため、
微細な配線形成に適している異方性ドライエッチング技
術が使用される。Conventionally, in this kind of semiconductor integrated circuit device, metal wiring is formed by etching a metal thin film (film to be etched) by isotropic wet etching or anisotropic dry etching using a desired resist pattern as a mask. However, in the case of isotropic wet etching, there is a problem that it is not suitable for the formation of fine metal wiring because side etching more than the metal film thickness occurs. Therefore, since metal wiring can be formed almost according to the desired resist pattern size,
An anisotropic dry etching technique suitable for forming fine wiring is used.
上述した従来の半導体集積回路装置は、金属配線を異
方性ドライエッチング法で形成しても、LSIのパターン
によっては金属配線に細りが生じたり、また金属配線端
部が垂直な形状ゆえにパシベーション膜が充分被着せ
ず、金属配線端部のパシベーション膜質が平坦部に比
べ、悪いという問題が生じる。In the conventional semiconductor integrated circuit device described above, even if the metal wiring is formed by the anisotropic dry etching method, the metal wiring may be thinned depending on the LSI pattern, and the passivation film may be formed because the metal wiring end portion is vertical. Does not adhere sufficiently, and the quality of the passivation film at the end of the metal wiring is worse than that of the flat portion.
上述した異方性ドライエッチングにおける金属配線形
成の問題についてさらに具体的に述べる。The problem of metal wiring formation in the above-mentioned anisotropic dry etching will be described more specifically.
LSIのパターンによっては金属配線に細り（サイドエ
ッチング）が生じる、すなわちパターン依存性の問題は
次のような理由による。例えばアルミをレジストをマス
クに塩素を主体としたガスを用いてエッチングする場
合、ClラジカルやCl2分子はアルミおよびレジストを同
時にエッチングする。レジストはアルミの側壁に付着
し、側壁保護膜として働くためエッチングは厚さ方向の
み進行し、横方向には進まないので異方性エッチングが
可能となっている。Depending on the LSI pattern, the metal wiring is thinned (side etching), that is, the problem of pattern dependence is as follows. For example, when aluminum is etched using a resist as a mask and a gas mainly containing chlorine, Cl radicals and Cl 2 molecules simultaneously etch aluminum and the resist. Since the resist adheres to the side wall of aluminum and acts as a side wall protective film, the etching progresses only in the thickness direction and does not proceed in the lateral direction, so that anisotropic etching is possible.
LSIのパターンによってLSIパターン全体において、金
属配線の占める割合いが多いものもあれば少ないものも
あるが、金属配線が少ない場合すなわちマスクとなるレ
ジストが少ない場合、エッチング時の側壁保護膜が少な
いため結果として異方性エッチングが成り立たず、金属
配線に細り（サイドエッチング）が生ずる問題が発生す
る。Depending on the LSI pattern, the metal wiring may occupy a large percentage or a small percentage of the entire LSI pattern, but if the metal wiring is small, that is, the resist used as a mask is small, the sidewall protection film during etching is small. As a result, anisotropic etching does not work, and there arises a problem that the metal wiring is thinned (side etching).
次に、金属配線端部のパシベーション膜質悪化の問題
であるが具体的にどのような不具合いが生じるか第３図
（ａ）〜（ｄ）を用いて説明する。Next, the problem of deterioration of the quality of the passivation film at the end of the metal wiring will be specifically described with reference to FIGS. 3 (a) to 3 (d).
第３図（ａ）は、半導体基板１上に酸化膜２を形成
し、その上にボンディング引き出し用の金属電極パッド
３を形成し、さらにパシベーション膜として例えばCVD
酸化膜４およびプラズマ窒化膜５を形成したものであ
る。前記金属電極パッド３はLSIの内部配線と同時形成
しているため側壁は垂直で、その領域６のパシベーショ
ン膜4,5はカバレッジが悪く、また平坦部に比べて膜厚
も薄い。In FIG. 3A, an oxide film 2 is formed on a semiconductor substrate 1, a metal electrode pad 3 for drawing out a bonding is formed on the oxide film 2, and a passivation film such as a CVD film is formed.
The oxide film 4 and the plasma nitride film 5 are formed. Since the metal electrode pads 3 are formed simultaneously with the internal wiring of the LSI, the side walls are vertical, the passivation films 4 and 5 in the region 6 have poor coverage, and the film thickness is smaller than that of the flat portion.
第３図（ｂ）は、ボンディング引き出し用のパッドを
開口するため、レジスト７をパターニングしたものであ
る。In FIG. 3B, the resist 7 is patterned in order to open the pad for drawing out the bonding.
第３図（ｃ）は、前記レジスト７をマスクにパッド開
口部８のプラズマ窒化膜５を等方性ドライエッチング
で、さらにCVD酸化膜４をフッ酸系のウェットエッチン
グでそれぞれエッチングしたものである。ところでプラ
ズマ窒化膜５を等方性ドライエッチングしている際に、
レジスト７とプラズマ窒化膜５の間９の密着性が弱くな
り、次のCVD酸化膜４をウェットエッチングしている時
に、エッチング液がレジスト７とプラズマ窒化膜５の間
９に浸み込み、金属側壁部６に達したエッチング液は、
従来エッチングされにくいプラズマ窒化膜５の膜質の悪
くなった側壁部をエッチングし、さらに下地のCVD酸化
膜４をエッチングする危険がある。FIG. 3C shows that the plasma nitride film 5 in the pad opening 8 is etched by isotropic dry etching and the CVD oxide film 4 is etched by hydrofluoric acid-based wet etching using the resist 7 as a mask. . By the way, during the isotropic dry etching of the plasma nitride film 5,
The adhesion between the resist 7 and the plasma nitride film 5 is weakened, and during the next wet etching of the CVD oxide film 4, the etching solution penetrates into the space between the resist 7 and the plasma nitride film 5, and metal The etching liquid that has reached the side wall portion 6 is
There is a risk of etching the side wall portion of the plasma nitride film 5 which is difficult to be etched conventionally, which has deteriorated in film quality, and further etching the underlying CVD oxide film 4.
第３図（ｄ）はパッド開口を終了し、レジスト７を除
去したのちの金属側壁部のパシベーション膜がエッチン
グされた様子を示すもので、パシベーション効果のなく
なった金属電極パッド側壁部からの水および不純物の侵
入によりLSIの信頼性を劣化させる問題が生じる。FIG. 3D shows a state in which the passivation film on the metal side wall portion is etched after the pad opening is completed and the resist 7 is removed. Water from the side wall portion of the metal electrode pad where the passivation effect is lost and Intrusion of impurities causes a problem of degrading the reliability of LSI.
本発明の第１の発明である半導体集積回路装置の製造
方法は、半導体集積回路装置の内部領域の金属配線およ
び周辺領域の金属パッドを形成するにあたり、パッド領
域をふくむその周辺の金属をレジストでマスクし、内部
領域の金属配線を異方性エッチングで形成する工程と、
内部領域をレジストでマスクし金属パッドを等方性エッ
チングで形成する工程とを含むことを特徴とする。In the method for manufacturing a semiconductor integrated circuit device according to the first aspect of the present invention, when forming the metal wiring in the internal region of the semiconductor integrated circuit device and the metal pad in the peripheral region, the metal around the region including the pad region is resisted. Masking and forming metal wiring in the inner region by anisotropic etching,
And masking the inner region with a resist to form the metal pad by isotropic etching.
また、本発明の第２の発明である半導体集積回路装置
は、半導体集積回路装置の内部領域の金属配線端部の断
面形状は垂直な形状を有し、周辺領域のボンディング引
き出し部の金属パッド領域の断面形状はなめらかな順テ
ーパーの形状を有することを特徴とする。In the semiconductor integrated circuit device according to the second aspect of the present invention, the cross-sectional shape of the metal wiring end portion in the internal region of the semiconductor integrated circuit device is vertical, and the metal pad region of the bonding lead-out portion in the peripheral region is formed. Is characterized by having a smooth forward taper shape.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図（ａ）乃至（ｂ）は本発明第１の発明の一実施
例であるMPU（microprocessing unit）LSI11の金属配線
パターンの形成法を示す工程順の平面図である。1 (a) and 1 (b) are plan views in order of steps showing a method for forming a metal wiring pattern of an MPU (microprocessing unit) LSI 11 which is an embodiment of the first invention of the present invention.
第１図（ａ）は半導体基板１上に複数の素子が形成さ
れ、各素子を結線するため全面にアルミを膜厚1.1μｍ
ほどスパッタ法にて成膜し、周知のフォトリソグラフィ
技術によりレジストにて所望のパターニングを形成した
ものである。ここで将来ボンディング引き出し用の金属
電極パッドとなる領域およびその周辺のできるかぎり大
きな面積の領域12（第１図（ａ）の斜線部）はレジスト
で覆い、LSIの内部素子領域13は微細なパターニングが
形成されている。ここで言うLSIの内部素子領域13と
は、斜線領域12の内部をさし、ROM,RAM,CPU等のブロッ
ク内のパターニングは図面上省略されている。In FIG. 1 (a), a plurality of elements are formed on the semiconductor substrate 1, and aluminum is formed on the entire surface in a film thickness of 1.1 μm to connect the elements.
A film is formed by a sputtering method, and desired patterning is formed by a resist by a well-known photolithography technique. Here, a region 12 which will be a metal electrode pad for drawing out a bonding in the future and a region 12 (a hatched portion in FIG. 1A) having the largest possible area around the region are covered with a resist, and the internal element region 13 of the LSI is finely patterned. Are formed. The internal element area 13 of the LSI mentioned here refers to the inside of the hatched area 12, and patterning in blocks such as ROM, RAM, and CPU is omitted in the drawing.
次に上記レジストをマスクに例えば塩素を主体とした
ガスでアルミを異方性ドライエッチングを行なう。Next, using the resist as a mask, anisotropic dry etching of aluminum is performed with a gas mainly containing chlorine.
この時アルミ側壁保護膜となるレジストはLSI周辺領
域12に充分存在するので、LSIの内部素子の微細なアル
ミ配線におけるサイドエッチングは抑制される。At this time, since the resist serving as the aluminum side wall protective film is sufficiently present in the LSI peripheral region 12, side etching in the fine aluminum wiring of the internal elements of the LSI is suppressed.
第１図（ｂ）は上記アルミドライエッチング時に使用
したレジストを除去したのち、再び周知のフォトリソグ
ラフィ技術により、LSIの内部素子領域13（第１図
（ｂ）の斜線領域）およびアルミ電極パッド14（第１図
（ｂ）の斜線部）を新たにレジストで覆う。In FIG. 1B, after removing the resist used in the aluminum dry etching, the internal element region 13 of the LSI (hatched region in FIG. 1B) and the aluminum electrode pad 14 are again formed by the well-known photolithography technique. (The shaded area in FIG. 1B) is newly covered with resist.
次に上記レジストをマスクに例えばリン酸系のエッチ
ング液でアルミの等方性ウェットエッチングを行なう。
つまり金属電極パッド14周囲の端部をなめらかに順テー
パーの形状にする。アルミのエッチングが完了したの
ち、上記レジストを除去し、パシベーション膜を形成
し、ボンディング引き出し用のパッド開口を行ない、LS
Iの拡散製造が完了する。Next, using the resist as a mask, isotropic wet etching of aluminum is performed with a phosphoric acid-based etching solution, for example.
That is, the end portion around the metal electrode pad 14 is formed into a smoothly forward tapered shape. After the aluminum etching is completed, the above resist is removed, a passivation film is formed, and a pad opening for bonding extraction is made.
Diffusion manufacturing of I is completed.
第２図（ａ）は本発明の第２の発明の一実施例である
MPU LSIの部分平面図である。LSIの内部素子領域のア
ルミ配線は異方性エッチングで行ない、LSI外周のアル
ミ電極パッドは等方性エッチングで行なうが、そのつな
ぎ目がＡ−Ａ′線である。フォトリソグラフィの露光時
の目ズレおよび等方性エッチング時のサイドエッチング
の影響をなくすため、つなぎ目（Ａ−Ａ′）方向のアル
ミ幅は充分な距離をとっている。FIG. 2 (a) shows an embodiment of the second invention of the present invention.
It is a partial top view of MPU LSI. The aluminum wiring in the internal element region of the LSI is anisotropically etched and the aluminum electrode pads on the outer periphery of the LSI are isotropically etched, and the joint is the AA 'line. The aluminum width in the joint (AA ') direction has a sufficient distance in order to eliminate the effects of misalignment during photolithography exposure and side etching during isotropic etching.
第２図（ｂ）は第２図（ａ）における異方性エッチン
グで形成したアルミ配線15のＢ−Ｂ′断面図である。配
線15上に例えばパシベーション膜として低濃度のリンシ
リケートガラス（PSG）のCVD膜４を0.7μｍおよびプラ
ズマCVD法による窒化膜５を0.5μｍを成長させたもので
ある。2B is a sectional view of the aluminum wiring 15 formed by anisotropic etching in FIG. 2A, taken along the line BB ′. For example, a low concentration phosphorous silicate glass (PSG) CVD film 4 having a thickness of 0.7 μm and a nitride film 5 formed by a plasma CVD method having a thickness of 0.5 μm are grown on the wiring 15 as a passivation film.
第２図（ｃ）は第２図（ａ）における等方性エッチン
グで形成したアルミ電極パッド14のＣ−Ｃ′線断面図で
ある。第２図（ｂ）と同様のパシベーション膜が形成さ
れている。等方性エッチングで形成されたアルミ電極パ
ッドの端部はなめらかな順テーパーの形状であるためパ
シベーション膜のカバレッジは良好であり、また膜質の
劣化は少ない。次工程で、ボンディング引き出し用のパ
ッド開口を行なうため、レジスト７をパターニングし、
前記レジスト７をマスクに、パッド開口部16のプラズマ
窒化膜５およびPSG膜４をそれぞれエッチングする本実
施例では上述した配線断面形状をとることにより、上記
エッチング時にレジスト７とプラズマ窒化膜５の間にエ
ッチング液が浸み込み金属電極パッド端部のパシベーシ
ョン膜をエッチングする従来見られた不具合いは、パシ
ベーション膜のカバレッジ改善により発生しなくなり、
信頼性の優れた金属電極パッドを形成できる。FIG. 2C is a sectional view taken along line CC ′ of the aluminum electrode pad 14 formed by the isotropic etching in FIG. A passivation film similar to that shown in FIG. 2B is formed. Since the end portion of the aluminum electrode pad formed by isotropic etching has a smooth forward taper shape, the coverage of the passivation film is good and the film quality is not significantly deteriorated. In the next step, the resist 7 is patterned to form a pad opening for drawing out the bonding,
In the present embodiment, the plasma nitride film 5 and the PSG film 4 in the pad opening 16 are respectively etched using the resist 7 as a mask. In this embodiment, the wiring cross-sectional shape described above is used, so that the space between the resist 7 and the plasma nitride film 5 is increased during the etching. The problem that has been seen in the past in which the etching solution penetrates into and etches the passivation film at the end of the metal electrode pad does not occur due to improved coverage of the passivation film,
A highly reliable metal electrode pad can be formed.
以上説明したように本発明は、LSI内部の微細な金属
配線を形成する際、金属電極パッド部を含むその周辺の
できるかぎり大きな面積の領域をレジストで残すことで
異方性ドライエッチング時に生じる金属配線の細りを抑
制できる。また次にLSI内部領域をレジストでマスクし
ながら、金属電極パッドを等方性ウェットエッチングに
より形成することで、パシベーション膜のカバレッジを
改善し、従来パッド開口時に生じた金属電極パッド端部
におけるパシベーション膜のエッチング問題を解決する
ことができ、信頼性の高いLSIが製造できる効果があ
る。As described above, according to the present invention, when forming fine metal wiring inside an LSI, a metal that occurs during anisotropic dry etching is left by leaving a region having the largest possible area including the metal electrode pad portion around the resist. Wiring thinness can be suppressed. Next, while masking the internal area of the LSI with a resist, the metal electrode pad is formed by isotropic wet etching to improve the coverage of the passivation film, and the passivation film at the edge of the metal electrode pad generated when the conventional pad was opened. It is possible to solve the etching problem described above, and it is possible to manufacture a highly reliable LSI.
第１図（ａ）乃至（ｂ）は本発明の第１の発明の一実施
例を示す工程順の平面図、第２図（ａ）は本発明の第２
の発明の一実施例の部分平面図、第２図（ｂ），（ｃ）
はそれぞれ第２図（ａ）のＢ−Ｂ′線およびＣ−Ｃ′線
の断面図、第３図（ａ）〜（ｄ）は従来装置の製造方法
を示す断面図である。 １……半導体基板、２……酸化膜、3,14……金属電極パ
ッド、４……CVD酸化膜、５……プラズマ窒化膜、６…
…金属側壁部、７……レジスト、8,16……パッド開口
部、９……レジストとプラズマ窒化膜の境界、10……フ
ッ酸でエッチングされたCVD酸化膜部、11……MPULSI、1
2……LSI周辺領域、13……LSI内部領域、15……金属配
線。1 (a) and 1 (b) are plan views in order of steps showing one embodiment of the first invention of the present invention, and FIG. 2 (a) is a second view of the present invention.
2 is a partial plan view of an embodiment of the invention of FIG.
Is a sectional view taken along the line BB 'and line CC' in FIG. 2 (a), and FIGS. 3 (a) to 3 (d) are sectional views showing a method for manufacturing a conventional device. 1 ... Semiconductor substrate, 2 ... Oxide film, 3,14 ... Metal electrode pad, 4 ... CVD oxide film, 5 ... Plasma nitride film, 6 ...
… Metal side wall, 7 …… resist, 8,16 …… pad opening, 9 …… between resist and plasma nitride film, 10 …… CVD oxide film etched with hydrofluoric acid, 11 …… MPULSI, 1
2 …… LSI peripheral area, 13 …… LSI internal area, 15 …… metal wiring.
Claims (2)
および周辺領域の金属パッドを形成するにあたり、パッ
ド領域を含むその周辺の金属をレジストでマスクし内部
領域の金属配線を異方性エッチングで形成する工程と、
内部領域をレジストでマスクし金属パッドを等方性エッ
チングで形成する工程とを含むことを特徴とする半導体
集積回路装置の製造方法。1. When forming a metal wiring in an internal region and a metal pad in a peripheral region of a semiconductor integrated circuit device, the metal around the pad region including the pad region is masked with a resist and the metal wiring in the internal region is anisotropically etched. Forming process,
And a step of forming a metal pad by isotropic etching while masking an inner region with a resist.
端部の断面形状は垂直な形状を有し、周辺領域のボンデ
ィング引き出し部の金属パッド領域の断面形状はなめら
かな順テーパーの形状を有することを特徴とする半導体
集積回路装置。2. A cross-sectional shape of an end portion of a metal wiring in an inner region of a semiconductor integrated circuit device has a vertical shape, and a cross-sectional shape of a metal pad region of a bonding lead-out portion in a peripheral region has a smooth forward taper shape. A semiconductor integrated circuit device characterized by the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26144389A JPH0824138B2 (en) | 1989-10-05 | 1989-10-05 | Semiconductor integrated circuit device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26144389A JPH0824138B2 (en) | 1989-10-05 | 1989-10-05 | Semiconductor integrated circuit device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03123041A JPH03123041A (en) | 1991-05-24 |
| JPH0824138B2 true JPH0824138B2 (en) | 1996-03-06 |
Family
ID=17361967
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26144389A Expired - Fee Related JPH0824138B2 (en) | 1989-10-05 | 1989-10-05 | Semiconductor integrated circuit device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0824138B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100420126B1 (en) * | 2002-01-28 | 2004-03-02 | 삼성전자주식회사 | Patterning Method For Fabrication Of Semiconductor Device |
-
1989
- 1989-10-05 JP JP26144389A patent/JPH0824138B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03123041A (en) | 1991-05-24 |
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