JPH056891A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve coverage ratio of wiring metal even if an aspect ratio of a hole is large by previously forming a stopper film at a position for surrounding a hole near a bottom of a hole to be formed and forming a sidewall on its inner wall. CONSTITUTION:A polysilicon film 2 is deposited on a silicon substrate 1, and patterned to form a polysilicon film pattern (stopper film). Then, after an SiO2 film is deposited, it is coated with SOG to flatten the surface. A resist pattern is formed on an insulator layer 4, and with it as a mask it is isotropically etched until it reaches the surface of a stopper 2. Then, the region of the layer 4 to be surrounded by the stopper 2 is reactive ion etched until the surface of the substrate 1 is exposed to form a sidewall 3 on the inner wall of the stopper 2. Thus, generation of a wiring metal thin layer on a tapered surface is prevented, and wiring metal 5 deposited in the hole 6 becomes substantially uniform to improve its coverage ratio.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improving the coverage ratio of wiring metal in through holes or contact holes.

With the recent trend toward miniaturization and high integration of semiconductor devices, through holes or contact holes (hereinafter simply referred to as holes) are miniaturized, and therefore metal wiring is required to have high reliability. Is coming. Therefore, in the hall, a high coverage ratio of the wiring metal is indispensable.

[0003]

2. Description of the Related Art Generally, the coverage rate in a hall is
Ratio (b / a) of the thickness of the metal layer deposited on the side wall inside the hole (b) to the thickness of the metal layer deposited on the peripheral surface outside the hole (a)
It is represented by and is a value smaller than 1. If the thickness of the metal layer deposited on the side wall in the hole is not uniform, b is set to the minimum thickness.

Conventionally, in order to improve the coverage ratio (to approach 1), a tapered portion is provided on the side wall of the hole to form a mortar-shaped hole. Figure
FIG. 4 (a) is a diagram schematically showing an example of a conventional metal wiring provided in a hole. In the figure, 21 is a substrate, 24 is an insulating film layer, 25 is a wiring metal, and 26 is an opening on the substrate surface. In the figure, first, on the insulating layer 24, the opening
After forming a mask layer (not shown) having 26, the insulating layer 24 is isotropically etched halfway through the mask layer, and then the remaining insulating layer 24 is anisotropically etched using the same mask. To form a contact hole. Next, wiring metal is deposited on the bottom and side surfaces of the contact hole and the tapered surface of the mortar.

[0005]

[Problems to be Solved by the Invention] However, recent LSI, VLS
In I, not only the hole diameter is becoming finer, but the aspect ratio (ratio between the hole depth and the hole diameter) is also increasing. When the aspect ratio is large, as shown in Fig. 4 (b), a thin layer of wiring metal is generated at the corner at the bottom of the hole, and as a result, a thin layer of wiring metal is easily generated even on the tapered surface. Poor contact of wiring, and even disconnection may occur. .. Therefore, it is almost difficult to improve the coverage rate simply by providing the tapered portion on the side wall of the hole as before.

Therefore, it is an object of the present invention to provide a method capable of improving the coverage ratio of wiring metal even when the aspect ratio of holes is large.

[0007]

[Means for Solving the Problems] The above-mentioned problems include the step of forming a stopper film in advance in the vicinity of the bottom of a hole to be formed so as to surround the hole, and the step of forming a sidewall on the inner wall of the stopper. Is solved by a method for forming a wiring metal having.

FIG. 1 is a diagram illustrating the principle of the present invention. In the figure, 2 is a stopper provided on the semiconductor substrate 1, 3
Is the side wall on the inner wall of stopper 2, 4
Is an insulating film that covers the stopper 2 and has an opening for the hole 6, and 5 is a wiring metal that is formed so as to cover the hole 6.

[0009]

[Function] In FIG. 1, since the stopper film 2 is present, only the isotropic etching of the insulating film 4 is performed, and the hole 6
It is possible to concentrically form a mortar having a tapered surface. Furthermore, by forming a sidewall on the inner wall of the stopper film 2 to cover the side wall of the stopper film 2 perpendicular to the Si substrate 1, and smoothing the shape of the peripheral portion of the bottom of the hole 6, the corner at the bottom of the hole is smoothed. Of the wiring metal thin layer portion is prevented. As a result, the formation of a thin wiring metal layer on the tapered surface is prevented, the wiring metal is deposited in the holes 6 substantially uniformly, and the coverage ratio is improved.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. Figures 2 and 3 show a typical MOSF of this embodiment.
It is a figure explaining each step in metal wiring manufacture of a hole in an ET manufacturing process.

First, as shown in FIG. 2 (a), silicon
A 100-200 nm-thick poly-Si film 2 is deposited on a (Si) substrate 1, and patterning is performed corresponding to the position of the hole 6 with a size of about 1 μm to form a poly-Si film pattern.
Form two. This poly-Si film pattern 2 will later become the etching stopper film 2.

Next, as shown in FIG. 2 (b), a Si substrate
1 Fill the exposed part of the surface, and
After depositing a silicon dioxide (SiO ₂ ) film 4'with a thickness of about 100 to 200 nm covering the entire surface of the substrate, spin-on-glass (SOG) 4 ''
Is applied to the entire surface to flatten the surface. That is, the poly-Si film pattern 2 has a form in which it is embedded by an insulator layer 4 having a thickness of about 500 nm, which is composed of a silicon dioxide (SiO ₂ ) film 4 ′ and spin-on-glass (SOG) 4 ″. It is also possible to use phosphosilicate glass (PSG) instead of silicon dioxide (SiO ₂ ).

Next, as shown in FIG. 2 (c), an insulating layer
A resist film is formed on 4 and patterned corresponding to the position of poly-Si film pattern 2 to form a resist pattern.
Form 7.

Next, as shown in FIG. 3D, with the resist pattern 7 as a mask, the insulating layer 4 is isotropically etched until the surface of the stopper 2 is reached. For etching, stopper 2 poly-Si, such as hydrofluoric acid solution, is used.
Wet etching with a solution having a selectivity between the film and the insulating layer 4 is used.

Next, as shown in FIG. 3 (e), using the resist pattern 7 as a mask, the region of the insulator layer 4 surrounded by the stopper 2 is subjected to reactive ion etching until the surface of the Si substrate 1 is exposed. (RIE) For the RIE, the stopper 2 poly-Si film and insulating layer, such as Freon gas, are used.
A gas having a selectivity with 4 is used.

In this step, the sidewall 3 is formed on the inner wall of the stopper 2. Finally, as shown in Fig. 3 (f), aluminum (Al) is
The wiring metal is deposited to complete the wiring process for the holes.

[0017]

As described above, according to the present invention, the coverage ratio of the wiring metal for the holes having a large aspect ratio is remarkably improved as compared with the conventional one, and as a result, the yield of LSI and VLSI manufacturing and the reliability can be remarkably improved. ..

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention (No. 1).

FIG. 3 is a diagram showing an embodiment of the present invention (No. 2)

FIG. 4 is an explanatory diagram of a conventional example.

[Explanation of symbols]

1, 21 Si substrate 2 Stopper film 3 Sidewall 4, 24 Insulating film layer 4'SiO ₂ film 4 '' SOG film 5, 25 Wiring metal 6, 26 Contact hole opening 7 Resist pattern

Claims (1)

Claim: What is claimed is: 1. A step of forming a first insulating film having a first opening on a substrate, and a step of forming a first insulating film including the first opening on the substrate. Forming a second insulating film different from that on the second insulating film and flattening the surface, and forming a second opening on the second insulating film at a position corresponding to the first opening. A step of forming a mask layer having the same, a step of isotropically etching the second insulating film using the mask layer as a mask, and etching to the surface of the first insulating film; and using the mask layer as a mask, A step of anisotropically etching the second insulating film layer embedded in the first opening to form a sidewall on the side wall of the first insulating film layer; It has a step of forming a wiring layer on the contact hole formed by The method of manufacturing a semiconductor device according to.