JPH0823818B2 - 命令群用マイクロコード生成装置及びコンピュータにおける組合せ装置 - Google Patents

命令群用マイクロコード生成装置及びコンピュータにおける組合せ装置

Info

Publication number
JPH0823818B2
JPH0823818B2 JP4001067A JP106792A JPH0823818B2 JP H0823818 B2 JPH0823818 B2 JP H0823818B2 JP 4001067 A JP4001067 A JP 4001067A JP 106792 A JP106792 A JP 106792A JP H0823818 B2 JPH0823818 B2 JP H0823818B2
Authority
JP
Japan
Prior art keywords
microinstructions
instruction
sequence
microinstruction
instructions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP4001067A
Other languages
English (en)
Japanese (ja)
Other versions
JPH04309131A (ja
Inventor
エル． ジェレマイア トーマス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPH04309131A publication Critical patent/JPH04309131A/ja
Publication of JPH0823818B2 publication Critical patent/JPH0823818B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/28—Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
JP4001067A 1991-02-08 1992-01-07 命令群用マイクロコード生成装置及びコンピュータにおける組合せ装置 Expired - Lifetime JPH0823818B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US65300691A 1991-02-08 1991-02-08
US653006 1991-02-08

Publications (2)

Publication Number Publication Date
JPH04309131A JPH04309131A (ja) 1992-10-30
JPH0823818B2 true JPH0823818B2 (ja) 1996-03-06

Family

ID=24619111

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4001067A Expired - Lifetime JPH0823818B2 (ja) 1991-02-08 1992-01-07 命令群用マイクロコード生成装置及びコンピュータにおける組合せ装置

Country Status (3)

Country Link
US (1) US5398321A (enExample)
EP (1) EP0498067A2 (enExample)
JP (1) JPH0823818B2 (enExample)

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JPH04143819A (ja) 1989-12-15 1992-05-18 Hitachi Ltd 消費電力制御方法、半導体集積回路装置およびマイクロプロセツサ
US5787303A (en) * 1991-10-31 1998-07-28 Kabushiki Kaisha Toshiba Digital computer system capable of processing a plurality of instructions in parallel based on a VLIW architecture
US6154828A (en) * 1993-06-03 2000-11-28 Compaq Computer Corporation Method and apparatus for employing a cycle bit parallel executing instructions
EP1186995B1 (en) * 1993-11-05 2003-09-03 Intergraph Corporation Instruction memory with associative cross-bar switch
US5509129A (en) * 1993-11-30 1996-04-16 Guttag; Karl M. Long instruction word controlling plural independent processor operations
JP3212213B2 (ja) * 1994-03-16 2001-09-25 株式会社日立製作所 データ処理装置
US5598546A (en) * 1994-08-31 1997-01-28 Exponential Technology, Inc. Dual-architecture super-scalar pipeline
FR2731094B1 (fr) * 1995-02-23 1997-04-30 Dufal Frederic Procede et dispositif de commande simultanee des etats de controle des unites d'execution d'un processeur programmable
US5924128A (en) * 1996-06-20 1999-07-13 International Business Machines Corporation Pseudo zero cycle address generator and fast memory access
US5923862A (en) * 1997-01-28 1999-07-13 Samsung Electronics Co., Ltd. Processor that decodes a multi-cycle instruction into single-cycle micro-instructions and schedules execution of the micro-instructions
US6047368A (en) * 1997-03-31 2000-04-04 Sun Microsystems, Inc. Processor architecture including grouping circuit
US6314493B1 (en) 1998-02-03 2001-11-06 International Business Machines Corporation Branch history cache
EP0992893B1 (en) * 1998-10-06 2008-12-31 Texas Instruments Inc. Verifying instruction parallelism
US6681319B1 (en) 1998-10-06 2004-01-20 Texas Instruments Incorporated Dual access instruction and compound memory access instruction with compatible address fields
US6742110B2 (en) 1998-10-06 2004-05-25 Texas Instruments Incorporated Preventing the execution of a set of instructions in parallel based on an indication that the instructions were erroneously pre-coded for parallel execution
EP0992892B1 (en) * 1998-10-06 2015-12-02 Texas Instruments Inc. Compound memory access instructions
US6453407B1 (en) * 1999-02-10 2002-09-17 Infineon Technologies Ag Configurable long instruction word architecture and instruction set
US6530077B1 (en) * 1999-09-15 2003-03-04 Powerquest Corporation Device and method for releasing an in-memory executable image from its dependence on a backing store
US7098921B2 (en) * 2001-02-09 2006-08-29 Activision Publishing, Inc. Method, system and computer program product for efficiently utilizing limited resources in a graphics device
US7047395B2 (en) * 2001-11-13 2006-05-16 Intel Corporation Reordering serial data in a system with parallel processing flows
US7451294B2 (en) * 2003-07-30 2008-11-11 Intel Corporation Apparatus and method for two micro-operation flow using source override
US9542192B1 (en) * 2008-08-15 2017-01-10 Nvidia Corporation Tokenized streams for concurrent execution between asymmetric multiprocessors
JP5311491B2 (ja) 2009-11-17 2013-10-09 Ｎｅｃシステムテクノロジー株式会社 グラフィクス頂点処理装置およびグラフィクス頂点処理方法
GB2516864A (en) * 2013-08-02 2015-02-11 Ibm Increased instruction issue rate and latency reduction for out-of-order processing by instruction chaining and collision avoidance
US11042929B2 (en) 2014-09-09 2021-06-22 Oracle Financial Services Software Limited Generating instruction sets implementing business rules designed to update business objects of financial applications

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US4295193A (en) * 1979-06-29 1981-10-13 International Business Machines Corporation Machine for multiple instruction execution
DE3009121C2 (de) * 1980-03-10 1982-02-18 Siemens AG, 1000 Berlin und 8000 München Mikroprogramm-Steuereinrichtung
US4376976A (en) * 1980-07-31 1983-03-15 Sperry Corporation Overlapped macro instruction control system
US4439828A (en) * 1981-07-27 1984-03-27 International Business Machines Corp. Instruction substitution mechanism in an instruction handling unit of a data processing system
US4594655A (en) * 1983-03-14 1986-06-10 International Business Machines Corporation (k)-Instructions-at-a-time pipelined processor for parallel execution of inherently sequential instructions
US4967343A (en) * 1983-05-18 1990-10-30 International Business Machines Corp. Pipelined parallel vector processor including parallel configured element processors for processing vector elements in parallel fashion
US4825363A (en) * 1984-12-05 1989-04-25 Honeywell Inc. Apparatus for modifying microinstructions of a microprogrammed processor
DE3751503T2 (de) * 1986-03-26 1996-05-09 Hitachi Ltd Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen.
US5051940A (en) * 1990-04-04 1991-09-24 International Business Machines Corporation Data dependency collapsing hardware apparatus
JPH0765101B2 (ja) * 1986-09-21 1995-07-12 東洋ラジエーター株式会社 チューブのアニール処理方法
JPS63131230A (ja) * 1986-11-21 1988-06-03 Hitachi Ltd 情報処理装置
US5005118A (en) * 1987-04-10 1991-04-02 Tandem Computers Incorporated Method and apparatus for modifying micro-instructions using a macro-instruction pipeline
US5155819A (en) * 1987-11-03 1992-10-13 Lsi Logic Corporation Flexible ASIC microcomputer permitting the modular modification of dedicated functions and macroinstructions
GB8817911D0 (en) * 1988-07-27 1988-09-01 Int Computers Ltd Data processing apparatus
JP2538053B2 (ja) * 1989-05-08 1996-09-25 松下電器産業株式会社 制御装置
JPH0612522B2 (ja) * 1989-05-08 1994-02-16 日本電気アイシーマイコンシステム株式会社 並列処理マイクロプロセッサ
US5129067A (en) * 1989-06-06 1992-07-07 Advanced Micro Devices, Inc. Multiple instruction decoder for minimizing register port requirements
US5241636A (en) * 1990-02-14 1993-08-31 Intel Corporation Method for parallel instruction execution in a computer
US5301341A (en) * 1990-11-28 1994-04-05 International Business Machines Corporation Overflow determination for three-operand alus in a scalable compound instruction set machine which compounds two arithmetic instructions
WO1991015820A1 (en) * 1990-04-04 1991-10-17 International Business Machines Corporation Early scism alu status determination apparatus
US5303356A (en) * 1990-05-04 1994-04-12 International Business Machines Corporation System for issuing instructions for parallel execution subsequent to branch into a group of member instructions with compoundability in dictation tag
US5295249A (en) * 1990-05-04 1994-03-15 International Business Machines Corporation Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel
US5163139A (en) * 1990-08-29 1992-11-10 Hitachi America, Ltd. Instruction preprocessor for conditionally combining short memory instructions into virtual long instructions
US5140545A (en) * 1991-02-13 1992-08-18 International Business Machines Corporation High performance divider with a sequence of convergence factors
US5287467A (en) * 1991-04-18 1994-02-15 International Business Machines Corporation Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
JPH05145093A (ja) * 1991-11-20 1993-06-11 Mitsubishi Electric Corp 半導体結晶への水銀拡散法

Also Published As

Publication number Publication date
JPH04309131A (ja) 1992-10-30
US5398321A (en) 1995-03-14
EP0498067A3 (enExample) 1994-03-23
EP0498067A2 (en) 1992-08-12

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