JPH0823788B2 - Reset controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In a system having a memory device accessed by a CPU, for example, to a reset control device for manually resetting the system from the outside, a simple configuration and a reset request signal only With the aim of enabling the system to be reset without destroying the memory contents by sending, the CPU and the memory connected to this CPU via the bus,
In a system including a memory interface that outputs a busy signal while accessing this memory, the CPU
Internal reset request signal and memory interface / busy signal are input to create a reset signal, and the reset signal is monitored and the memory interface / busy signal is monitored, and the busy signal is valid for a certain time or longer. In this case, the reset signal generating section is provided with a busy signal time monitoring section for transmitting a forced reset permission signal, and the reset signal generating section is outputting a memory interface busy signal when the reset request signal is given. If not, a reset signal is output, and when the memory interface / busy signal remains valid for a certain period of time or more, a forced reset enable signal from the busy signal time monitoring unit is received and a signal is output.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset control device for externally resetting a system, for example, manually in a system having a memory device accessed by a CPU.

In a system having a memory device accessed by a CPU, for example, when some abnormality occurs during operation, it is necessary to stop the operation of the system in accordance with an instruction from a reset switch operated by means, for example. In this case, the external reset request signal output from the reset switch is output regardless of the memory access of the CPU, so if you use this external reset request signal as is to reset the system, for example, the reset will occur during memory access. May occur and the contents of memory may be corrupted.

Therefore, a reset control device for externally resetting the system without adversely affecting the operation of the system based on the memory contents is required.

[Prior Art] A conventional reset control device of this type includes a stop key for stopping memory access on the panel surface of the system,
A reset key for issuing a reset request is provided, and the system is reset by two key operations of first stopping the memory access using the stop key and then issuing a set request by the reset key, or Before sending a reset request from the outside, first send a warning signal from the outside to each memory access device, stop its own memory access in each memory access device, and make the CPU unconditionally reset the system after a certain period of time. There are things such as configured.

[Problems to be Solved by the Invention] In these conventional devices, the former one has a problem that the memory contents are destroyed unless the two keys are operated in order. In the latter case, it is necessary to provide a means for controlling memory access for each memory access device, which complicates the configuration and increases the number of interface signals (notice signals). Further, since the CPU unconditionally resets, there is a problem that it is unknown whether or not there is a possibility that the memory contents will be destroyed.

The present invention has been made in view of these points,
An object of the present invention is to provide a reset control device which has a simple configuration and can reset the system without destroying the memory contents by sending only the reset request signal.

[Means for Solving Problems] FIG. 1 is a block diagram showing the principle of the present invention. In the figure, 1 is a CPU, 2 is a memory connected to the CPU 1 via a bus BS, and 3 is an interface unit of the memory 2, which outputs a memory interface busy signal when the memory is in use.

In the CPU1, 11 is a reset signal creation unit that inputs a reset request signal and a memory interface busy signal from the outside, and creates a reset signal for resetting the system, 12 is a monitor of the memory interface busy signal by the reset request signal When the busy signal is valid for a certain time or longer, the busy signal time monitoring unit sends a forced reset permission signal to the reset signal creating unit 11.

[Operation] When the reset request signal is given, the reset signal generator 11 outputs the reset signal when the memory interface busy signal is not output, and when the busy signal remains valid for a certain time or more, the busy signal is output. It receives a forced reset permission signal from the time monitoring unit 12 and outputs a reset signal.

This simplifies the configuration and prevents the memory contents from being destroyed.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of the essential parts of an embodiment of the present invention. Here, the reset signal creation unit 11 configured in the CPU1
And a busy signal time monitoring unit 12, both of which are configured by hardware.

In the reset signal generator 11, F1 is a first flip-flop to which a reset request signal from the outside is applied to the D terminal via the inverter IV, and F2 is the output of the first flip-flop F1 to the D terminal. The second flip-flops for synchronizing the reset request signal sent from the outside at an arbitrary timing with the machine clock. The machine clock or these clocks are used as the clocks of these flip-flops F1, F2. The purpose is achieved by using a clock that is synchronous with the clock. Then, the reset request signal synchronized with the machine clock is output from the gate G1. F3 is a third J type flip-flop, to which the reset request signal from the gate G1 is applied.

G2, G3, and G4 are gates, and F4 is a fourth J-type flip-flop, and the output of the gate G3 is applied to the J terminal to output a reset signal. This reset signal is given to a memory access device and a memory (not shown). Also, gate G2
The timer output of the first timer T1 which is applied to the first timer T1 and is output after a predetermined time has been applied to the K terminals of the third and fourth J type flip-flops. . The gate (OR gate) G4 is a busy signal from the memory interface and a busy signal time monitoring unit 12
And a forced reset enable signal from the same are input, and its output signal is applied to the gate G3.

In the busy signal time monitoring unit 12, G5 is a gate, and inputs the output of the gate G2 in the reset signal generating unit 1 and the memory interface busy signal. T2 is a second timer which counts clocks by the output from the gate G5 and outputs a forced reset enable signal after a predetermined time.

G6 is busy signal, forced reset enable signal and gate G2
F5 is a fifth J type flip-flop in which the output of the gate G6 is applied to the J terminal, which can be reset by a write command from the program via the K terminal. The output of F5 is connected to the CPU internal bus (not shown) so that the state of F5 can be read by a program. The gate G6 and the J-type flip-flop F5 constitute a register means for notifying the software side that the reset signal is forcibly output as a result of monitoring the busy signal, which is essential in the present invention. Is not a component of.

When the device configured in this way operates normally,
It is as follows if it explains separately at the time of forced reset.

(At Normal Reset) FIG. 3 is a time chart showing the operation at normal reset.

FIG. 3 (A) is a waveform diagram of the reset request signal given to the third flip-flop F3, and the third flip-flop F3 is set by this as shown in (B). The output of the third flip-flop F3 is given to the gate G3 through the gate G2. Here, if the interface busy signal is turned off as shown in (c), or if it is turned off (when no memory is accessed),
The off state of this busy signal goes through gate G4 and gate G3.
, The gate G3 is opened, the fourth flip-flop F4 is set, and the reset signal becomes valid as shown in (d). This reset signal activates the first timer T1, and after the reset signal becomes valid, a predetermined time t1
When the time has passed, the timer output is sent as shown in (e), and the third and fourth flip-flops F3 and F4 are reset,
Cancel the validity of the reset signal.

(At the time of forced reset) FIG. 4 is a time chart showing the operation at the time of forced reset. The reset request signal shown in FIG.
The operation in which the flip-flop F3 is set as shown in (b) is the same as that in FIG. Here, the busy signal is already active as shown in (c),
When a predetermined time t2 (this time is set longer than the maximum busy time for normal memory access) has elapsed from the time when the flip-flop F3 of
The timer T2 outputs the forced reset signal to the gate G3 via the OR gate G4 as shown in (d). The forced reset signal is sent to the fourth flip-flop via the gate G3.
By setting F4, the reset signal becomes valid as shown in (e). In addition, the above-mentioned forced reset signal sets the fifth flip-flop F5 through the gate G6.
Set F5 as shown in (g).

When the reset signal becomes valid as shown in (e), the first timer T1 is started, and when the predetermined time t1 elapses, the third timer T1
Similarly to the figure, send the timer output as shown in (f),
The third and fourth flip-flops F3 and F4 are reset to cancel the validity of the reset signal.

The set state of the fifth flip-flop F5 indicates that the busy signal exceeds the maximum time for normal memory access, which may have destroyed the destination of the busy signal. It means that. Therefore, it is possible that the contents of the memory may have been destroyed by the forced reset by reading the set state of this flip-flop F5 as shown in (g) after the reset signal is released from being valid. I try to get to know. Then, if there is a possibility that the memory contents will be destroyed, the memory will be initialized.

[Effect of the Invention] As described in detail above, according to the present invention, the timing of sending the reset signal in response to the reset request from the outside is operated according to the state of the memory access. Further, it is possible to provide a reset control device capable of resetting the system only by the reset signal.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of the essential parts of an embodiment of the present invention, and FIGS. 3 and 4 are time charts showing an example of the operation. In FIGS. 1 and 2, 1 is a CPU, 2 is a memory, 3 is a memory interface, 11 is a reset generation unit, and 12 is a busy signal time monitoring unit.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Ichiyoshi Okabe 4-49, Fukaminishi, Yamato-shi, Kanagawa PFU Yamato Factory Co., Ltd. (72) Osamu Moriyama 4-chome, Fukaminishi, Yamato-shi, Kanagawa No. 49 In stock company PFU Yamato Factory (72) Inventor Hideyuki Sugawara 4-249 Fukaminishi, Yamato City, Kanagawa Prefecture PFU Yamato Factory

Claims (1)

[Claims] 1. A CPU (1) and a memory (2) connected to the CPU (1) via a bus.
And a memory interface (3) which outputs a busy signal while accessing the memory (2), in the CPU (1), a reset request signal and a memory interface busy signal from the outside are provided. A reset signal creation unit (11) that inputs and generates a reset signal, and a memory interface / busy signal is monitored by a reset request signal, and if the busy signal is valid for a certain time or more, the reset signal creation unit (11) is A busy signal time monitoring unit (12) for sending a forced reset permission signal is provided, and the reset signal creation unit (11) is a reset signal when a memory interface busy signal is not output when a reset request signal is given. Is output, and the busy signal time is monitored when the memory interface / busy signal remains valid for a certain time or longer. Reset control apparatus and outputs the received signal to force a reset permission signal from (12).