JPS5935263A - Memory control circuit - Google Patents

Abstract

PURPOSE:To prevent the influence of a fault exerting upon other computers, by permitting access within a specific time limit according to priority in a system wherein one memory is accessed by plural computers. CONSTITUTION:When a computer A has priority to a computer B and they generate memory requests MREQA and MREQB at the same time, a decision making circuit 7 outputs a gate signal MENa to open gates 3 and 5, permitting the computer A to access the memory 1. A timer 8 outputs a time limit signal TUa on the basis of a specific time limit. Consequently, the circuit 7 stops the output of the gate signal MENa and outputs a gate signal MENb to allow the computer B to access the memory 1 within the specific time limit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for controlling access to a memory shared by a plurality of computers.

Conventionally, there has been a circuit of this type as shown in FIG.

In FIG. 1, memory request (signal) MREQ A,
MREQ B is a signal output from the central processing unit, ie, computers A and B (not shown), requesting access to the memory 1.

Input to gate 2. Gate 2 is the memory request MRE
Gate signal MEN corresponds to Q A and MREQ B.
*[1i12 is set to output A, MEN BY, and here the gate signal MEN (or MEN B) is output in response to the memory request MREQ A (or MREQ B) input earlier in time. .

Gate signals MEN A and MEN B are address signals A and B of computers A and B for accessing memory 1.
It is input to a gate 6.4 which causes DRA and ADRB to open and a gate 5.6 which causes data signals DATA A and DATA BY to open.

In operation, for example, if memory request MREQ A occurs before memory request MREQ B.

Gate signal MEN A is output and gates 3 and 5 are opened. This causes the address signal ADR to be sent to the computer.
A is supplied to the memory 1 through the gate 5, and the memory 1 reads (or writes) the data signal Ai through the gate 5. Computer B is made to wait until such memory access by computer A is completed, and a conflict in access to memory 1 is avoided.

Since the conventional memory control circuit is configured as described above, it has the disadvantage that when the first computer fails to complete the rememory access due to a malfunction, the second computer starts accessing the memory. was there.

This invention eliminates the drawbacks of the conventional ones as described above.
This method was developed to provide a maximum allowable memory access time for each computer, and when this time is reached, the memory access is forcibly released for other computers. It is an object of the present invention to provide a memory control circuit that can prevent a failure from spreading to other computers even if a failure occurs in one computer.

Hereinafter, FIG. 7 will be described as an embodiment of the present invention. Second
In the figure, the same reference numerals as in FIG.
The gate signal MENa is input to the timer 8 and gates 5 and 5 in the determination circuit that outputs either EN a or MEN b.

Gate signal MEN b is input to timer 9 and gates 4 and 6. Timers 8 and 9 receive gate signals MEN a,
After being activated by MEN bK, the time signal TU a, TU bi outputs a small amount after a predetermined period of time, so that the determination circuit 7 outputs the gate signal MBNa.

MEN　by　stops the small output.

In operation, for example, when the priority between computers A and B is set to A)B, the simultaneous pressure memory request MR
If EQ A and MREQ B occur, the determination circuit 7 outputs a gate signal MEN a. This starts timer 8 and opens gates 3 and 5. On the other hand, since gate signal MENb is not output, timer 9
is not activated and gates 4 and 6 are closed. By opening gates 5 and 5, computer A can access memory 1. The timer 8 outputs a time limit signal TUa'g when a predetermined time limit is exceeded.

As a result, the 1 determination circuit 7 stops outputting the gate signal MEN a, responds to the memory request MREQ B of the computer B waiting here, and outputs the gate signal MEN by.
<Output. Thereafter, the computer B controls the acceleration timer 90 of the memory 1 to enable the processing for a predetermined period of time in the same manner as in the case of the computer. Such processing ensures that even if computer A (or B) is unable to complete access to memory 1 due to a failure, it is still possible to access computer B (or A) within a predetermined time period after access is started, that is, it can be released. can.

In the above embodiment, a timer is provided for each computer, but if the functions of these computers are significantly different, memory control rights may be given only to computers with more important functions.

In this case, one timer ya' can be omitted.

As described above, in a system in which one memory t is accessed by multiple computers.

Since we allowed access to each computer for a predetermined period of time according to the priority given to each computer, even if a particular computer malfunctions, it will not affect the other computers. The memory can be accessed without any influence, and the reliability of the multi-computer system can be improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional memory control circuit, and FIG. 2 is a circuit diagram of a memory control circuit according to an embodiment of the present invention. 1...Memory, 2-6...-gate, 7...Judgment circuit, 8.9...Timer. Note that in the drawings, the same reference numerals indicate the same parts χ. Agent Makoto Kuzuno (and 1 other person) Figure 1 Figure 2 Figure 35

Claims (1)

[Claims] determining whether to generate one possible signal selected in accordance with the memory access request signals output from each of the plurality of central processing units and the priority quality for memory access given in advance to each of the central processing units; a circuit, a timer that is activated by the enable signal and prohibits generation of the enable signal after a predetermined time period, and a gate that guides a signal for memory access of the central processing unit corresponding to the enable signal to the memory. Memory control circuit.