JPH01114955A - Memory protection system - Google Patents

Memory protection system

Info

Publication number
JPH01114955A
JPH01114955A JP62273806A JP27380687A JPH01114955A JP H01114955 A JPH01114955 A JP H01114955A JP 62273806 A JP62273806 A JP 62273806A JP 27380687 A JP27380687 A JP 27380687A JP H01114955 A JPH01114955 A JP H01114955A
Authority
JP
Japan
Prior art keywords
ram
access right
block
controlling
memory protection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62273806A
Other languages
Japanese (ja)
Inventor
Maki Uematsu
上松　真樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62273806A priority Critical patent/JPH01114955A/en
Publication of JPH01114955A publication Critical patent/JPH01114955A/en
Pending legal-status Critical Current

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  • Storage Device Security (AREA)

Abstract

PURPOSE:To execute a simple and sure memory protection control in a small system by adding an FF applying the access right to a RAM to a fixed RAM block unit and managing and controlling the FF by an OS. CONSTITUTION:The RAM 1 is divided from a RAM area to be used for the whole system into blocks with an optional size and each block is one unit for memory management. A gate circuit 2 determines the validity/invalidity of access right to the RAM 1. The gate circuit 2 controls writing in the RAM 1 by controlling a writing signal and may control also an address signal to the RAM 1. Each FF 3 for controlling the access right to the RAM 1 is connected at every block to be the control unit of the RAM 1. The FF 3 can control the access right of its corresponding block by applying a request or no request of access right to a selecting signal and applying a strobe signal.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はマイクロコンピュータシステムにおけ′　るメ
モリの保護方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory protection system in a microcomputer system.

〔従来の技術〕[Conventional technology]

従来、この種の小規模なマイクロコンピュータシステム
におけるメモリ管理方式は、ソフトウェアにより直接メ
モリのアクセス領域を管理する方式が主に行なわれてい
た。Conventionally, the memory management method used in this type of small-scale microcomputer system has mainly been a method in which the memory access area is directly managed by software.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来のマイクロプロセッサを用いたメモリ管理機能を持
たない、あるいは、ソフトウェアによるメモリ管理によ
ればメモリの保護が行なわれないので、ＲＡＭ　（ラン
ダムアクセスメモリ）上のあるデータ領域をあるタスク
が占有している時に何らかの不正動作によりＲＡＭ上の
データを破壊してしまった場合に、別のタスクがそのデ
ータ領域を参照して動作しようとする時にデータの内容
が破壊されており正常な動作が行なえないという場合が
あった。Because it does not have a memory management function using a conventional microprocessor, or because memory management using software does not protect the memory, it is possible for a certain task to occupy a certain data area in RAM (Random Access Memory). If the data on the RAM is destroyed due to some kind of malfunction while the task is in progress, when another task tries to refer to that data area and perform an operation, the data contents will be destroyed and normal operation will not be possible. There was a case.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のメモリ保護方式ではＲＡＭ領域のアル一定のＲ
ＡＭブロック単位にアクセス権を保持するＦ−Ｆ（フリ
ップ・フロップ）を設け、ソフトウェア（ＯＳ）により
このアクセスすべきＲＡＭ領域に対応するこのＦ−Ｆを
介してメモリの保護管理をできる様にしている。In the memory protection method of the present invention, the RAM area has a constant R
An F-F (flip-flop) is provided that holds access rights for each AM block, and the software (OS) can protect and manage memory through this F-F that corresponds to the RAM area to be accessed. There is.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例を示すブロック図である。１
はＲ，Ａ　Ｍであり、システム全体で使用するＲＡＭ領
域から任意の大きさでブロックに分割されており、その
ブロックは本発明によるメモリ管理の一単位となるもの
である。なお、この分割されたＲＡＭ領域は全ＲＡＭ領
域に渡る必要はない。２は、ＲＡＭ１へのアクセス権の
可否を決定するゲート回路である。このゲート回路は本
例においては書き込み信号を制御することによってＲＡ
Ｍ１への書き込み制御してし）るが、ＲＡＭ　１へのア
ドレス信号（デバイス・セレクト信号）を制御してもよ
い。３は、ＲＡＭ１へのアクセス権制御用のフリップ・
フロップであり、ＲＡＭ１の管理単位であるブロック毎
に設けられる。このフリップ・フロップの制御は、セレ
クト信号にアクセス権を要求するかしないかを与え、ス
トローブ信号を与えることにより対応するブロックのア
クセス権を制御することができる。FIG. 1 is a block diagram showing one embodiment of the present invention. 1
are R, AM, and the RAM area used in the entire system is divided into blocks of arbitrary size, and each block is a unit of memory management according to the present invention. Note that this divided RAM area does not need to cover the entire RAM area. Reference numeral 2 denotes a gate circuit that determines whether or not access to the RAM 1 is granted. In this example, this gate circuit controls the RA by controlling the write signal.
The address signal (device select signal) to RAM 1 may also be controlled. 3 is a flip for controlling access rights to RAM1.
A flop is provided for each block, which is a management unit of the RAM 1. To control this flip-flop, it is possible to control the access right of the corresponding block by giving a select signal whether or not to request an access right, and by giving a strobe signal.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、一定のＲＡＭブロック単
位にＲＡＭのアクセス権を与えるフリップ・フロップを
付加し、そのフリップ・フロップをソフトウェア（Ｏ３
）で管理・制御することにより小規模なシステムにおい
て、簡単で確実なメモリ保護管理を行なうことができる
という効果がある。As explained above, the present invention adds a flip-flop that gives RAM access rights to a certain RAM block, and the flip-flop is installed in software (O3).
) has the effect of allowing simple and reliable memory protection management in small-scale systems.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明のメモリ保護方式を示すブロック図であ
る。 １・・・ＲＡＭ、２・・・ゲート回路、３・・・ブロッ
ク管理用フリップ・フロップ。FIG. 1 is a block diagram showing the memory protection scheme of the present invention. 1...RAM, 2...gate circuit, 3...flip-flop for block management.

Claims (1)

【特許請求の範囲】[Claims] マイクロコンピュータシステムにおけるメモリ保護方式
において、ＲＡＭ上の予じめ定めた連続したＲＡＭ領域
をある一定のブロックに分割し、前記分割された各ブロ
ックに対応して、ＲＡＭ領域のアクセスを禁止・許可す
るフリップ・フロップを設けオペレーティングシステム
により前記フリップ・フロップを管理し、前記ＲＡＭへ
のアクセスを制御することを特徴とするメモリ保護方式
。In a memory protection method for a microcomputer system, a predetermined continuous RAM area on the RAM is divided into certain blocks, and access to the RAM area is prohibited or permitted according to each divided block. A memory protection system comprising a flip-flop and an operating system managing the flip-flop and controlling access to the RAM.
JP62273806A 1987-10-28 1987-10-28 Memory protection system Pending JPH01114955A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62273806A JPH01114955A (en) 1987-10-28 1987-10-28 Memory protection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62273806A JPH01114955A (en) 1987-10-28 1987-10-28 Memory protection system

Publications (1)

Publication Number Publication Date
JPH01114955A true JPH01114955A (en) 1989-05-08

Family

ID=17532830

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62273806A Pending JPH01114955A (en) 1987-10-28 1987-10-28 Memory protection system

Country Status (1)

Country Link
JP (1) JPH01114955A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103440176A (en) * 2013-09-13 2013-12-11 北京经纬恒润科技有限公司 Protection method and device for memory in real-time operation system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103440176A (en) * 2013-09-13 2013-12-11 北京经纬恒润科技有限公司 Protection method and device for memory in real-time operation system

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