JPH04251324A - Semiconductor disk device - Google Patents

Abstract

PURPOSE:To enable a host device to make access to a memory unit irrespective of the access from a processor section and, at the same time, to enable the processor section to make maintenance irrespective of the host device when the processor section requires urgently the maintenance to the memory unit. CONSTITUTION:When an access instruction to a memory unit 50 composed of multi-port RAM elements is issued from a host device 10, the instruction is sent to a 1st memory control section 30 through an interface control section 20. The section 30 starts the access to the memory unit 50. In addition, when a processor section 40 requires maintenance to the memory unit 50, the section 40 issues a memory unit 50 accessing instruction to a 2nd memory control section 31. The section 31 starts the access to the memory unit 50.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor disk device.

0002

2. Description of the Related Art In a conventional semiconductor disk device, a memory unit is composed of a RAM element, and a memory control section for controlling the memory unit corresponds to the memory unit.

By the way, electronic disks hold data in RAM elements, but data in RAM elements is generally easily destroyed by naturally occurring radiation and the like. Therefore, it has a processor section that performs maintenance such as error detection and correction. It also has an arbitration unit that arbitrates between requests for access to the memory unit from the host device through the interface control unit and requests for access from the processor unit for maintenance. The memory unit could be accessed through the memory control section.

0004

[Problems to be Solved by the Invention] In the conventional semiconductor disk device described above, when accessing the memory unit section, both the interface control section and the processor section issue an access request to the arbitration section, and after permission is granted, the memory unit is accessed. Since the unit is configured to access the memory unit, if the processor section accesses the memory unit in a complicated manner or for a long time, it becomes difficult to grant access requests from the host device, and the performance of the semiconductor disk device may deteriorate. There is a problem to be said.

Another problem is that when the processor section urgently requires maintenance, if a host device is using it, access is not permitted and maintenance is impossible.

[0006]

[Means for Solving the Problems] A semiconductor disk device of the present invention includes an interface control unit that controls an interface with a host device, and a memory unit that is configured of a multi-port RAM element that can be accessed from multiple systems at the same time. , a processor unit for maintaining the semiconductor disk device, an interface control unit for accessing the memory unit at the same time, and a first memory control unit located between the memory unit and controlling access of the interface control unit; A second memory control section is provided between the processor section and the memory unit and controls access by the processor.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. The semiconductor disk device 60 is connected to the host device 10 via the interface control section 20. The memory unit 50 uses a multi-port RAM element that can be accessed simultaneously from two systems, and can be accessed simultaneously from the first memory control section 30 and the second memory control section 31.

Next, the operation of this embodiment will be explained. When a command to access the memory unit 50 is issued from the host device 10, the command is sent to the interface control unit 2.
0 to the first memory control unit 30. When the first memory control unit 30 receives the command,
Access to the memory unit 50 is started. Furthermore, when maintenance of the memory unit 50 becomes necessary due to a factor that occurs unrelated to the operation of the host device, the processor unit 40 issues an access command to the memory unit 50 to the second memory control unit 31. The second memory control unit 31 includes a processor unit 40
When the command is received, access to the memory unit 50 is started.

0010

As explained above, the present invention uses a multi-port RAM element in the memory unit and makes it accessible from two systems of memory control units.
This has the effect that the host device can access the memory unit regardless of access from the processor section.

Another advantage is that when the processor section urgently requires maintenance on the memory unit, the maintenance can be done in the shortest possible time regardless of the host device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention.

[Explanation of symbols]

10 Host device 20 Interface control section 30 First memory control section 31 Second memory control section 40 Processor section 50 Memory unit 60 Semiconductor disk device

Claims (1)

[Claims] 1. An interface control unit that controls an interface with a host device, a memory unit configured with a multi-port RAM element that can be accessed from multiple systems at the same time, and a processor unit that maintains a semiconductor disk device; a first memory control section that is located between the interface control section and the memory unit and controls access of the interface control section; and a second memory control section that is located between the processor section and the memory unit that controls access of the processor. A semiconductor disk device comprising: