JPH04333961A - Dual bus controller - Google Patents

Abstract

PURPOSE:To accelerate processing speed by shortening the time required for acquisition of the right of using a bus at an information processor loading the plural buses in a system. CONSTITUTION:This dual bus controller is composed of a main access register 5 to request the right of using a main Bus A by a function module B, main status register 4 to report the acquisition of the main Bus using right to a local CPU 10, local control register 2 to request the stop of the local CPU 10 from the main Bus, local status register 3 to report the stop of the local CPU 10 to a main CPU 8 and buffer controller 6 to control a buffer for connecting the main Bus A and a local Bus C.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to an electronic device having one or more functional modules in a system and connecting these functional modules with a main bus. and information transfer between the main CPU and devices inside the functional module,
and a bus control circuit that transfers information between a local CPU and a device connected to a main bus.

0002

[Prior Art] A conventionally known system has one
Information transfer in an electronic device that has one or more functional modules, connects the functional modules with a main bus, and has a local bus within each functional module is performed on the main bus side and the local bus as shown in Figure 2. A local bus requester (15), a main bus requester (14), and a main bus arbiter (7) (main bus
A circuit that receives a signal requesting the right to use the main bus from a device connected to s and determines which device is given the right to use the main bus), local B
A bus control circuit (16) consisting of a us arbiter (13) (a circuit that receives a signal requesting the right to use the local bus from a device connected to the local bus and determines which device is given the right to use the local bus). ), and when the main CPU (8) accesses a device inside the function module, the main CPU (8) first accesses the main B
After requesting the us arbiter (7) for the right to use the main bus and securing the right to use the main bus, the bus control circuit (16) requests the right to use the local bus.
The local bus requester (15) requests the local bus arbiter (13) for the right to use the local bus, and after securing the right to use the local bus, connects the main bus and the local bus. A bus interface buffer (12) is used to access the target device inside the functional module and transfer information. Also, when the local CPU (10) accesses a device on the main bus, the local CPU (10) first accesses a device on the main bus.
) is on the local bus side, the local bus arbiter (
13) to request main Bus usage rights from Local B.
After securing the right to use the us, the main bus requester (14) accesses the main bus requester (14) in the bus control circuit (16) to request the right to use the main bus. After requesting the right to use the main bus and securing the right to use the main bus, the bus interface buffer (12) for connecting the main bus and the local bus is used to access the target device inside the function module. Information was being transferred.

0003

[Problem to be solved by the invention] Main B as shown in Figure 2
When using a bus control circuit consisting of a local bus requester (15) and a main bus requester (14) for requesting bus usage rights from the us side and the local bus side, the main CPU (8) functions. When accessing a device on a module or when the local CPU (10) accesses a device on the main bus, the B of both the local bus and the main bus must be
It is necessary to secure the right to use the bus, and the time it takes to secure the right to use the bus increases the access time.

0004

[Means for solving the problem] The above problem is solved by the main access, which generates a signal for the functional module to request the right to use the main bus by setting data from the local bus side as shown in FIG. register(
5), a main status register (4) for notifying the local CPU that the functional module has acquired the right to use the main bus, and a signal for the main CPU to request stoppage of the local CPU from the main bus side. a local control register (2) that generates a local CPU, and a local status register (3) that notifies the main CPU that the local CPU has stopped.
After the functional module acquires the right to use the main bus, it synchronizes and controls the buffer for connecting the main bus and local bus with the read cycle and write cycle of the local CPU, and also stops the local CPU. This can be solved by providing a dual bus controller (1) having a buffer controller (6) that controls the buffer in synchronization with the read cycle and write cycle of the main CPU.

[0005]

[Operation] The local control register (2) in Figure 1 generates a signal to start and stop the local CPU (10) by setting it from the main bus side, and the local status register (3) generates a signal to start and stop the local CPU (10). By reading the register from the main bus side, the local C
It can be seen whether the PU (10) is operating or stopped. By setting the main access register (5) from the local bus side, the main bus arbiter (7)
This is a register that generates a signal for a functional module to request the right to use the main bus, and as a result, indicates that the functional module has acquired the right to use the main bus.
The register for the local CPU to know is the main status register (4). When the main access register (5) is disabled and the local status register (3) indicates stop, the buffer controller (6) adjusts the bus interface buffer (12) to the write/read timing of the main CPU. If the main access register (5) is enabled and the main status register (4) is
When the right to use US has been acquired and the local status register (3) indicates activation, the bus interface buffer (12) is controlled in accordance with the write/read timing of the local CPU.

[0006]

[Embodiment] An embodiment of the present invention will be explained with reference to FIG. Figure 1 shows the main memory (9) that stores programs and data.
), a main CPU (8) that supervises the entire system using programs and data in the main memory (9), and a main Bus arbiter (8) that determines the right to use the main bus.
7) This is an embodiment of an electronic circuit system composed of a functional module connected to the main bus, and this functional module includes a bus interface buffer (12) that couples the main bus and the local bus, and a function module that controls the operation of the functional module. local memory (11) for storing programs and data necessary for
A dual bus controller (
1), and a dual bus controller (
1) is a local control register (2) that generates a signal to start and stop the local CPU (10) by setting it from the main bus side, and whether the local CPU (10) is operating or stopped. Local status register (3) that tells the main bus whether
) A main access register (5) that generates a signal for a functional module to request the right to use the main bus from the main bus arbiter (7) by setting it from the local bus side; It consists of a main status register (4) that allows the local CPU to know that the usage right has been acquired, and a buffer controller (6) that controls the bus interface buffer (12). To explain the operation of this system, when the local CPU (10) accesses the main memory (9), the local CPU (10) first requests the main access register (5). generates a signal for the functional module to request the right to use the main bus from the main bus arbiter (7). Local CPU (10
) learns that it is authorized to use the main bus by reading the main status register (4), and then generates and accesses the target address on the main bus. At this time, the buffer controller (6) controls the bus interface buffer (12) in accordance with the write/read timing of the local CPU (10), and transfers addresses and data. Main C
When the PU (8) accesses the local memory (11), the main CPU (8) first uses the main bus arbiter (
7) requests the right to use the main bus. Main Bu
When s becomes available, a stop command for the local CPU (10) is set in the local control register (2), and the local control register (2) immediately generates a stop signal to the local CPU (10). When the local CPU (10) stops, stop information is set in the local status register (3), and the main CPU
The U (8) reads the local status register (3) to confirm that the local CPU (10) has stopped, and then the main CPU (8) generates and accesses the target address of the functional module. At this time, the buffer controller (6) controls the bus interface buffer (12) in accordance with the write/read timing of the main CPU (10), and transfers addresses and data. When the target address has been accessed, a startup command for the local CPU (10) is set in the local control register (2).

[0007]

[Effect of the invention] 1. According to the present invention, the local CPU (
10) When accessing a device on the main bus,
It is no longer necessary to secure bus usage rights for the local bus, and as a result, the main bus device and local CPU
(10) can be shortened, and the local CPU (10) can be used efficiently.

2. When the main CPU (8) continuously accesses devices inside the functional module, the local CPU accesses the local control register (2).
By temporarily stopping (10), local B
Since the main CPU (8) can continuously occupy the US, the information transfer rate can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block layout diagram of a basic embodiment of the present invention.

FIG. 2 is a block layout diagram of an electronic device using a conventional bus controller.

[Explanation of symbols]

2...Local control register, 3...Local status register, 4...Main status register, 5...
Main access register, 6...Buffer controller, 8
...Main CPU, 10...Local CPU.

Claims (1)

[Claims] Claim 1: A main bus (a bus that transmits information between the main CPU that controls the entire system and individual functional modules, hereinafter referred to as the main bus), and a local bus.
In a system having (a bus independent of the main bus, hereinafter referred to as local bus, which incorporates a local CPU for dedicated processing of individual functions within each functional module and transmits information within the module, hereinafter referred to as local bus),
By setting data from the local bus side,
It has a register that generates a signal for a functional module to request the right to use the main bus, and a register that notifies the local CPU that the functional module has acquired the right to use the main bus. It has a register that generates a signal for the main CPU to request that the CPU be stopped and started, and a register that notifies the main CPU that the local CPU has stopped and started. After acquisition, the buffer for connecting the main bus and the local bus is controlled in synchronization with the read cycle and write cycle of the local CPU, and after the local CPU is stopped, the buffer is connected to the main bus.
A dual bus controller comprising a circuit that performs control in synchronization with a read cycle and a write cycle of a PU.