JPH0823044A - Manufacture of high frequency semiconductor device - Google Patents

Manufacture of high frequency semiconductor device

Info

Publication number
JPH0823044A
JPH0823044A JP15337294A JP15337294A JPH0823044A JP H0823044 A JPH0823044 A JP H0823044A JP 15337294 A JP15337294 A JP 15337294A JP 15337294 A JP15337294 A JP 15337294A JP H0823044 A JPH0823044 A JP H0823044A
Authority
JP
Japan
Prior art keywords
ceramic
semiconductor device
copper
high frequency
heat treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15337294A
Other languages
Japanese (ja)
Inventor
Masaru Ishibashi
勝 石橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP15337294A priority Critical patent/JPH0823044A/en
Publication of JPH0823044A publication Critical patent/JPH0823044A/en
Pending legal-status Critical Current

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To alleviate the thermal strain in assembling of the high frequency semiconductor device of a ceramic casing having a copper flange, and to prevent generation of cracks by a method wherein, after the ceramic casing with a copper flange has been assembled, heat treatment is conducted at a specific temperature, and the outer casing is formed. CONSTITUTION:A ceramic casing is composed of a beryllia substrate part 1 on which a silicon transistor chip 4, formed by beryllia, is mounted, a ceramic frame part 2a where a sealing cap is mounted, a ceramic substrate 2b provided with an electrode lead-out part 5 with is used to lead out the electrode of a transistor chip, and a copper heat sink 3 having a screwing part. After assembling the abovementioned ceramic casing, heat treatment is conducted at 450 to 500 deg.C, the thermal strain generated when assembling the ceramic casing in the manufacture of the high frequency semiconductor device is alleviated, and the generation of cracks is prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は高周波半導体装置の製造
方法に係り、特に銅製フランジを用いるセラミック製外
囲器の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a high frequency semiconductor device, and more particularly to a method of manufacturing a ceramic envelope using a copper flange.

【0002】[0002]

【従来の技術】高周波高出力トランジスタの高出力化は
目覚ましく、トランジスタチップの高出力、高性能化に
加え、外囲器の大型化、低熱抵抗化が盛んに行われてい
る。
2. Description of the Related Art High-frequency and high-power transistors have been remarkably increased in output. In addition to high-output and high-performance transistor chips, large-sized envelopes and low thermal resistance have been actively used.

【0003】ここでは、高周波・大電力用半導体装置に
用いるセラミック製外囲器の中で特に、シリコントラン
ジスタ用セラミック製外囲器の構造、およびその製造方
法について図1を参照して説明する。
Here, of the ceramic envelopes used in the semiconductor device for high frequency and high power, the structure of the ceramic envelope for the silicon transistor and the manufacturing method thereof will be described with reference to FIG.

【0004】セラミック製外囲器は、ベリリアで形成さ
れシリコントランジスタチップ4をマウントするベリリ
ア基板部1、いずれもセラミックで形成されシーリング
キャップを取付けるフレーム部2aおよび前記トランジ
スタチップの電極を導出する電極導出部5が設けられる
セラミック基板部2b(図示省略)、銅で形成されねじ
止め部を備えるヒートシンク3で構成されている。
The ceramic envelope is a beryllia substrate portion 1 formed of beryllia and mounting a silicon transistor chip 4, a frame portion 2a, both of which are made of ceramic, for mounting a sealing cap, and an electrode lead-out for leading out electrodes of the transistor chip. It is composed of a ceramic substrate portion 2b (not shown) on which the portion 5 is provided, and a heat sink 3 made of copper and provided with a screwing portion.

【0005】上記構造のポイントは、半導体素子の発熱
を効果的に放散させるために熱伝導率の大きい材料を用
いていることである。さらに、各材料間の熱膨張係数の
差を小さくし、熱処理等で発生する歪みによるクラック
を極力防止している。
The point of the above structure is that a material having a high thermal conductivity is used in order to effectively dissipate the heat generated by the semiconductor element. Further, the difference in the coefficient of thermal expansion between the respective materials is made small, and cracks due to strain generated by heat treatment or the like are prevented as much as possible.

【0006】次の叙上に用いられる各材料の熱伝導率お
よび熱膨張係数を表示する。
The thermal conductivity and the coefficient of thermal expansion of each material used in the following table are displayed.

【0007】[0007]

【表1】 上記の各部材を形成後、銀ろう材による接着を850℃
にて行い、さらに、Ni,Auめっきを施して、外囲器
が完成する。
[Table 1] After forming each of the above members, use a silver brazing material to bond them at 850 ° C.
Then, Ni, Au plating is applied to complete the envelope.

【0008】半導体装置製造工程における熱処理工程
は、半導体素子、内部整合回路部品をマウントするため
の400℃のAuSi共晶工程、200℃のAuワイヤ
ボンディング工程、及び、300℃のシーリング工程で
ある。
The heat treatment process in the semiconductor device manufacturing process is a 400 ° C. AuSi eutectic process for mounting semiconductor elements and internal matching circuit parts, a 200 ° C. Au wire bonding process, and a 300 ° C. sealing process.

【0009】[0009]

【発明が解決しようとする課題】銅製フランジを用いる
上記外囲器の製造方法においては、半導体装置の製造工
程における熱処理工程での熱歪みにより、セラミック等
にクラックが発生する欠点があった。
The above-mentioned method of manufacturing an envelope using a copper flange has a drawback that cracks are generated in a ceramic or the like due to thermal strain in a heat treatment step in a semiconductor device manufacturing step.

【0010】熱歪みの低減として、銅とセラミックやベ
リリアの接触面積を小さくする方法や銅の代りに熱膨張
数の小さい銅タングステン合金を用いる方法が考えられ
るが、いずれも、熱伝導の悪化を招き、信頼性の低下を
起こす欠点があった。
As a method for reducing the thermal strain, a method of reducing the contact area between copper and ceramic or beryllia or a method of using a copper-tungsten alloy having a small coefficient of thermal expansion instead of copper can be considered, but in either case, the heat conduction is deteriorated. However, there is a drawback that it invites a decrease in reliability.

【0011】また、外囲器を大型化する場合は金属とセ
ラミックやベリリアの接触面積が大きくなるため、熱膨
張係数の差による熱歪みは、さらに顕著になる。
Further, when the envelope is made large, the contact area between the metal and the ceramic or beryllia becomes large, so that the thermal strain due to the difference in the coefficient of thermal expansion becomes more remarkable.

【0012】叙上の如く銅製のフランジを用いる外囲器
を使用する場合、半導体装置の製造工程においてセラミ
ックやベリリアにクラックが発生しやすい。
When an envelope using a copper flange as described above is used, cracks are likely to occur in ceramics and beryllia in the semiconductor device manufacturing process.

【0013】本発明の目的はフランジが銅でなるセラミ
ック製外囲器の高周波半導体装置の製造における組立の
熱歪みを緩和してクラックの発生を防止するにある。
An object of the present invention is to alleviate thermal strain in the assembly of a ceramic envelope whose flange is made of copper in the manufacture of a high frequency semiconductor device and prevent the occurrence of cracks.

【0014】[0014]

【課題を解決するための手段】本発明に係る高周波半導
体装置の製造方法は、フランジが銅でなるセラミック製
外囲器を組立したのち、450〜500℃で熱処理を施
して外囲器を構成することを特徴とする。
In the method of manufacturing a high frequency semiconductor device according to the present invention, a ceramic envelope having a flange made of copper is assembled and then heat treated at 450 to 500 ° C. to form the envelope. It is characterized by doing.

【0015】[0015]

【作用】本発明によりフランジが銅でなるセラミック製
外囲器の高周波半導体装置の製造における組立の熱歪み
を緩和してクラックの発生が防止できる。
According to the present invention, the thermal distortion of the assembly in the manufacture of the high frequency semiconductor device of the ceramic envelope whose flange is made of copper can be relaxed and the occurrence of cracks can be prevented.

【0016】[0016]

【実施例】以下、本発明に係る一実施例のシリコンバイ
ポーラトランジスタ用セラミック製外囲器の製造方法に
ついて図1を参照して説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a ceramic envelope for a silicon bipolar transistor according to an embodiment of the present invention will be described below with reference to FIG.

【0017】セラミック製外囲器は、ベリリアで形成さ
れシリコントランジスタチップ4をマウントするベリリ
ア基板部1、いずれもセラミックで形成されシーリング
キャップを取付けるフレーム部2aおよび前記トランジ
スタチップの電極を導出する電極導出部5が設けられる
セラミック基板部(図示省略)、銅で形成されねじ止め
部を備えるヒートシンク3で構成されている。
The ceramic envelope is a beryllia substrate portion 1 formed of beryllia for mounting a silicon transistor chip 4, a frame portion 2a for mounting a sealing cap, and a lead portion for leading out electrodes of the transistor chip. It is composed of a ceramic substrate portion (not shown) provided with the portion 5, and a heat sink 3 made of copper and provided with a screwing portion.

【0018】そして、製造は次の如く行う。Then, the manufacturing is performed as follows.

【0019】まず、シリコントランジスタチップ4をマ
ウントする前記ベリリア基板1、シーリング用キャップ
を取付ける前記フレーム部、電極導出部5が設けられる
前記セラミック基板部2bの夫々を成形し焼結する。
First, the beryllia substrate 1 on which the silicon transistor chip 4 is mounted, the frame portion to which the sealing cap is attached, and the ceramic substrate portion 2b on which the electrode lead-out portion 5 is provided are molded and sintered.

【0020】次に、前記部品を銀ろう材を用いて850
℃にて接着・組立する。さらに、Ni,Auめっきを施
す。
Next, the above-mentioned parts are made 850 by using a silver brazing material.
Bond and assemble at ℃. Further, Ni and Au plating is applied.

【0021】次に、450〜500℃で熱処理を施す。Next, heat treatment is performed at 450 to 500.degree.

【0022】次に、半導体素子、内部整合部品の400
℃のAuSi共晶マウント工程、さらに、200℃のA
uワイヤボンディング工程、300℃のシーリング工程
を行う。
Next, a semiconductor device and an internal matching component 400
AuSi eutectic mounting process at ℃, A at 200 ℃
A u wire bonding process and a 300 ° C. sealing process are performed.

【0023】これら各工程の熱処理においても、半導体
素子・内部整合部品、ベリリア基板・セラミック基板
に、クラックの発生は全く無かった。
Even in the heat treatment in each of these steps, no cracks were generated in the semiconductor element / internal matching component, the beryllia substrate / ceramic substrate.

【0024】熱歪みによるクラックの原因は熱膨張係数
の他に銅の硬度が大きく影響し、熱処理により硬度を小
さくすることでクラックの防止ができると考えられる。
さらに、銅素材のみを熱処理する場合よりも、外囲器組
立後に熱処理する場合のほかが効果的であった。組立後
の熱処理により、外囲器組立時の熱歪みも緩和される。
It is considered that the cause of cracks due to thermal strain is largely influenced by the hardness of copper in addition to the coefficient of thermal expansion, and cracks can be prevented by reducing the hardness by heat treatment.
Further, it is more effective to heat-treat after assembling the envelope than to heat-treat only the copper material. Due to the heat treatment after assembling, the thermal strain at the time of assembling the envelope is also alleviated.

【0025】発明者が試作確認を行ったところでは、銅
のビッカース硬度が50以下ならセラミック等にクラッ
クが発生しないことが判った。このビッカース硬度を得
るには、熱処理温度は450℃以上で熱処理時間は10
分間程であれば良い。また、熱処理温度500℃以上で
は、Ni、Auめっき層の変質、変色が起こりやすかっ
た。
When the inventor made a trial confirmation, it was found that if the Vickers hardness of copper was 50 or less, no crack was generated in the ceramic or the like. To obtain this Vickers hardness, the heat treatment temperature is 450 ° C. or higher and the heat treatment time is 10
It's good for about a minute. Further, at a heat treatment temperature of 500 ° C. or higher, the Ni and Au plating layers were likely to be deteriorated and discolored.

【0026】これらのことから、熱処理温度を450〜
500℃にし、熱処理時間は10分間程にすれば、N
i、Auめっき層の変質、変色起こさずに、セラミック
等にクラックが発生しない硬度を安定的に得ることがで
きる。
From these facts, the heat treatment temperature is 450 to
If the temperature is set to 500 ° C and the heat treatment time is set to about 10 minutes, N
It is possible to stably obtain hardness such that cracks do not occur in the ceramic or the like without the i and Au plating layers being deteriorated or discolored.

【0027】以上、本発明の一実施例としてシリコンバ
イポーラトランジスタ用セラミック製外囲器の製造方法
について説明したが、各種セラミックと金属が接する外
囲器についても、本発明の製造方法が適用でき、同様の
効果が期待できる。
The manufacturing method of the ceramic envelope for the silicon bipolar transistor has been described above as one embodiment of the present invention. However, the manufacturing method of the present invention can be applied to an envelope in which various ceramics and metals are in contact with each other. The same effect can be expected.

【0028】[0028]

【発明の効果】以上述べたように本発明によれば、銅製
フランジを用いるセラミック製外囲器の熱歪みを緩和
し、半導体装置の歩留向上と信頼性向上が実現できる。
As described above, according to the present invention, the thermal distortion of the ceramic envelope using the copper flange can be relaxed, and the yield and reliability of the semiconductor device can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明明に係る高周波半導体装置の一実施例の
要部を説明するための外囲器を示し、(a)は上面図、
(b)は(a)のAA線に沿断面図、(c)は(b)と
異なる方向の断面図。
FIG. 1 shows an envelope for explaining a main part of an embodiment of a high-frequency semiconductor device according to the present invention, in which (a) is a top view,
(B) is a sectional view taken along the line AA of (a), and (c) is a sectional view in a direction different from that of (b).

【符号の説明】[Explanation of symbols]

1…ベリリア基板部 2a…フレーム部 3…ヒートシンク 4…シリコントランジスタチップ 5…電極導出部 DESCRIPTION OF SYMBOLS 1 ... Berrillia substrate part 2a ... Frame part 3 ... Heat sink 4 ... Silicon transistor chip 5 ... Electrode lead-out part

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 フランジが銅でなるセラミック製外囲器
を組立したのち、450〜500℃で熱処理を施して外
囲器を構成することを特徴とする高周波半導体装置の製
造方法。
1. A method of manufacturing a high-frequency semiconductor device, comprising assembling a ceramic envelope whose flange is made of copper, and then heat treating it at 450 to 500 ° C. to form the envelope.
JP15337294A 1994-07-05 1994-07-05 Manufacture of high frequency semiconductor device Pending JPH0823044A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15337294A JPH0823044A (en) 1994-07-05 1994-07-05 Manufacture of high frequency semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15337294A JPH0823044A (en) 1994-07-05 1994-07-05 Manufacture of high frequency semiconductor device

Publications (1)

Publication Number Publication Date
JPH0823044A true JPH0823044A (en) 1996-01-23

Family

ID=15561021

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15337294A Pending JPH0823044A (en) 1994-07-05 1994-07-05 Manufacture of high frequency semiconductor device

Country Status (1)

Country Link
JP (1) JPH0823044A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100216731B1 (en) * 1996-10-04 1999-09-01 김충환 A power device modules using a petyllia dbc substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100216731B1 (en) * 1996-10-04 1999-09-01 김충환 A power device modules using a petyllia dbc substrate

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