JPH08223544A - Data processing circuit - Google Patents

Abstract

PURPOSE: To relieve the burden of a programer of a microcomputer when a function of extracting character information superimposed on a video signal for a specific horizontal scanning period by using the microcomputer. CONSTITUTION: An output buffer 10 storing data representing character information extracted by a data slicer 4 is activated by an enable signal *CE generated after the end of scanning of 21H of an even number field from a microcomputer 5 including a decoder 11 decoding the data. Then the data having been stored are fed to the decoder 11 in the inside of the microcomputer 5 based on a clock signal SCLIN generated from the microcomputer 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention extracts data such as character information superimposed on a specific horizontal scanning period of a video signal,
The present invention relates to a data processing circuit suitable for displaying on a display body (television receiver, VTR clock display portion, etc.).

[0002]

2. Description of the Related Art At present, a so-called closed caption system is being implemented in the United States for displaying information on a television screen as desired or for not displaying it for the purpose of deaf people. This system typically has a function of transmitting caption data from a television broadcasting station and displaying character information on a television screen in real time.

By the way, the caption data is defined by the standard so as to be superposed on the 21st horizontal scanning period (21H) of the video signal forming the odd field. In other words, 21 of the video signal forming the even field
The H does not have the caption data.
Therefore, in order to effectively use the latter 21H, instead of the caption data, complementary data representing various kinds of complementary information (program name, broadcasting station name, current time information, etc.) is superimposed on the even field 21H, and the caption data is obtained. Similar to the above, a system for processing a sampling signal is also implemented. As a specific example, let us consider the time display function of a VTR. Since this function is used for timer recording, it is desirable to be able to continue accurate time display at all times. Therefore, when the time information is superimposed on the even field 21H from the television broadcasting station side as the complementary information, this time information is
Internally extracted and signal processed, the VTR will always be able to display the correct time. Especially in the United States, the use of this complementary information is effective because the time change called summer time occurs.

Now, in order to realize the display of the complementary information on the display body, as described above, 21 of the video signal of the even field is used.
It is necessary to extract and decode the complementary data superimposed on H. About this 21H information, CVideo of FIG. 2
Will be explained. CVideo of FIG. 2 represents a composite video signal of an even field, and the run-in clock is superimposed on the period t0 in the horizontal scanning period of 21H. The run-in clock is information for notifying that complementary data is superimposed on 21H as well as caption data, and is a frequency 32 times the horizontal scanning frequency fH.
A 03 KHz clock is continuously superimposed for 7 cycles. In addition, the start bit of 3 bits is superimposed in the period t1. The start bit is defined as "001" in the standard, and the frequency in which the generation period of each bit is one cycle is 503 KHz as in the run-in clock. Further, 16-bit complementary data is superimposed in the period t2. The frequency in which the generation period of each bit of the complementary data is one cycle is also set to 503 KHz.

When extracting the complementary data from 21H, the oscillation clock obtained from the oscillator is frequency-divided to create a frequency-divided clock of 503 KHz, and the frequency-divided clock is used as the run-in clock (or start bit). The phase was aligned with "rising from" 0 "to" 1 "). The fact that the phases of the divided clock and the run-in clock match each other means that the divided clock also matches the phase of the complementary data, and the state of each bit of the complementary data. 16 bits for sequentially holding the complementary data in a shift register (not shown) in synchronization with the rising or falling of the divided clock that changes at a position where the data is stable, that is, near the middle of each bit information of the complementary data. After the complementary data of (1) is held in the shift register, the complementary data is taken out of the shift register and decoded to enable the display of complementary information on the display body.

Here, the conventional complementary information processing will be described with reference to FIG. In FIG. 3, (1) is a 21H sampling circuit for sampling complementary information superimposed on the 21st horizontal scanning period of the even field in the composite video signal. The 21H extraction circuit (1) is
Extract bit complementary information. (2) is a microcomputer having a decoding function for decoding the 16-bit complementary information. (3) is a microcomputer having a function of displaying character information on a display according to a decoded signal obtained from the microcomputer (2) in the preceding stage. For example, when the complementary information is time information, the VTR
The corrected display time will always be displayed on the display screen.

[0007]

However, in the conventional circuit shown in FIG. 3, the 21H extraction circuit (1) is a single integrated IC, but has a circuit for interfacing with a general purpose microcomputer. Microcomputer with decoding function because it does not exist (2)
Had to be provided. Therefore, since the microcomputer (2) for decoding the complementary information and the microcomputer (3) for displaying characters based on the decoding result of the microcomputer (2) are separate independent chips, each microcomputer (2) When creating a program for controlling (3), there is a problem that the load on the program developer becomes heavy due to the difference in programming languages.

Therefore, according to the present invention, when a function of extracting character information superimposed on a specific horizontal scanning period of a video signal is realized by using a microcomputer, data processing which can reduce the burden on a program developer of the microcomputer. The purpose is to provide a circuit.

[0009]

The present invention has been made to solve the above-mentioned problems, and is characterized in that character information superimposed on a specific one horizontal scanning period of a video signal is displayed. A holding unit for holding the data extracted by the extracting unit, the holding unit including a decoder for decoding the data; This is a point to supply the held data to the decoder inside the microcomputer in synchronization with the clock signal generated from the microcomputer after the operation is enabled by the enable signal generated after the scanning of the period.

[0010]

According to the present invention, the holding means for holding the data representing the character information extracted by the extracting means is generated after the end of the scanning for the specific one horizontal scanning period from the microcomputer including the decoder for decoding the data. After being enabled by the enable signal, the held data is supplied to the decoder inside the microcomputer in synchronization with the clock signal generated from the microcomputer.

[0011]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a diagram showing a data processing circuit of the present invention. In FIG. 1, (4) is a data slicer for extracting and retaining complementary information (in this embodiment, time information) superimposed on 21H of an even field in the composite video signal. Further, (5) is a microcomputer for displaying time information. First, in the data slicer (4), (6) is a PLL circuit, which generates a latch clock LCK of 503 KHz synchronized with a run-in clock of a period t0 based on a clock pulse CP of a predetermined frequency. (7) is a 21H extraction circuit, PL
Based on the clock generated from the L circuit (6), 16-bit time data is extracted as described in the conventional technique. At the same time, the 21H sampling circuit (7) generates a signal LN21 which becomes high level by 21H of the even field depending on the number of times of counting the clock. (8) is a 16-bit shift register, which has a latch clock L
The 16-bit time data output from the 21H extraction circuit (7) is serially held in synchronization with the rising edge of CK. (9) is a gate circuit composed of 16 transmission gates and the like, which opens the gate at the trailing edge of the signal LN21 and outputs the data held in the shift register (8) in parallel to the output buffer in the subsequent stage. (10) is the above-mentioned output buffer.

When the microcomputer (5) detects the trailing edge of the signal LN21, the chip enable signal * CE goes low, and the output buffer (1
0) is in an operable state. Chip enable signal * C
When E falls to the low level, the serial clock SCKIN is generated from the microcomputer (5), and the 16-bit time data held in the output buffer (10) is serialized to the microcomputer (5) side as CPDT. Is output. Microcomputer (5)
Inside, a decoder (11) for decoding 16-bit time data CPDT and a display driver (12) for displaying the time on a display unit such as a VTR are built in.

The operation of FIG. 1 is shown in the time chart of FIG. In FIG. 2, the 16-bit time data is, for example, “0110010010110100”, the serial clock SCLIN has a frequency obtained by dividing the oscillation clock of the microcomputer (5), and the serial clock SCKIN 16-bit time data CPDT is output from the output buffer (10) in synchronization with the fall.

From the above, the data slicer (4) is operated by being controlled by the program processing of the microcomputer (5), and by configuring the data slicer (4) as in the present embodiment, it is possible to realize the conventional method. In addition, it is not necessary to provide a plurality of microcomputers of completely different chips,
Since it suffices to provide only one microcomputer (5) having the decoder (11) built therein, the burden on the program creator of the microcomputer can be reduced as compared with the prior art.

[0015]

According to the present invention, when extracting character information to be superimposed in a specific horizontal scanning period of a video signal, it is sufficient to provide only one macro computer to be used. It is possible to obtain an advantage that it can be reduced compared to the conventional one.

[Brief description of drawings]

FIG. 1 is a diagram showing a data processing circuit of the present invention.

FIG. 2 is a time chart showing the operation of FIG.

FIG. 3 is a diagram showing a conventional data processing circuit.

[Explanation of Codes] (5) Microcomputer (7) 21H Extraction Circuit (8) Shift Register (9) Gate Circuit (10) Output Buffer (11) Decoder

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Masaya Ota 2-5-5 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd.

Claims (2)

[Claims] 1. A holding means for extracting data representing character information superimposed on a specific horizontal scanning period of a video signal, and a holding means for holding the data extracted by the extracting means. The means synchronizes with a clock signal generated from the microcomputer after being enabled by an enable signal generated from the microcomputer including a decoder for decoding the data after scanning of the specific one horizontal scanning period. A data processing circuit for supplying the held data to the decoder inside the microcomputer. 2. The data processing circuit according to claim 1, wherein the extracting unit and the holding unit are integrated circuits, and the circuits are controlled by a program process of the microcomputer.