JPH01229576A - Video signal sampling circuit - Google Patents

Abstract

PURPOSE:To simplify the constitution of a video signal sampling circuit by sampling the video data with use of the sampling synchronizing signal that is decided by sampling the horizontal synchronizing signal of a video information source with plural clocks produced by plural clock generating means corresponding to a bit clock generating means of a selected frequency. CONSTITUTION:The horizontal synchronizing signal HSYNC of a video information source is sampled with use of plural clocks CLK1 to CLKn produced by plural sampling clock generating means 2 corresponding to a bit clock generating means of a frequency selected by a selection means. Then a sampling synchronizing signal is decided out of those clocks CLK1 to CLKn and used for sampling of the video data. Thus it is possible to obtain a video signal sampling circuit of a simple constitution with no use of an expensive PLL circuit.

Description

TECHNICAL FIELD The present invention relates to a video signal sampling circuit, and more particularly, to a video signal sampling circuit for storing video data output from a video information source in a memory or for performing some processing on the data. The present invention relates to a video signal sampling circuit that makes it possible to easily sample video data.

BACKGROUND ART Conventionally, when sampling video data, there is a method of sampling with a sampling clock having a frequency that is more than twice the frequency of the bit clock of the video data.
Alternatively, it is common to configure a PLL circuit using a horizontal synchronizing signal output from a video information source as a reference signal.

However, in the case of the former method, since the frequency of the sampling clock is high, the circuit is required to operate at high speed, resulting in a problem that the circuit becomes complicated and expensive. Furthermore, since the number of data sampled at this time is more than twice the number of original video data, there is also the problem that the memory capacity becomes large when storing the sampled data in memory.

On the other hand, in the latter method of configuring a PLL circuit using the horizontal synchronization signal output from the video information source as a reference signal, it is possible to Since a PLL circuit must be constructed and the PLL circuit is expensive, there is a problem in that the cost of the device increases significantly.

Purpose The present invention has been made in view of the above circumstances, and its purpose is to solve the above-mentioned problems in conventional video signal sampling circuits, to eliminate the need for expensive PLL circuits, and to provide simple An object of the present invention is to provide a video signal sampling circuit that can be realized with a circuit configuration.

Configuration The above object of the present invention is to provide a circuit for sampling video data that is the output of a video information source controlled by a synchronization signal of a unique frequency, in which a plurality of pit clocks having a frequency corresponding to each of the video information sources are provided. means for generating a plurality of tarocks, means for selecting one of the pit clocks, and means for generating a plurality of tarocks having the same frequency and different phases as each of the plurality of pit clocks; A horizontal synchronization signal of the video information source is sampled by a plurality of clocks generated from the plurality of clock generation means corresponding to the pit clock generation means, a sampling synchronization signal is determined from among the plurality of tarlocks, and the sampling synchronization signal is Using,
This is achieved by a video signal sampling circuit characterized by sampling video data.

Hereinafter, the configuration of the present invention will be explained in more detail based on examples.

FIG. 6 is a diagram showing an example of the configuration of a video information processing system to which the present invention is applied. In the figure, 21a to 21n are video information sources, 20 is a video data sampling circuit M according to the present invention (hereinafter also simply referred to as a "sampling circuit"), 22 is a memory for storing sampled video data, and 23 is a memory for storing sampled video data. A mixer, for example, mixes video data input from the video information source 21n and another video information source 21a stored in the memory 22.
21(n-1) is synthesized with processed data and displayed on a CRT 24.

FIG. 1 is a block diagram of a sampling circuit showing an embodiment of the present invention. In the figure, 1 is a control circuit to be described later;
2 is a sampling clock generation circuit which will also be described later; 3
a to 3n and 4a to 4n indicate latch circuits.

Further, FIG. 2 is a block diagram showing a detailed configuration of the control circuit 1, and here, the case where n=3 is shown.

The signal output from the video information source includes a horizontal sync signal (
There are synchronization signals such as H3YNC) and vertical synchronization signal (VSYNC), and video data (VD), and the synchronization signal (pit clock) that controls these signals is usually not output. Therefore, it is necessary to generate a clock having the same frequency as this pit clock in the sampling circuit, and the sampling clock generation circuit 2 corresponds to this.

a sampling clock CLKI output from the sampling clock generation circuit 2; 2. ..., n are clocks having the same frequency f as the pit clock of the video data, but with a phase difference of 1/nf. The configuration of this circuit is, for example, one using a frequency divider as shown in FIG. 3(a), and one using a delay element as shown in FIG. 3(b). In the following explanation, an example using a frequency divider as shown in FIG. 3(a) will be explained.

The above-mentioned sampling clocks CLK1, 2 . ....

For n, latches 3 a, 3 b, . . .
, 3n samples the horizontal synchronization signal (H3YNC) and video data (VD) of the video information source. Then, sample values H31, H of the horizontal synchronization signal (H3YNC)
Which of 82,..., H3n is uLo first?
, monitors whether the level has reached n level, and during that one horizontal scanning period,
Which latch circuit makes the sampled video data valid, that is, 5-VDI.

5-VD2. . . , 5-VDn, which is output as sampling video data (S-VD) is the control circuit 1 described above.

In the control circuit 1 configured as shown in FIG. 2, the sampling clocks CLKL, 2. ..., n receives the sample values H31, H32, ..., H8n sampled by the latches 3 a, 3 b, ..., 3n, and among these, the first one receives the 11 L Ow" level. The latches 4a, 4b correspond to the sample values that have become.

..., 4n, and sends the drive signal OEi to the latch 4a.

4 b, ..., 4 n to S-V D 1 , S
-V D 2,----.

5-VDn sampling video data 5
-Control to output as VD.

In addition, whether or not sampling can be performed reliably with the valid sampling clock during the horizontal scanning period depends on the frequency error and stability between the bit clock of the video information source and the sampling clock, but it is possible to increase the number of sampling clocks n. It will be shown below that the sampling clock margin for video data can be increased by doing this.

FIG. 4 shows the output signal (H5Y
12 is an operation timing chart of the sampling circuit when n = 3 (NC, VD) and n = 3. H3YNC is sampled with clocks CLKI and 2.3 respectively, and the sampling clock whose sample value reaches the IZLoν" level first is made valid during that one horizontal scanning period, and video data is sampled with that clock. In FIG. 4, since the sample value HS2 reaches the LL L ol, II+ level first, CLK2 is enabled during the horizontal scanning period and video data is being sampled.

Next, a comparison between n=3 and n=5 is shown in FIG. First, when n=3, in sampling H3YNC using CLK2, if the sampling point P is located within the period Ta, CL during that one horizontal scanning period
K2 becomes valid. At this time, the sampling point Q for the video data is also located within the period TcL, and the left and right margins ML and MR for the video data are as shown in the figure.

On the other hand, when n=5, H3YNC by CLK2
In sampling, when the sampling point R is located within the period Tb, the sample value H32 of H3YNC becomes the "Lo" level before the other sample values. At this time, if the control circuit is set to sample the video data by validating the next clock (in this case, CLK3) as the sampling clock during one horizontal scanning period, the sampling point S of CLK3 for the video data is as follows. It is located within the period Tb, and the left and right margins ML' and MR' are as shown in the figure.

Obviously, ML'>ML, and n=5 is less likely to cause a sampling error due to instability of the sampling clock and video data.

Effects As described above, according to the present invention, in a circuit for sampling video data that is the output of a video information source controlled by a synchronization signal of a unique frequency, the circuit has a frequency corresponding to each of the video information sources. Means for generating a plurality of bit clocks, means for selecting one of the bit clocks, and means for generating a plurality of clocks having the same frequency and different phases as each of the plurality of bit clocks,
The horizontal synchronizing signal of the video information source is sampled by a plurality of clocks generated from the plurality of clock generation means corresponding to the P1-clock generation means of the frequency selected by the selection means, and the horizontal synchronization signal of the video information source is sampled from among the plurality of clocks. The video signal sampling circuit is configured to determine a sampling synchronization signal and sample video data using the sampling synchronization signal, so that it can be constructed with a simple circuit configuration without using an expensive PLL circuit. This has the remarkable effect of realizing the following.

[Brief explanation of the drawing]

Figure 1 is a block configuration diagram of a sampling circuit showing an embodiment of the present invention, Figure 2 is a block diagram showing the detailed configuration of a control circuit which is the main part, and Figures 3 (a) and (b) are sampling circuits. 4 and 5 are operation timing charts of the sampling circuit, and FIG. 6 is a diagram showing an example of the configuration of a video information processing system to which the present invention is applied. 1: Control circuit, 2: Sampling clock generation circuit, 3
a to 3n, 4a to 4n: latch circuit, 20: video data sampling circuit, 21a to 21n: video information source,
22: memory, 23: mixer, 24: cRT. Figure 1 a Figure 2 Figure 6 Procedural amendment. ,. ! ¥3'863''''-11B 1985 Patent Application No. 56955 3, Relationship with the case of the person making the amendment Patent applicant r4 table (name) (674) Rico Co., Ltd. - Representative Hama 1) Hiro 4, Agent 5, number of inventions increased by amendment: 1
) The description in the "Detailed Description of the Invention" column is amended as follows. 1) Page 8, lines 17-18 “Sampling Point P”
is corrected as "the falling edge of rH3YNC". 2) Page 9, lines 5-6 F sampling point R”
The fall of rH3YNc is corrected. (2) “Drawings” shall be amended as follows. 1) Correct Figure 5 to the attached one.

Claims (1)

[Claims] (1) In a circuit for sampling video data that is the output of a video information source controlled by a synchronization signal of a unique frequency, means for generating a plurality of bit clocks having a frequency corresponding to each of the video information sources; means for selecting one of the plurality of bit clocks, and means for generating a plurality of clocks having the same frequency and different phases as each of the plurality of bit clocks, the bit clock generation means having the frequency selected by the selection means; By a plurality of clocks generated from the corresponding plurality of clock generation means,
sampling a horizontal synchronization signal of the video information source;
A video signal sampling circuit characterized in that a sampling synchronization signal is determined from among the plurality of clocks, and video data is sampled using the sampling synchronization signal.