KR100205606B1 - Port read circuit using vertical synchronous signal - Google Patents

Abstract

The present invention relates to a port read circuit that can receive data from an input port using a vertical synchronization signal of a graphics controller. The present invention relates to an MPEG decoder 15 from an MPEG controller 10 of a graphics controller. A port enable for outputting a second enable signal (giox) to the input port 25 by receiving the vertical synchronization signal (Hsync) and the first enable signal (gport_enx) output from the port control unit 20 is output as A signal output unit; The port input data data1 received from the second enable signal giox and the input port 25 is received to latch the port input data data1 in response to a predetermined clock signal CLK. A port input data output unit for outputting to the control unit 20; MPEG enable which receives the MPEG enable signal mpeg_enx and the second enable signal giox output from the MPEG controller 10 and outputs a third enable signal mpeg_oex to the MPEG decoder 15. The MPEG data is input during the vertical driving period including the signal output unit, and the data of the other input port is received in the other sections.

Description

Port Lead Circuit Using Vertical Synchronization Signal

The present invention relates to a port read circuit, and more particularly, to a pod read circuit that can receive data from an input port using a vertical synchronization signal of a graphics controller.

1 is a timing diagram illustrating a process in which MPEG data is read in a vertical synchronization section in a conventional graphics controller.

Referring to FIG. 1, there is a National Television System Committee / Phase Alteration by Line (NTSC / PAL) as a representative format for displaying Motion Picture Experts Group (MPEG) data. In these formats, data is not continuously input, but MPEG data is valid only between vertical synchronization signals Hsync.

On the other hand, if you want to use a game port while displaying MPEG data, the graphics controller must have two ports for MPEG and a game port. Currently, MPEG data and input from a game port are processed through one port. Therefore, in this case, it is impossible to use MPEG and game port at the same time. The disadvantage is that the pin count of the graphics controller increases too much to support two simultaneous inputs. In addition, the current graphics controller has a limitation in extending the number of pins to support all the existing graphics functions while simultaneously supporting the game port.

An object of the present invention has been proposed to solve the above problems, by using the characteristics of the MPEG to control the enable signal between the MPEG decoder and the other input port between the vertical dynamics to prevent mutual data collision and the other input port It is to provide a graphics controller having a port lead circuit that can receive the data of.

1 is a timing diagram illustrating a process in which MPEG data is read in a vertical synchronization section in a conventional graphics controller;

2 is a detailed circuit diagram of a port lead circuit using a vertical driving mechanism according to an embodiment of the present invention;

3 is a timing diagram according to the operation of the critical part shown in FIG.

* Description of the symbols for the main parts of the drawings *

10 MPEG control 15 MPEG decoder

20: game port control unit 25: game port

30: port lead circuit 32, 34, 38: logic circuit

36: latch portion

(Configuration)

According to a feature of the present invention for achieving the above object, the port lead circuit using a vertical synchronization signal: a vertical synchronization signal output from the MPEG controller of the graphics controller to the MPEG decoder and the first enable signal output from the port controller; A port enable signal output unit provided to output a second enable signal to an input port; A port input data output unit receiving the second enable signal and the port input data inputted from the input port and latching the port input data in response to a predetermined clock signal to output the port input data to the port controller; And an MPEG enable signal output unit configured to receive an MPEG enable signal and the second enable signal output from the MPEG controller and output a third enable signal to the MPEG decoder.

In this embodiment, the port enable signal output unit is configured to receive the vertical synchronization signal and the first enable signal and to perform a predetermined logic operation to output the second enable signal.

In this embodiment, the logic circuit portion is composed of an OR gate.

In an embodiment, the port input data output unit may include: a logic circuit unit configured to receive the second enable signal and the clock signal and perform a predetermined logic operation to output a latch clock; And a latch unit for latching the port input data and outputting the port input data to the port controller in synchronization with the latch clock.

In this embodiment, the logic circuit portion is composed of an OR gate.

In this embodiment, the MPEG enable signal output unit is composed of a logic circuit unit which receives the MPEG enable signal and the second enable signal and performs a predetermined logic operation to output the MPEG enable signal to the MPEG decoder.

In this embodiment, the logic circuit portion is composed of a NAND gate.

(Action)

According to the present invention as described above, the MPEG data is input during the vertical driving period, and the data of the other input port is received in the other sections.

(Example)

DETAILED DESCRIPTION Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a detailed circuit diagram of the port lead circuit using the vertical driving mechanism according to the embodiment of the present invention, and FIG. 3 is a timing diagram according to the operation of the important part shown in FIG.

As shown in FIG. 2, the port lead circuit 30 of the graphics controller according to the embodiment of the present invention includes a NAND gate 32, first and second ora gates 34 and 38, and a latch unit 36. It is configured to include, the operation of each part is as follows.

First, the first OR gate 34 is a vertical enable signal Hsync output from the MPEG controller 10 and a first enable signal gport_enx for enabling the game port output from the game port controller 20. Is provided to output a second enable signal (giox) to the game port (25).

The second OR gate 34 receives the output of the first OR gate 34 and a predetermined clock signal CLK and provides a game clock signal gCLK to the latch unit 36.

The latch unit 36 receives data from the game port 25 in synchronization with the game clock signal gCLK and outputs the data to the game port control unit 20.

The NAND gate 32 receives an MPEG enable signal (mpeg_enx) output from the MPEG controller 10 and an output of the first OR gate 34 to perform a NAND operation to perform an NAND operation on the MPEG decoder 15. A third enable signal mpeg_oex for outputting data is output.

Again, referring to FIGS. 2 and 3, the MPEG controller 10 and the game port controller 20 enable the MPEG enable signal when both the MPEG decoder 15 and the game port 25 are enabled. Both mpeg_enx and the first enable signal gport_enx are active low.

According to the present invention, since the actual video data of MPEG is not input in a section in which the vertical sync signal Hsync is at a low level, the third enable signal for enabling the MPEG decoder 15 when the manual sync signal Hsync is activated. Since the mpeg_oex is inactive, the data port is floated from the MPEG decoder 15 and the game port 25 is enabled to activate a second enable signal (giox). Allow the data of 25 to be driven.

More specifically, the clock signal CLK input from the outside is 27 MHz as a reference clock of MPEG. The most common format of MPEG is NTSC / PAL. NTSC is activated every 858 pixels and PAL is every 864 pixels. The vertical sync signal (Hsync) is activated.

In addition, the third enable signal mpeg_oex for enabling the MPEG decoder 15 is OR-operated with the first enable signal gport_enx and the vertical synchronization signal Hsync for enabling the game port 25. The signal is then NAND-calculated with the MPEG enable signal mpeg_enx and output to the MPEG decoder 15.

The second enable signal (giox) for enabling the game port 25 is generated by ORing the vertical synchronization signal (Hsync) and the first enable signal (gport_enx). The data line is shared by the MPEG decoder 15 and the game port 25, and the data line is floated according to each enable signal. The synchronization signal gCLK input to the latch unit 36 is a signal for latching data input from the game port 25 during a period in which the vertical synchronization signal Hsync is at a low level. The second enable signal (giox) and the clock signal (CLK) for enabling it can be obtained by OR operation.

According to the present invention as described above, since the input from the MPEG data and the game port can be input and processed according to the vertical synchronization section, respectively, there is an effect that the video output by the MPEG data and the game using the game port can be simultaneously performed.

Claims (7)

A vertical synchronization signal Hsync output from the MPEG controller 10 of the graphics controller to the MPEG decoder 15 and a first enable signal gport_enx output from the port controller 20 are provided to the input port 25. A port enable signal output unit configured to output a 2 enable signal (giox); The port input data data1 received from the second enable signal giox and the input port 25 is received to latch the port input data data1 in response to a predetermined clock signal CLK. A port input data output unit for outputting to the control unit 20; MPEG enable which receives the MPEG enable signal mpeg_enx and the second enable signal giox output from the MPEG controller 10 and outputs a third enable signal mpeg_oex to the MPEG decoder 15. A port lead circuit using a vertical drive section including a signal output section. The method of claim 1, The port enable signal output unit receives the vertical synchronization signal (Hsync) and the first enable signal (gport_enx) and performs a predetermined logic operation to output the second enable signal (giox) 34. Port lead circuit using a vertical dynamic section composed of. The method of claim 2, The logic circuit part 34 is a port lead circuit using a vertical driving mechanism composed of an ora gate. The method of claim 1, The port input data output unit receives a second enable signal (giox) and the clock signal (CLK) and performs a predetermined logic operation to output a latch clock (gCLK); And a latch unit (36) for latching the port input data (data1) and outputting the port input data (data1) to the port control unit (20) in synchronization with the latch clock (gCLK). The method of claim 4, wherein The logic circuit 38 is a port lead circuit using a vertical driving mechanism composed of an ora gate. The method of claim 1, The MPEG enable signal output unit includes a logic circuit unit 32 that receives the MPEG enable signal mpeg_enx and the second enable signal giox and performs a predetermined logic operation to output the MPEG enable signal to the MPEG decoder 15. Port lead circuit using vertical dynamic section. The method of claim 6, The logic circuit part 32 is a port lead circuit using a vertical driving mechanism composed of a NAND gate.