JPH0821615B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a method for forming an element isolation insulating film.

[Conventional technology]

A LOCOS method (Local Oxidation of Silicon :) that uses a silicon nitride film as an oxidation resistant mask to perform element isolation of various elements in an integrated circuit formed on a silicon substrate.
J. Apels et al., Phillips Research Report, Vol. 25, p. 118, 1970: JAppels et al, Philips Res Re
pt 25, 118 (1970)) have been used conventionally. However, in this method, when an oxide film as an element isolation insulating film is formed on a silicon substrate, oxygen rapidly diffuses under the silicon nitride film, which is an oxidation resistant mask, and oxidation progresses in the lateral direction. Then, it is known that an overhang having a pointed cross section (so-called bird's beak) is formed on the side surface of the element isolation insulating film. When such bird's beaks are formed, the active region (element formation region) on the silicon substrate is reduced as compared with immediately after patterning. Therefore, when this LOCOS method is used for manufacturing a dynamic memory, the active area is reduced due to the bird's beak, especially in the memory array portion, so that the capacitor area of the memory cell and the channel area cannot be sufficiently taken. For this reason, in such a dynamic memory, the amount of accumulated charge is reduced as the capacitor area is reduced, which causes a soft error and a narrow channel effect due to the reduction of the channel region.

Therefore, as an element isolation method replacing the LOCOS method, a trench isolation method has been proposed in which the element isolation insulating film has an isolation structure as shown in FIG. 7, for example. This 7th
The figure is a cross-sectional view of an element isolation insulating film formed by the trench isolation method disclosed in JP-A-60-124840. The element isolation insulating film having such a structure is first oxidized on the upper surface of the silicon substrate 1. The silicon film 2 and the silicon nitride film 3 are sequentially formed. After that, a groove 4 is formed, a silicon oxide film 5 is formed on the inner surface of the groove 4, and then the groove 4 is formed with polycrystalline silicon 6.
Fill in. Then, an element isolation structure is formed by flattening these surfaces using an etch back method or the like.

[Problems to be solved by the invention]

However, in the element isolation by the conventional trench isolation method, not only the complicated process of filling the trench 4 with the polycrystalline silicon 6 and further planarizing the surface as described above is required, but also the trench is formed in the silicon substrate 1. There is a problem that the formation of No. 4 causes strain in the silicon substrate 1, which causes the structure of the silicon single crystal to collapse and a leak current to easily occur at the corner portion 7 of the groove 4.

The present invention has been made to solve such a problem, and in forming an element isolation insulating film,
It is an object of the present invention to obtain a method for manufacturing a semiconductor memory device which can secure a wide active region and can achieve sufficient element isolation without requiring complicated steps.

[Means for solving problems]

A method of manufacturing a semiconductor memory device according to the present invention comprises forming a first element isolation insulating film for the memory array and a second element isolation insulating film for the peripheral circuit on a semiconductor substrate, Only the upper surface portion of the first inter-element isolation insulating film is selectively etched, and a voltage lower than the power supply voltage is applied to at least a part of a region including the first inter-element isolation insulating film and its vicinity. To form a capacitor electrode,
A gate electrode to which a voltage higher than the power supply voltage is applied is formed on the second element isolation insulating film.

[Action]

In this invention, since the upper surface portion of the element isolation insulating film formed by the LOCOS method or the like is removed by etching, the bird's beak length of the element isolation insulating film is shortened, and the active region is expanded accordingly. become. Further, the formation of the inter-element isolation insulating film before etching is not particularly limited, and since the LOCOS method or the like may be adopted, the whole process of forming the inter-element isolation insulating film is not complicated, and the trench isolation method can be used. There is no decrease in the element isolation capability due to the strain at the time of forming the groove.

〔Example〕

FIG. 1 is a sectional view showing an embodiment of a method of manufacturing a semiconductor memory device according to the present invention. This embodiment shows a case where a memory array section of a dynamic RAM and its peripheral circuit section are formed on a semiconductor substrate 1 of P-type silicon.

In this method, first, the silicon oxide film 2 is formed on the semiconductor substrate 1 by thermal oxidation or the like, and the silicon nitride film 3 is formed on the upper surface thereof by the CVD method. Then, a part of the silicon nitride film 3 is selectively etched, and boron is injected from the etched opening 3a to form a P ⁺ diffusion layer 8 for preventing inversion on the semiconductor substrate 1 below the opening 3a. Formed (FIG. 1 (a)).

Next, using the silicon nitride film 3 as an oxidation resistant mask, an oxide film to serve as the element isolation insulating film 9 is formed in the opening 3a by LOCOS.
It is formed by the method (FIG. 1 (b)). The steps up to this point are the same as in the normal LOCOS method, and bird's beaks B extend to the formed inter-element isolation insulating film 9 to form the silicon nitride film 3 formed in the step shown in FIG. The element isolation length l _B is longer than the patterning length l _O.

Then, the uppermost silicon nitride film 3 is entirely removed by etching, and then a resist 10 is applied. By patterning, only the resist 10 existing on the upper surface of the peripheral circuit portion is left (the left side portion of FIG. 1C). Then, the silicon oxide film 3 on the entire surface of the memory array portion and the upper surface portion of the element isolation insulating film 9 are removed by etching to form a thin element isolation film as indicated by 9a in FIG. 1 (c). . As a result, the film thickness of the element isolation insulating film 9a in the memory array section becomes smaller than the film thickness of the element isolation insulating film 9 remaining in the peripheral circuit section. Further, since the tip portion of the bird's beak B is removed due to such a decrease in film thickness, the element isolation length l _B of the initial element isolation insulating film 9 (FIG. 1 (b)).
However, the element isolation length l of the element isolation insulating film 9a after etching is shortened, and the active region C in the memory array portion is expanded.

Next, after the resist 10 in the peripheral circuit portion is removed, in order to form a so-called high see structure in the capacitor portion D of the memory cell in the memory array portion, boron and arsenic are selectively formed in the region including the element isolation insulating film 9a. Is injected into. As a result, as shown in FIG. 1 (d), the P ⁺ diffusion layer 11
And N ⁺ diffusion layers 12 are formed respectively. However, the P ^{+ type} diffusion layer 11 is integrated with the P ^{+ type} diffusion layer 8 formed in the memory array portion in FIG. 1 (c). At this time, if the boron implantation energy is set high, the element isolation insulating film 9a which is thinned by etching in the step of FIG.
Boron injected from the upper surface side of this is the element isolation insulating film.
It easily penetrates through 9a and reaches the P ^{+ type} diffusion layer 8. For this reason, the impurity concentration of the inversion prevention P ⁺ diffusion layer 8 under the element isolation insulating film 9a becomes higher than the initial concentration, so that the element isolation capability of the thinned element isolation insulating film 9a is increased. Will be done.

After that, the gate oxide film 13 is further formed in the memory array section.
Is formed, the capacitor electrode 14 is selectively formed in at least a part of the region including the element isolation insulating film 9a and the vicinity thereof to form the capacitor section D.

Then, as shown in FIG. 1 (e), a gate oxide film 15 is formed over the memory array portion and the peripheral circuit portion,
Then, the transfer gate 16a in the memory array portion and the gate electrode 16b in the peripheral circuit portion are formed. After that, the N ⁺ diffusion layer 17 for source / drain is formed by ion implantation or the like.

Next, as shown in FIG. 1 (f), an oxide film 18 is formed in the entire area extending from the memory array portion to the peripheral circuit portion, and the oxide film 18 is selectively etched to form a contact hole 19 at a predetermined position. Then, the aluminum wiring 20 is formed.

FIG. 2 shows a plan view of a semiconductor device obtained by such a process, and a sectional view taken along the line AA of FIG. 2 corresponds to FIG. 1 (f). However, in Figure 2, aluminum wiring
Twenty etc. are omitted.

FIG. 3 is a graph showing experimentally measured results of the relationship between the bird's beak length and the film thickness of the element isolation insulating film 9a formed in the memory array portion by the above-mentioned process. It shows the case where the initial film thickness t _OX of the element isolation insulating film 9 before etching is 0.50 μm and 0.75 μm, respectively. As is clear from the figure, even if the element isolation insulating film 9a left after etching has the same film thickness,
The thicker the initial film thickness t _OX, the shorter the bird's beak. When the initial film thickness t _OX is 0.75 μm (II), if the film thickness after etching is 0.24 μm, the bird's beak length can be made almost zero.

According to FIG. 3, bird's beaks are reduced as the film thickness is reduced by etching, but on the other hand, if the film thickness is too thin, the element separation capability deteriorates. Therefore, it is necessary to set the lower limit of the film thickness. 4 and 5 show the threshold voltage and isolation of the element isolation transistor (parasitic transistor generated near the element isolation insulating film) when the back gate bias V _B is (−3) V and 0V, respectively. It is a graph showing the relationship of length for each film thickness. In the figure, I, II, and III are film thickness t _OX of 0.13 μm and 0.20 μm, respectively.
The case of m and 0.32 μm is shown. As is clear from FIG. 4, when the back gate bias V _B is (−3) V, the threshold voltage is 12 V or higher for any film thickness, and sufficient separation performance can be secured. On the other hand, if the back gate bias V _B is O [V], the fifth
As shown in the figure, the film thickness of the element isolation insulating film is 0.13 μm.
In the case of I in the figure, the threshold voltage is about 6V.
In the case of the dynamic memory applied in this embodiment,
In the peripheral circuit part of FIG. 1 (f), the gate electrode 16b to which a power supply voltage (5 V) or more is applied is connected to the element isolation insulating film 9 while the element isolation isolation of the memory array part is connected. Since the structure is such that the capacitor electrode 14 (so-called cell plate), which is applied only half the power supply voltage (2.5V) to 0V, is connected on the film 9a, the isolation withstand voltage of 5V or more in the memory array portion is sufficient. .

Therefore, in the memory array portion where it is necessary to make the channel width and the capacitor area wide as in the embodiment, while the inter-element isolation length is shortened by adopting the thin inter-element isolation insulating film 9a that is etched, By adopting the inter-element isolation insulating film 9 which is not etched after being formed by the LOCOS method, in the peripheral circuit portion where a high voltage is applied, the channel width is sufficiently wide and there is almost no problem such as a narrow channel effect, Both the peripheral circuit section and the memory array section can be provided with an element isolation capability suitable for the sensor.

FIG. 6 shows respective narrow channel effects in the case of isolation between elements (shown by a solid line in the figure) by the manufacturing method of the embodiment and conventional (normal LOCOS method) element isolation (shown by a broken line in the figure). 3 is a graph comparing and showing a case where the channel length L = 10 μm and a case where L = 1.5 μm. The channel width on the horizontal axis is the channel width set on the mask used to form the silicon nitride film 3 of FIG. 1 (a). As is clear from this figure, in the embodiment, even if the channel width set on the mask is small, the threshold voltage of the transistor included in the memory cell does not increase so much and the element isolation according to the embodiment It can be seen that the narrow channel effect is significantly suppressed by. This is because, in the conventional element isolation, the channel width becomes substantially narrow due to the influence of the bird's beak described above, whereas the bird's beak can be made small in the embodiment.

In addition, in the above-mentioned embodiment, the case where the P-type silicon substrate is used as the semiconductor substrate 1 is shown, but it is needless to say that the same can be applied to the case where the N-type silicon substrate is used. It is also applicable to element isolation of complementary transistors. Further, the present invention can be applied not only to the dynamic type memory but also to all semiconductor devices which are required to secure a sufficient active region. Birds Beak is LOCOS
However, even if another inter-element isolation insulating film forming method is used, the insulating film that is laterally overhanged should be the subject of the present invention. You can

〔The invention's effect〕

As described above, according to the present invention, since the bird's beak length is shortened by etching the upper layer portion of the inter-element isolation insulating film, the active region can be formed without a complicated process such as a trench isolation method. There is an effect that it is possible to obtain a method for manufacturing a semiconductor memory device that can be widely secured and have sufficient element isolation.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a method for manufacturing a semiconductor device according to the present invention, FIG. 2 is a plan view of the semiconductor device, and FIG. 3 is a bird's beak of an element isolation insulating film in the semiconductor device. Graphs showing the relationship between the length and the film thickness, and FIGS. 4 and 5 show that the back gate bias is (−
3) A graph showing the relationship between the threshold voltage of the parasitic transistor in the element isolation region and the isolation length in the case of V and 0 V. FIG. 6 shows the element isolation according to the embodiment and the element isolation according to the conventional manufacturing method. FIG. 7 is a cross-sectional view showing a comparison between the narrow channel effects in the case, and FIG. 7 is a conventional manufacturing method. In the figure, 1 is a semiconductor substrate, and 9 and 9a are element isolation insulating films. In the drawings, the same reference numerals indicate the same or corresponding parts.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location 7735-4M H01L 27/10 681 F

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor memory device in which a memory array and peripheral circuits are formed on a semiconductor substrate, wherein a first element isolation insulating film for the memory array and the periphery are formed on the semiconductor substrate. A second element isolation insulating film for a circuit is formed, and only the upper surface portion of the first element isolation insulating film is selectively etched, and the first element isolation insulating film and its vicinity are included. A capacitor electrode to which a voltage lower than the power supply voltage is applied is formed in at least a portion above the region, and a gate electrode to which a voltage higher than the power supply voltage is applied is formed on the second element isolation insulating film. A method of manufacturing a semiconductor memory device, which comprises forming the semiconductor memory device. 2. The etching step, wherein, after the etching is completed, the first inter-element isolation insulating film is applied to a region including the first inter-element isolation insulating film from an upper surface side of the first inter-element isolation insulating film. Impurities of the same conductivity type as that of the semiconductor substrate and impurities of a conductivity type opposite to that of the semiconductor substrate are selectively implanted so as to penetrate through the isolation insulating film and reach an underlying semiconductor region. Claim 1 characterized by including the process of
13. The method for manufacturing a semiconductor memory device according to item 13.