JP2876670B2 - Manufacturing method of nonvolatile semiconductor memory device - Google Patents

Description

The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device,
In particular, the present invention relates to a method for manufacturing a nonvolatile semiconductor memory device having a two-layer gate electrode transistor.

[Conventional technology]

The most common structure of nonvolatile semiconductor memory devices is
It has a structure in which a two-layer gate electrode transistor having a floating gate electrode is used as a memory transistor, and a typical one is an EPROM. As a manufacturing method for highly integrating such a memory device, there is a digest of technology paper, 1986 VLSI symposium (Digest o).
f Tecnology Paper, 1986 VLSI SYMPOSIUM), page 87. According to this method, an element isolation region is formed by embedding an insulating film in a groove formed by etching a predetermined region of a semiconductor substrate.

FIG. 3 shows a conventional method obtained by further improving this manufacturing method. Hereinafter, this manufacturing method will be described with reference to FIGS.
This will be described with reference to FIG.

For example, a first gate insulating film 2 made of, for example, silicon oxide (hereinafter referred to as SiO ₂ ) is formed on a predetermined region on a semiconductor substrate 1 made of Si. Further, a first polycrystalline silicon film 3, for example, a second gate insulating film 2 made of SiO ₂ or the like is formed. Further, a first polycrystalline silicon film 3, for example, Si
A _second gate insulating film 4 made of O ₂ or the like, a second polycrystalline silicon film 5, and a silicon nitride film 6 are sequentially stacked. afterwards,
A patterning mask 7 such as a resist, for example, is formed so that only a portion serving as an element isolation region is exposed (FIG. 1A).

With this mask, the silicon nitride film 6, the second polycrystalline silicon film 5, the second gate insulating film 4, the first polycrystalline silicon film 3, and the first gate insulating film 2 are sequentially and selectively etched, The surface of the substrate is exposed, and the substrate is etched in a groove shape. As these etching techniques, anisotropic etching such as RIE is generally used in order to reduce the dimensional deviation. Then, for example, decompression CV
Interlayer insulating film 8 of good shape such as silicon oxide film by D
Is deposited so as to cover the wall of the groove (FIG. 1 (b)),
Next, the third polycrystalline silicon film 10 is buried in the trench.
Is grown (FIG. 1 (c)).

Then, the third polycrystalline silicon film 10 is etched back, and the exposed interlayer insulating film 8 having good shape is etched to expose the surface of the silicon nitride film 6. Next, when the surface of the third polycrystalline silicon film 10 remaining in the groove is oxidized, the oxidation-resistant silicon nitride film 6 is not oxidized, and the silicon oxide film 11 is formed only in the element isolation region.

Next, only the silicon nitride film 6 is etched to expose the surface of the second polycrystalline silicon film 5 (FIG. 3E). Next, a fourth polycrystalline silicon film 12 is deposited, and a patterning mask 13 is formed (FIG. 3 (f)).

Thereafter, using known techniques, patterning of each gate electrode, formation of source / drain regions 14 by introducing impurities, formation of an interlayer insulating film 15, opening of contact holes 17, and formation of metal wirings 16 are performed. A nonvolatile semiconductor memory device as shown in FIG. 3 (g) is obtained.

[Problems to be solved by the invention]

According to the conventional method for manufacturing a nonvolatile semiconductor device described above, the polycrystalline silicon film embedded in the trench of the element isolation region is not in direct contact with the substrate and is electrically floating. As a result, a high voltage is applied between the source and drain during programming of the memory cell, and even if holes are injected into the polycrystalline silicon film in the isolation region, the polycrystalline silicon film in the isolation region is directly Since it is not in contact with the substrate, the potential of the element isolation region rises and the threshold voltage of the parasitic MOS transistor falls. For this reason, there is a disadvantage that adjacent diffusion layers are brought into a conductive state.

[Means for solving the problem]

According to the present invention, a first gate insulating film, a first polycrystalline silicon film, a second gate insulating film, a second polycrystalline silicon film, and a silicon nitride film are sequentially stacked on a semiconductor substrate of one conductivity type. And selectively removing the silicon nitride film, the second polycrystalline silicon film, the second gate insulating film, the first polycrystalline silicon film, and the first gate insulating film in predetermined regions, Forming a trench for element isolation by etching the substrate in the predetermined region; and growing third polycrystalline silicon doped with an impurity of one conductivity type so as to fill the inside of the trench. Etching the crystalline silicon film until the surface of the silicon nitride film is exposed, oxidizing the surface of the remaining third polycrystalline silicon film to form an element isolation structure, and forming the second polycrystalline silicon film. Until the surface is exposed, Etching a silicon nitride film, forming a fourth polycrystalline silicon film in ohmic connection with the second polycrystalline silicon film, and forming a fourth region of the fourth polycrystalline silicon film in a predetermined region; Forming a stacked gate structure by sequentially and selectively removing the second polycrystalline silicon film, the second gate insulating film, the first polycrystalline silicon film, and the first gate insulating film; Is a method for manufacturing a nonvolatile semiconductor memory device including:

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIGS. 1A to 1G are sectional views of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.
FIGS. 1 (a) and 1 (b) show a conventional example.
Same as (b).

Here, 1 is a semiconductor substrate made of, for example, P-type Si, 2 is a first gate insulating film made of, for example, SiO _{2 having a} thickness of 20 nm, and 3 is a first gate insulating film of, for example, 200 nm thick doped with N-type impurities.
The polycrystalline silicon film 4 has a thickness formed by oxidizing the first polycrystalline silicon film 3 at a high temperature of at least 1150 ° C.
A second gate insulating film such as 20 nm of SiO ₂ , 5 a second polycrystalline silicon film with a thickness of 200 nm doped with N-type impurities, 6 a silicon nitride film with a thickness of 150 nm grown by CVD, for example, 7 is a patterning mask made of, for example, a resist, 8 is an interlayer insulating film having a good shape such as SiO ₂ grown by, for example, low-pressure CVD, 9 is an element anisotropically etched by, eg, RIE with a depth of 0.8 μm The groove. The manufacturing method up to FIG. 1B is the same as the conventional method. 1B and thereafter, the interlayer insulating film 8 having good shape is etched back by anisotropic etching such as RIE so that the bottom of the groove and the surface of the silicon nitride film 6 are exposed. Thereafter, for example, a third polycrystalline silicon 10 doped with a P-type impurity is grown to a thickness of 1 μm (FIG. 1C). Next, the third polycrystalline silicon film 10 is etched back until the surface of the silicon nitride film 6 is exposed.
(FIG. 1 (d)). Next, a thick SiO ₂ film 11 is selectively formed only on the element isolation region, for example, for 600 n.
m is formed (FIG. 1 (e)). Thereafter, the silicon nitride film 6 is removed by etching, and a fourth polycrystalline silicon film 14 capable of making ohmic contact with the second polycrystalline silicon film 5 is grown, for example, to a thickness of 200 nm (FIG. 1 (f)). The following is obtained using the well-known technique as in the conventional example, as shown in FIG. 1 (g). According to the conventional example, an element isolation structure in which the polycrystalline silicon film embedded in the element isolation trench is not in direct contact with the substrate cannot be obtained. The trench for element isolation can be filled with a polycrystalline silicon film which is doped and is in direct contact with the substrate.

2 (a) to 2 (c) are sectional views of a semiconductor chip shown in the order of steps for explaining a second embodiment of the present invention.

After steps similar to those described with reference to FIGS. 1A to 1E of the first embodiment, the silicon oxide film 11 is etched back until the surface of the second polycrystalline silicon film is exposed. (FIG. 2A). Thereafter, a silicide layer 18 made of WSi or the like having a thickness of, for example, 150 nm is formed (FIG. 2B).
Thereafter, it is manufactured in the same manner as in the first embodiment using a known technique,
The one shown in FIG. 2 (c) is obtained.

This embodiment has an advantage that the layer resistance of the control gate electrode can be reduced because a silicide layer having an electric resistance lower than that of poly-Si is laminated.

〔The invention's effect〕

As described above, the present invention provides a conventional example by forming an insulating film only on the side wall portion of a trench for element isolation and then filling the above-mentioned trench with a polycrystalline silicon film doped with an impurity of the same conductivity type as the substrate. In this way, it is possible to avoid an element isolation structure having a built-in polycrystalline silicon film in an electrically floating state.
Even if a high voltage is applied between the drains and holes are injected into the polycrystalline silicon film in the isolation region, the polycrystalline silicon film in the isolation region is in direct contact with the substrate and has the same conductivity type as the substrate. Therefore, the injected holes can escape to the substrate, which has an effect that the element isolation region is fixed at the potential of the substrate. As a result, the parasitic of the element isolation region
The threshold voltage of the MOS transistor does not change, and the adjacent diffusion layers do not become conductive. Therefore, there is an effect that isolation between elements of the nonvolatile semiconductor memory device can be surely performed.

[Brief description of the drawings]

1 (a) to 1 (g) are cross-sectional views showing steps in order to explain a first embodiment of the present invention, and FIGS. 2 (a) to 2 (c) show a second embodiment of the present invention. FIGS. 3 (a) to 3 (g) are cross-sectional views illustrating a conventional example in the order of steps for explaining the conventional example. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... 1st gate insulating film, 3 ... 1st polycrystalline silicon film, 4 ... 2nd gate insulating film, 5 ... 2nd
6, a silicon nitride film; 7, a patterning mask; 8, an interlayer insulating film having good shape; 9, an etching groove; 10, a third polycrystalline silicon film; 11, a silicon oxide film; ... 4th polycrystalline silicon film, 13 ... patterning mask, 14 ... impurity diffusion layer, 15 ... interlayer insulating film, 16
... metal wiring, 17 ... contact hole, 18 ... silicide layer.

Claims (1)

(57) [Claims] 1. A first gate insulating film, a first polycrystalline silicon film, a second gate insulating film, a second polycrystalline silicon film, and a silicon nitride film are sequentially laminated on a semiconductor substrate of one conductivity type. And selectively removing the silicon nitride film, the second polysilicon film, the second gate insulating film, the first polysilicon film, and the first gate insulating film in predetermined regions. Forming a groove for element isolation by etching the substrate in the predetermined region; forming an insulating film on the groove and the silicon nitride film; and insulating the side surface of the groove by anisotropic etching. Exposing the substrate and the silicon nitride film by removing the insulating film on the bottom of the trench and the silicon nitride film while leaving a film, and a step of doping one conductivity type impurity so as to fill the trench. 3 polycrystalline silicon After growing a capacitor, etching the third polycrystalline silicon film until the surface of the silicon nitride film is exposed, and oxidizing the surface of the remaining third polycrystalline silicon film to form an element isolation structure. And until the surface of the second polycrystalline silicon film is exposed.
Etching the silicon nitride film; and forming a fourth ohmic connection with the second polycrystalline silicon film.
Forming the polycrystalline silicon, and the fourth polycrystalline silicon film, the second polycrystalline silicon film, the second gate insulating film, the first polycrystalline silicon film, and the Selectively removing the first gate insulating film sequentially to form a stacked gate structure.