JPH0821553B2 - Multiple spreading method - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a multiple diffusion method in which impurity diffusion is performed a plurality of times by sharing a diffusion mask (hereinafter referred to as self-alignment), and more particularly, self-alignment double diffusion. Lateral pnp
The present invention relates to a transistor diffusion method.

[Background of the Invention]

For the self-aligned double-diffused lateral pnp transistor, which has a withstand voltage of 350 V and requires a high h _FE (current amplification factor) and f _T (gain bandwidth product), see the 16th (1984 Internat.
ional) “Solid Equipment and Materials Conference (Conf.on Solid Sta
"High-performance high-voltage lateral pnp transistor" by Sugawara et al. (A High
Performance High Voltage Lateral pnp Transistor)
Is discussed in the literature.

However, although the cross-sectional structure was discussed there, no consideration was given to the planar structure.

Here, the characteristics of the self-aligned double diffusion lateral pnp transistor will be described.

FIG. 4 shows a schematic sectional view of a conventional lateral pnp transistor. This is because the p-type emitter (p-type) is formed in the n-type semiconductor region 101 in which the n ⁺ buried layer 100 is formed by impurity diffusion such as boron.
_E ) 104 and p collector (p _C ) 105 are formed, and then n base contact layer (n _BC ) 1 is formed by diffusion of impurities such as phosphorus.
After forming 06, electrodes 12, 13, 14 are further formed
It is a pnp transistor.

With this pnp transistor, p _E −p _C
It is necessary to increase the _space dimension (W _nB ). When the dimension W _nB is reduced, the current amplification factor h _FE and the gain bandwidth product f _T can be increased, but on the other hand, there is a problem that the breakdown voltage is lowered due to punch through.

Therefore, the structure shown in FIG. 4 has a difficult structure to obtain a transistor having high breakdown voltage, high h _FE and high f _T.

FIG. 5 shows a schematic sectional view of a self-aligned double-diffused lateral pnp transistor.

This transistor has p _E 104, p _C 105, n _BC 106 in the n-type semiconductor region 101 in which the n ⁺ buried layer 100 is formed as in FIG.
Are formed.

Structural features include a high concentration of n ⁺ base (n ⁺ _B ) 103 surrounding p _E , and between n ⁺ _B 103 and p _C , p _C
The p ^- collector layer (p _C ) 102 having a slightly lower impurity concentration may be provided.

n ⁺ _B 103 is to prevent punch through, and also p ^- _C 1
02 is for narrowing the base width between p _{E and} p _C and for relaxing the electric field. By these, a narrow base is formed to secure high breakdown voltage, high h _FE and high f _T.

Since impurities for forming p _E 104 are introduced from the same opening 11A of the oxide film 11 used for forming n ⁺ _B 103, the one shown in FIG. 5 is self-aligned double diffusion. It is called a lateral pnp transistor.

However, the self diffusion type double diffusion lateral pn
In the p-transistor, the distance from the diffusion end of n ⁺ _{B to} the diffusion end of p _E , that is, the n _B width is likely to vary, and there is a possibility that the breakdown voltage may be reduced due to punch through.

 The reason will be described below.

A method of forming n ⁺ _B and p _E of the self-aligned double-diffused pnp transistor shown in FIG. 5 will be described with reference to FIG. (1) of the same figure shows a cross section of n ⁺ _B and p _E and a perspective view from the upper right.

Opening 1 of oxide film 11 formed on the surface of semiconductor region 101
Phosphorus is diffused from 1A to form n ⁺ _B 103, and then an oxide film is formed.
Boron is diffused from the same opening 11A of 11 to form p _E 104.

6 (2) is a sectional view taken along the line XX ′ perpendicular to the straight line portion 120 of the opening 11A, and FIG. 6 (3) is taken along the line YY ′ of the corner portion 121 of the opening 11A. FIG.

As can be seen from the comparison between (1) and (2) in FIG. 6, in the linear portion 120 and the corner portion 121 of the pattern of the opening 11A, phosphorus of the same concentration is diffused to form n ⁺ _B 103. If
Diffusion spreads differently.

That is, considering the amount of impurities per unit volume, the impurities are diffused in a single plane in the straight line portion 120. However, in the corner portion 121, since the impurities are diffused in a 1/4 spherical shape, the diffusion spread of n ⁺ _B 103 is larger in the straight portion than in the corner portion. That is, in FIG. 6 (2) and (3), L _nx > L _ny .

Next, boron is diffused through the opening 11A of the same oxide film 11 to form p _E 104. At this time, if there is no change in the size and shape of the opening 11A of the oxide film, then L _px > L _py as described above.
Becomes Therefore, it is the difference of diffusion spread
The n _B width of the corner portion is narrower than that of the straight portion.

That is, in FIG. 6 (2) and (3), W _nBx > W _nBy
Is. Therefore, the corner portion is more likely to affect the punch-through than the straight portion.

Further, if the oxide film is side-etched before boron diffusion, W _nBy becomes further smaller, and punch-through easily occurs at this portion.

According to the trial production results of the present inventors up to now, the breakdown voltage is 10 to 35.
The variation was in the range of 0V, and the yield was also very poor.

As described above, the self-aligned double diffusion lateral pn
There is a problem to be solved in the planar structure of the p-transistor.

[Object of the Invention]

The object of the present invention is to provide a self diffusion type double diffusion lateral.
In a pnp transistor, it is an object of the present invention to provide a pattern structure in which a necessary n base width is secured and a breakdown voltage is prevented from being lowered by punch through even if the side etching amount at the self-line photo etching for forming p _E varies.

[Outline of Invention]

A feature of the present invention is that when multiple diffusion is performed by sharing the opening of the diffusion mask, the mask opening in the bending portion is selected to be smaller during the subsequent diffusion processing than during the previous diffusion. This is because the n-base width in each part is narrower than that in the other parts and punch-through is prevented.

Example of Invention

 The first embodiment of the present invention will be described below with reference to FIG.

In the method of manufacturing a pnp transistor according to the present invention, first, n
P ^- _C 102 is formed by boron diffusion in the semiconductor region 101 of the shape, and then by phosphorus diffusion from the opening 114 of the oxide film 11 (including the dotted line portion under the oxide film 113, that is, in the absence of the oxide film 113). form n ⁺ _B 103.

Next, with the self-alignment photo, the oxide film 113 is left in the bent portion or the corner portion of the opening portion 114 of the oxide film when n ⁺ _B 103 is formed, and the effective opening area is reduced from the opening portion.
Boron diffusion forms p _E 104. Further, p _C 105 is obtained from the opening 115 of the oxide film 11 and n _{BC is obtained} from the opening 116 of the oxide film 11 _.
106 are formed respectively.

Obviously, features of this embodiment, the corner portion of the n _BC 103, without applying the self-alignment technique in the strict sense, the mask opening during boron diffusion mask during the previous phosphorus diffusion The point is narrower than the opening.

FIG. 3 is a partial cross-sectional perspective view of the second embodiment of the present invention.

In the method of manufacturing the pnp transistor according to the present embodiment, as in the first embodiment, p ^- _C 102 is formed in the n-type semiconductor region 101 by boron diffusion, and then n ⁺ _B 103 is formed by phosphorus diffusion.
To form.

Next, as shown in the figure, the oxide film when n ⁺ _B 103 was formed
A new opening is formed in which the oxide film 113 remains at the corner of the opening 114 of 11 and boron is diffused from this opening to p _E 10
Forming 4 Further, p _C 105 and n _BC 106 are formed from the openings 115 and 116 of the oxide film 11.

The feature of the second embodiment is that the mask opening at the time of boron diffusion is
Before that, the oxide film 113 was left in the corner portion of the oxide film opening 114 at the time of phosphorus diffusion, so that the operating region was made wider (peripheral length of the emitter was longer) than in the first embodiment. is there.

FIG. 2 is a diagram showing a distribution of collector-emitter breakdown voltage BV _CEO of a transistor to which the manufacturing method of the present invention is applied.

It can be seen that a transistor with higher withstand voltage (about 350 V) and less variation can be developed compared to the case where the complete self-alignment method is applied to the diffusion of n ⁺ _B 103 and p _E 104.

In addition, the p _E operating region is narrower than the case where the self line is applied to the entire circumference of n ⁺ _B , but h _FE , f _T, etc. have no practical problems.

Similar results were obtained even if the oxide films 114 and 113 were left so that the corners of the openings 116 and 114 had a radius of curvature.

In the embodiments described above, the example of double spreading is described, but it will be apparent that the present invention can be applied to more multiple spreading.

〔The invention's effect〕

According to the present invention, the collector-emitter breakdown voltage is high,
Moreover, a lateral transistor with less variation can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional perspective view of a first embodiment of the present invention, FIG. 2 is a diagram showing a collector-emitter breakdown voltage distribution of a lateral transistor according to the present invention in comparison with a conventional method, and FIG. FIG. 4 is a sectional view of a conventional lateral structure pnp transistor, FIG. 5 is a sectional view of a self-aligned double-diffused lateral pnp transistor, and FIG. it is an illustration of a n ⁺ _B and p _E forming method of type double diffusion pnp transistor. 11,113 ... Oxide film, 100 ... n ⁺ buried layer, 101 ... n type single crystal silicon region, 102 ... P ^- _C region, 114 ... Oxide film opening, 103 ... n ⁺ base region, 104 …… p emitter region,
105 …… p collector area, 106 …… n base contact area

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shigeyuki Kawabata 4026 Kuji Town, Hitachi City, Ibaraki Prefecture Hitate Works Ltd., Hitachi Research Laboratory (72) Toshifumi Ohata 4026 Kuji Town, Hitachi City, Ibaraki Prefecture Nitate Works Co., Ltd. In Hitachi Research Laboratory (72) Inventor Hidetoshi Arakawa 3-10-2 Bentencho, Hitachi City, Ibaraki Hitachi Haramachi Electronics Co., Ltd. (56) References JP-B-44-23774 (JP, B1) JP-B-47- 4815 (JP, B1)

Claims (3)

[Claims] 1. A diffusion mask having an opening including both an opening end having a radius of curvature smaller than a predetermined value and an opening end having a curvature radius larger than the predetermined value is formed on a surface of a semiconductor substrate, and a part of the opening is shared. In the multiple diffusion method in which the semiconductor substrate is subjected to impurity diffusion a plurality of times, the opening edge having a radius of curvature less than a predetermined value in the mask used in the previous diffusion and its vicinity are opened by expanding the mask in the subsequent diffusion. And a mask opening is shared at the other opening ends. 2. The multiple diffusion method according to claim 1, wherein the diffusion is performed twice using different impurities. 3. The extension of the mask is set so that a diffusion edge distance from a diffusion edge of a diffusion layer formed first to a diffusion edge of a diffusion layer formed later is uniform. The multiple spreading method according to claim 1.