JPH03240271A - Manufacture of gto thyristor provided with insulated gate - Google Patents

Abstract

PURPOSE:To form a deep base layer of P-type without increasing the channel length, and enhance turn-off capability, by forming diffusion windows for a P-type base layer and an N-type emitter layer, at different positions, without influence of mask alignment deviation. CONSTITUTION:By one time photolithography process, diffusion windows for forming a P-type base layer 6 and an N-type emitter layer 7 are formed at different positions, without influence of mask alignment deviation. The diffusion window of the N-type emitter layer 9 in the vicinity of a gate 4, is used as a mask, and impurities for forming the P-type base layer 6 are introduced for doping; after the mask of the diffusion window of the N-type emitter layer 9 in the vicinity of the gate 41 is eliminated, impurities for forming the N-type emitter layer 7 are introduced for doping. As the result, a deep base layer of P-type is formed and the sheet resistance of the P-type base layer can be decreased without increasing the channel length.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a method of manufacturing a GTO thyristor with an insulated gate.

(Prior Art) The structure of a conventional general GTO thyristor with an insulated gate is shown in FIG. Note that the following description will be made assuming that the first conductivity type is the p type and the second conductivity type is the n type. In the conventional technique, impurities were doped through the same diffusion window using the gate electrode 4□ as a mask to form the P base layer 6 and the N emitter layer 9 in the channel forming portion.

In this manufacturing method, if a shallow n emitter layer is formed inside a deep p base layer in order to improve the current turn-off ability of the GTO thyristor with an insulated gate, the channel 15
The disadvantage is that the length increases, channel resistance increases, and turn-on ability decreases.

In the GTO thyristor with insulated gate, the general G
As with the TO thyristor, by increasing the amount of impurities in the p-base layer to lower the sheet resistance of the p-base layer, a larger current can be drawn from the base electrode at turn-off, resulting in a greater turn-off ability. However, if the amount of impurities in the P base layer is increased without changing the diffusion depth of the P base layer, the impurity concentration of the P base layer at the junction between the P base layer and the N emitter layer will increase, and the concentration of impurities in the P base layer will increase. The junction breakdown voltage of the n-emitter layer decreases, making it impossible to apply a high turn-off voltage to the base electrode during turn-off, resulting in a decrease in turn-off ability. It is necessary to form a deep p base layer so that the impurity concentration does not become high and the junction breakdown voltage does not decrease.

(Problem to be Solved by the Invention) In a GTO thyristor with an insulated gate, when the amount of current flowing through the channel becomes small during turn-on, the turn-on ability decreases6. Therefore, in the conventional manufacturing method, the GTO thyristor with an insulated gate In order to enhance the current turn-off ability of the thyristor, a shallow n layer is formed inside the deep p base layer 6.
Forming the emitter layer 9 has the drawback that the length of the channel 15 becomes longer, and as the channel resistance increases, the turn-on ability decreases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a GTO thyristor with an insulated gate, which eliminates the conventional drawbacks.

[Structure of the invention]

(Means for Solving Problem 11) The present invention enables diffusion windows for forming the P base layer 6 and the N emitter layer 7 at different positions to be formed in a single photolithography process without being affected by misalignment of masks. The diffusion window of the n emitter layer 9 near the gate 41 is masked and impurities for forming the p base layer 6 are doped.
The feature is that after removing the mask of the diffusion window of the n-emitter layer 9 near □, impurities for forming the n-emitter layer 7 are doped.

(Function) According to the manufacturing method of the present invention, the diffusion windows of the P base layer 6 and the N emitter layer 9 can be formed in different positions with high accuracy without being affected by misalignment of masks, so that the channel length can be reduced. Since it is possible to reduce the sheet resistance of the p base layer by forming a deep p base layer without increasing the length, it is possible to realize a GTO thyristor with an insulated gate that improves the turn-off characteristics without degrading the turn-on characteristics. You can.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a method of manufacturing a GTO thyristor with an insulated gate according to an embodiment of the present invention. In (a), a silicon oxide film is formed as a gate insulating film 3 on the n base layer 2 of a substrate having an n base layer 2 on the n emitter layer 1, and in (b), a silicon oxide film is formed as a gate insulating film 3. A polycrystalline silicon film 4 is deposited as a gate electrode material film through the film, and the polycrystalline silicon film is selectively etched to form a gate electrode 41 and a first masking agent 42 remaining in an island shape adjacent to the gate electrode 41. and the first mask material 42
A photoresist film is formed as a first masking agent 4.
□, a P base layer 6 is doped in the N base layer 2 by doping impurities using the second masking agent 5 and the gate electrode 41 as a mask.
In (c), the gate electrode 41 is masked with the third mask material 7 so as not to cover the second mask material 42, and the second mask material 4□ is removed. In (d), an n emitter layer 9 is formed in the p base layer 6 by doping impurities using the gate electrode 41 and the fourth mask material 8 as masks, and (e
), an insulating film layer 10, an anode electrode 11, a cathode electrode 12, and a base electrode 13 are formed to form a G with an insulated gate.
Manufacture TO thyristors.

Note that the method of the present invention can be applied to the GTO thyristor with an insulated gate in which the P type and n type are exchanged according to this embodiment, and various insulated gate type semiconductor devices using the method.

〔Effect of the invention〕

By using the manufacturing method of the present invention, it is possible to form diffusion windows in the P base layer and the N emitter layer with high precision at different positions without being affected by misalignment of masks. A p base layer can be formed. G with insulated gate improves turn-off ability without reducing turn-off ability.
A TO thyristor can be realized.

[Brief explanation of drawings]

1(a) to 1(e) are cross-sectional views of the manufacturing process of a GTO thyristor with an insulated gate according to the first embodiment of the present invention;
The figure is a sectional view of a conventional GTO thyristor with an insulated gate. Engineering: P-type emitter layer, 2: N-type base layer, 3:
...Gate insulating film, 41...Gate electrode, 42...
- First mask material, 5... Second mask material, 6...
P-type base layer, 7... third mask material, 8...
Fourth mask material, 9... n-type emitter layer, 10...
Silicon oxide film, 11... Anode electrode, 12...
cathode electrode, 13... short channel, 15...
long channel.

Claims (2)

[Claims] (1) Depositing a gate electrode material film on a first base layer of a substrate having a first base layer of a second conductivity type on a first emitter layer of a first conductivity type, with a gate insulating film interposed therebetween; a step of selectively etching a gate electrode material film to form a first masking agent remaining in an island shape adjacent to the gate electrode; and a second masking material covering between the gate electrode and the first masking material. forming a second base layer of a first conductivity type in the first base layer by doping impurities using the first and second masking agents and the gate electrode as masks; A method for manufacturing a GTO thyristor with an insulated gate, comprising the step of forming a second emitter layer of a second conductivity type in the second base layer using an electrode as a mask. (2) The GTO with an insulated gate according to claim 1, wherein impurity doping for forming the second emitter layer is performed after removing the first and second mask materials.
Method of manufacturing thyristors.