JPS5924546B2 - Field effect semiconductor switching device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a field effect semiconductor switching device, and particularly to a gate structure thereof.

Vertical field-effect semiconductor switching devices that have been proposed to date include so-called buried-gate devices in which a striped or lattice-shaped gate layer is buried in the semiconductor substrate, and a so-called buried-gate device in which a gate layer and a cathode layer are alternately formed from the surface of the semiconductor substrate. There is a so-called surface gate type element which is selectively formed at regular intervals.

FIG. 1 shows an example of a conventional example of such a buried gate type field effect switching element, and FIG. 2 shows an example of a conventional example of a surface gate type field effect switching element. In these figures, 1 is an n-type silicon substrate, and 2 is 1 of the substrate 1.
A p-type anode layer formed adjacent to the main surface, 3 is p
4 is an n-type cathode layer having a high impurity concentration, 5 is a channel portion through which the main current passes, and a Pnn+ type diode is formed in the vertical direction of these elements including the channel portion. There is. Further, an anode electrode 12, a gate electrode 13, and a cathode electrode 14 are formed in the anode layer 2, gate layer 3, and cathode layer 4, respectively. When voltages such that the anodes of these elements are positive and the cathodes are negative are applied to the anode electrode 12 and the cathode electrode 14, respectively, the main current flows to P including the channel portion 5.
It flows through the nn+ diode region.

This state is called an on state. On the other hand, when a voltage that makes the gate voltage negative with respect to the cathode is applied to the gate electrode 13, the Pn junction between the gate and the cathode is biased in the opposite direction, and a space charge layer spreads in the channel portion 5.

When the negative voltage applied to the gate 3 is sufficiently large, the channel portion 5 is pinched off by the space charge layer, blocking the current path in the diode region. This state is called an OFF state. The field effect device as described above operates as a switch having two steady states, on and off, by controlling the reverse bias voltage between the gate and the cathode.

Important characteristics that these devices should have are (1) short switching time (particularly the switching time from an on state to an off state);

(2) Forward bias voltage (VAK) between the anode and cathode in the off state and reverse bias voltage (VG) between the gate and cathode required to maintain the off state
The ratio of voltage gain (AK/VGK) is large, and the switch may be excellent as a semiconductor switch. (
In order to shorten the switching time in 1), it is necessary to quickly draw out the excess minority carriers accumulated in the channel section 5 in the on state through the gate layer 3.

For this purpose, it is necessary to reduce the resistance of the gate layer 3 as much as possible, and for this purpose, it is important to increase the impurity concentration of the gate layer 3. In order to improve the voltage gain in (2), it is important to lower the pinch-off voltage of the channel portion 5, that is, to narrow the channel width.

Examining the conventional example from the above viewpoint, in the conventional buried gate type device shown in FIG.
can be formed narrowly, so the voltage gain is large. However, due to its structure, a buried gate has a relatively long distance to the gate electrode, which increases the resistance in the longitudinal direction of the gate.
It is difficult to increase the impurity concentration of As a result, the resistance of the gate layer 3 increases, and the extraction of accumulated carriers from the channel portion 5 becomes weak, making it impossible to shorten the switching time and making it impossible to cut off a large current. In addition, in the conventional surface gate type device shown in FIG. 2, since the gate layer 3 is usually formed by a diffusion method, the impurity concentration can be made sufficiently high, making it easy to draw out the accumulated carriers in the channel section 5. , the switching time can be shortened.

However, in a surface gate type device, if the impurity concentration of the surface gate layer 3 is increased and a gate voltage large enough to pinch off the channel portion 5 is applied between the gate and the cathode, the depletion layer mainly forms in the cathode layer 4. It spreads in the channel portion 5 closer to the gate, making it difficult to obtain a reverse withstand voltage between the gate and the cathode.

In order to improve this, the gate layer 3 and the cathode layer 4 may be formed to be separated from each other to some extent, but this results in the disadvantage that the width of the channel portion 5 becomes wider and the voltage gain decreases. SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the conventional elements described above, and to provide a field effect switching element with short switching time and high voltage gain.

The switching element of the present invention that achieves the above object is characterized in that the impurity concentration of the gate layer, which is formed to substantially surround the sides of the cathode layer, is lowered in the interior than in the portion adjacent to the cathode layer. The point is that it is made to be high.

Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 3, 31 is an n-type silicon substrate, 32 is a p-type anode layer, 33 is a p-type gate layer, 34 is an n-type cathode layer with higher impurity concentration than the substrate 31, and 35 is the gate layer 3. In the enclosed channel part, 36 is a p-type gate contact layer with high impurity concentration to make good contact with the gate layer, and 37 is a p-type gate contact layer with high impurity concentration to make good contact with the anode layer. This is an anode contact layer. Further, 39 is an anode electrode, 40 is a gate electrode, 41
is the cathode electrode. A- in Figure 4 and Figure 3
As can be seen from the diagram showing the impurity concentration distribution in cross section A, the impurity concentration near the surface of the gate layer 3 is lower than that inside the gate layer 3.

In forming the switching element according to the present invention, any method and any impurity may be used as long as the impurity concentration of the gate layer 33 can be made higher on the substrate 31 side than near the surface. One way to achieve this is to make the depth of the gate layer wings deeper than the cathode layer 34, and to make the gate layer 33 and the cathode layer 34 directly adjacent to each other or to partially overlap with each other, so that the adjacent or overlapping parts A method can be used in which the impurity concentration of the gate layer 33 in the vicinity is reduced by the influence of impurities that determine the conductivity type of the cathode layer 34. Next, referring to FIG. 5, a device fabrication process will be described in which the selective aluminum diffusion method is used to form the gate layer 3 having the above impurity concentration distribution.

(a) First, an aluminum layer 52 is vacuum-deposited on the surface of an n-type silicon substrate 51, and unnecessary aluminum is removed by photo-etching. (b) A shallow p-type layer 53 is formed by heat treatment at 950° C. for about 1 hour, and an alloy layer of aluminum and silicon formed on the surface is removed using aqua regia or the like. (c) Heat treatment is performed at 1250° C. for about 8 hours in a gas atmosphere in which water at room temperature is bubbled with oxygen gas to stretch and diffuse the p-type layer. At this time, aluminum near the surface of the substrate 51 is diffused into the silicon oxide film formed during stretching and diffusion, and the aluminum concentration near the surface is 10
It decreases to 14-1016 cm-3. Further, as shown in FIG. 4, the concentration inside the gate layer 33 can be made sufficiently high, and the lateral resistance of the gate layer 33 can be made small. (d) In order to improve electrode contact between the anode layer 32 and the gate layer 35, a p+ layer 54 is formed by diffusing p-type impurities, such as boron, at a high concentration. (e) On the surface of the channel portion 55 surrounded by the gate layer, an n+ cathode layer 56 is formed by diffusing an n-type impurity, for example, phosphorus at a high concentration. (to) Finally, the p+ layer 54 and the n+ cathode layer 56
Electrodes 57 are formed by vacuum-depositing a highly conductive metal such as aluminum on the surface. When a reverse voltage is applied between the gate and cathode of the device manufactured by the above process, the space charge layer mainly spreads toward the gate layer 33 near the surface, as shown by 38 in FIG. Under the cathode layer 34, it mainly spreads toward the n-substrate 31 side.

That is, since the space charge layer 38 spreads to the cathode layer 34 little, the gate layer 33 and the cathode layer 34 may be in contact with each other, and the channel portion 35 can be narrowed without reducing the reverse withstand voltage between the gate and the cathode. can. Furthermore, as described above, the lateral resistance of the gate layer 33 can be reduced. Therefore, according to the above embodiment, it is possible to obtain a vertical field-effect semiconductor switch with short switching time and high voltage gain.

Further, in the above embodiment, the gate layer 33 was formed by diffusion of aluminum in an oxidizing atmosphere, but the same effect can be achieved by using gallium instead of aluminum.

As described above, using only the diffusion method to fabricate the switching device of the present invention simplifies the device manufacturing process and improves the yield. FIG. 6 shows another embodiment of the switch invention.

The numbers on the figures are the same as in Figure 3. In this embodiment, the device is formed so that the periphery of the sawing layer 3475 is embedded in the upper end of the gate layer 33. 7 in this case? ―
◆―? 1-'1 as well, as described above, the concentration of impurities near the surface of the gate layer 33 is lower than that inside, so there is no reduction in the reverse withstand voltage between the gate and the cathode.

Furthermore, in the structure as shown in FIG. 6, in addition to the p+Pnn+ type diode region including the channel portion 35, the cathode layer 34 includes the recessed upper end portion of the gate layer 33 to become a p+Pnpn+ type thyristor region. Since this also serves as the main current path, in addition to the effects shown in the previous embodiment, there is an advantage that the current-carrying area in the on state increases, and the forward voltage drop and turn-off time are reduced for the same amount of current.

In the device having the structure shown in FIG. 6, in the manufacturing process shown in FIG. 5, the diffusion pattern of the n+ type cathode layer 56 is made wider than that in FIG. It can be manufactured by making it ゜. As described above, according to the present invention, the impurity concentration near the surface of the gate layer is lowered without using epitaxial growth technology and without increasing the lateral resistance of the gate layer. It is possible to shorten the time, lower the forward voltage drop, and increase the voltage gain.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a conventional buried gate type field effect switching device, FIG. 2 is a diagram showing an example of a conventional surface gate type field effect switching device, and FIG. 3 is a diagram showing an example of a conventional field effect switching device according to the present invention. FIG. 4 is a diagram showing an impurity concentration distribution in the A-N portion of the example device shown in FIG. 3. FIG. 5 is a diagram showing the manufacturing process of the device shown in FIG. 3. FIG. 6 is a diagram showing another embodiment of the present invention. 31... Silicon substrate, 32... Anode layer, 33
...Gate layer, 34...Cathode layer, 35,...
Channel portion, 36... Gate contact layer, 37.
...Anode contact layer, 39...Anode electrode, 4
0... Gate electrode, 41... Cathode electrode.

Claims (1)

[Claims] 1. A first semiconductor layer of one conductivity type, and a second semiconductor layer of the other conductivity type that is adjacent to one side of the first semiconductor layer and forms a pn junction between the first semiconductor layer and the first semiconductor layer. a semiconductor layer;
At least one semiconductor layer of the other conductivity type is formed in the second semiconductor layer adjacent to the surface of the second semiconductor layer opposite to the first semiconductor layer, and has a higher impurity concentration than the second semiconductor layer. a first semiconductor region and a second semiconductor layer formed in the second semiconductor layer adjacent to a surface of the second semiconductor layer on the opposite side from the first semiconductor layer; at least one second semiconductor region of one conductivity type that surrounds the first semiconductor region and extends from the first semiconductor layer to the first semiconductor layer and forms a pn junction with the second semiconductor layer; first, second, and third electrodes formed on the other surface of the first semiconductor layer, the exposed surface of the first semiconductor region, and the exposed surface of the second semiconductor region, respectively; A field-effect semiconductor switching element characterized in that the impurity concentration is higher inside than in a portion in contact with the first semiconductor region. 2. The field-effect semiconductor switching element according to claim 1, wherein the second semiconductor region is in contact with the first semiconductor region at its peripheral portion and lower peripheral portion. 3. The field effect switching element according to claim 1 or 2, wherein the impurity that determines the conductivity type of the second semiconductor region is aluminum. 4. The field effect switching element according to claim 1 or 2, wherein the impurity that determines the conductivity type of the second semiconductor region is gallium.