JPH08213538A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPH08213538A JPH08213538A JP7042517A JP4251795A JPH08213538A JP H08213538 A JPH08213538 A JP H08213538A JP 7042517 A JP7042517 A JP 7042517A JP 4251795 A JP4251795 A JP 4251795A JP H08213538 A JPH08213538 A JP H08213538A
- Authority
- JP
- Japan
- Prior art keywords
- island
- die bond
- resin
- die
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
半導体チップを搭載するリードフレームのアイランドと
封止樹脂の密着性が良好な樹脂封止型半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a resin-encapsulated semiconductor device having good adhesion between an island of a lead frame on which a semiconductor chip is mounted and a sealing resin.
【０００２】[0002]
【従来の技術】従来の樹脂封止型半導体装置は図７に示
すように、半導体チップ８を搭載するアイランド１上に
半導体チップ８がＡｇペースト等のダイボンド材９で固
着され、半導体チップ８の電極（不図示）とインナーリ
ード３とが金線６でボンディングされ、全体を封止樹脂
７で樹脂封止後、封止樹脂から露呈したリードを所望の
形状に成形した構造となっている。2. Description of the Related Art In a conventional resin-encapsulated semiconductor device, as shown in FIG. 7, a semiconductor chip 8 is fixed on a land 1 on which a semiconductor chip 8 is mounted with a die bond material 9 such as Ag paste. The electrode (not shown) and the inner lead 3 are bonded with a gold wire 6, and the entire structure is sealed with a sealing resin 7, and then the lead exposed from the sealing resin is molded into a desired shape.
【０００３】このような構造を有する樹脂封止型半導体
装置は、シリコンからなる半導体チップ８と、金属から
なるアイランド１及び樹脂からなるダイボンド材９や封
止樹脂１１との各材料の熱膨張係数が異なるため、種々
の問題が発生している。In the resin-sealed semiconductor device having such a structure, the coefficient of thermal expansion of each of the semiconductor chip 8 made of silicon, the island 1 made of metal, the die bond material 9 made of resin, and the sealing resin 11. However, various problems have occurred.
【０００４】例えば、ダイボンド材９のベーキング等の
樹脂封止型半導体装置の製造工程での加熱工程や温度サ
イクル等の熱的信頼性試験において、各材料の熱膨張差
により、半導体チップ８とアイランド１との剥離、半導
体チップ８、封止樹脂１１及びダイボンド材９のクラッ
ク等の問題が発生していた。For example, in a thermal reliability test such as a heating process or a temperature cycle in a manufacturing process of a resin-sealed semiconductor device such as baking of a die bond material 9, a semiconductor chip 8 and an island are caused by a difference in thermal expansion of each material. 1 and the semiconductor chip 8, the sealing resin 11, and the die bonding material 9 have cracks.
【０００５】また、封止樹脂１１は一般に吸湿するが、
吸湿した状態で樹脂封止型半導体装置をプリント基板等
に半田付けした場合、急加熱により樹脂封止型半導体装
置内の水分が膨張し、アイランド１やダイボンド材９等
と封止樹脂１１との剥離や封止樹脂１１のクラックが発
生するという問題が発生していた。Although the sealing resin 11 generally absorbs moisture,
When the resin-encapsulated semiconductor device is soldered to a printed circuit board or the like in a moisture-absorbed state, moisture in the resin-encapsulated semiconductor device expands due to rapid heating, so that the island 1, the die bond material 9, etc. There has been a problem that peeling or cracking of the sealing resin 11 occurs.
【０００６】これらの問題点を解決する方法として、例
えば特開平２−１２５６５１号公報には、半導体チップ
を接地するアイランドの周辺を複数リードが取囲む領域
を金属帯板に連続して設けたリードフレームにおいて、
アイランドに該アイランド内をほぼ均等区分するような
複数のスリットを設けたリードフレームが提案されてい
る。すなわち、前記特開平２−１２５６５１号公報に記
載のリードフレームによれば、アイランド内にスリット
を設けることにより製造工程上加えられる熱、および樹
脂封止後に周囲海峡の温度変化による半導体チップのリ
ードフレーム間に発生する熱応力を低減でき半導体チッ
プがアイランドから剥離しない効果を有するものであ
る。As a method for solving these problems, for example, in Japanese Unexamined Patent Publication No. 2-125651, leads in which a region surrounding a plurality of leads surrounding an island for grounding a semiconductor chip are continuously provided on a metal strip plate. In the frame,
There has been proposed a lead frame in which a plurality of slits are provided on an island so as to divide the island substantially evenly. That is, according to the lead frame described in Japanese Patent Laid-Open No. 125651/1990, the lead frame of the semiconductor chip due to the heat applied in the manufacturing process by providing the slit in the island and the temperature change of the surrounding strait after resin sealing. This has the effect of reducing the thermal stress generated between them and preventing the semiconductor chip from peeling off from the island.
【０００７】[0007]
【発明が解決しようとする課題】前記従来のアイランド
にスリットを有した樹脂封止型半導体装置において、ス
リットによる応力緩和の効果を十分に得るためには、ア
イランドをより細分化することが望ましい。形状として
は、前記特開平２−１２５６５１号公報に示されるよう
に８分割する方法や、あるいは図８及び図９に示す形態
等が考えられる。In the conventional resin-sealed semiconductor device having slits in the island, it is desirable to further subdivide the island in order to sufficiently obtain the stress relaxation effect of the slit. As the shape, a method of dividing into eight as shown in the above-mentioned Japanese Patent Laid-Open No. 2-125651, or a form shown in FIGS. 8 and 9 can be considered.
【０００８】例えば□１６mmのアイランドサイズの場
合、半導体装置のサイズや厚さにも依存するが、アイラ
ンドを４分割した時に温度サイクル試験３００サイクル
において樹脂クラックが発生したが、図９に示すよう
に、アイランドを９分割した時においては１０００サイ
クルまで樹脂クラックの発生は無しであった。For example, in the case of an island size of □ 16 mm, although depending on the size and thickness of the semiconductor device, resin cracks were generated in 300 cycles of the temperature cycle test when the island was divided into four, as shown in FIG. When the island was divided into 9 parts, no resin crack was generated up to 1000 cycles.
【０００９】しかしながら、このようにアイランドをス
リットにより細分化した場合、アイランドに半導体チッ
プをダイボンド材で搭載接着する時にダイボンド材がス
リットから漏れ出すという問題が生じる。However, when the islands are subdivided by the slits in this way, there arises a problem that the die bond material leaks from the slits when the semiconductor chip is mounted and bonded to the islands by the die bond material.
【００１０】この場合、半導体チップをアイランドに接
着後、ベーキングの熱工程において、アイランドは熱膨
張するが、熱膨張した状態のアイランドのスリット間に
ダイボンド材が充填しているため、室温冷却後において
もアイランドが膨張し、規定の寸法よりも伸びた状態に
てダイボンディング後の半導体装置が形成されている。In this case, after the semiconductor chip is bonded to the island, the island thermally expands in the baking thermal process, but since the die bond material is filled between the slits of the thermally expanded island, it is cooled at room temperature. Also, the semiconductor device after die bonding is formed in a state where the island expands and extends beyond the specified dimension.
【００１１】このため、半導体チップ及びアイランドが
設計通りの位置よりシフトした状態で後工程である樹脂
封止を行なうため樹脂封止後の樹脂収縮によるアイラン
ドシフトがさらに大きくなり、薄型の半導体装置では半
導体チップあるいはアイランドが樹脂封止後の半導体装
置の表面に容易に露出するという欠点をなお残してい
た。For this reason, since the semiconductor chip and the island are shifted from the positions as designed, the resin sealing, which is a post-process, is performed in the subsequent step, and the island shift due to the resin shrinkage after the resin sealing is further increased. There is still a drawback that the semiconductor chip or the island is easily exposed on the surface of the semiconductor device after resin sealing.
【００１２】また、ダイボンド材がアイランドのスリッ
トから漏れ、アイランドの裏面へにじみ出しているた
め、樹脂封止後アイランドの金属−封止樹脂間の密着面
積低下による密着性低下から半田付け時のモールド樹脂
の吸湿に基づくアイランド−封止樹脂間の剥離、さらに
は樹脂クラックを容易に発生するという欠点をなお残し
ていた。Further, since the die-bonding material leaks from the slits of the island and oozes out to the back surface of the island, the adhesiveness deteriorates due to the reduction of the contact area between the metal and the sealing resin of the island after resin sealing, and therefore the mold at the time of soldering. It still has the drawback of easily peeling between the island and the sealing resin due to moisture absorption of the resin and further causing resin cracks.
【００１３】さらに、このダイボンド材のアイランドの
スリットからの漏れはダイボンディング装置の汚染を招
き、作業性低下、すなわち生産効率低下を誘発し易い欠
点をなお残していた。Further, the leakage of the die-bonding material from the slits of the island leads to contamination of the die-bonding apparatus, and there is still a drawback that the workability is lowered, that is, the production efficiency is lowered.
【００１４】このようなアイランドのスリットからのダ
イボンド材の漏れを防止する方法として、アイランドへ
のダイボンド材の塗布量を少なく制御することが考えら
れるが、この場合は半導体チップのアイランドへの接着
強度と半導体チップの熱放散性の劣化が生じる。As a method of preventing the leakage of the die bonding material from the slits of the island, it is conceivable to control the coating amount of the die bonding material on the island to be small. In this case, the adhesive strength of the semiconductor chip to the island is controlled. And the heat dissipation of the semiconductor chip deteriorates.
【００１５】これらの劣化を防止するためには、少なく
とも半導体チップに対し４０〜５０％以上のダイボンデ
ィング材の濡れ面積を確保する必要があり、アイランド
を細分化した場合、アイランドのスリットからのダイボ
ンド材の漏れを防止した上で４０〜５０％以上の濡れ面
積を確保することが困難であるという問題がある。In order to prevent these deteriorations, it is necessary to secure at least 40 to 50% or more of the wet area of the die bonding material with respect to the semiconductor chip. When the island is subdivided, die bonding from the slit of the island is performed. There is a problem that it is difficult to secure a wetted area of 40 to 50% or more while preventing material leakage.
【００１６】従って、本発明は上記問題点を解消し、リ
ードフレームのアイランドにスリットを有する樹脂封止
型半導体装置において、ダイボンド材のスリットからの
漏れにより発生する半田付け時のアイランド裏面−樹脂
間剥離、樹脂クラック等の発生を防止するようにした樹
脂封止型半導体装置を提供することを目的とする。Therefore, the present invention solves the above problems and, in a resin-sealed semiconductor device having a slit in the island of the lead frame, between the back surface of the island and the resin at the time of soldering caused by leakage of the die bond material from the slit. It is an object of the present invention to provide a resin-encapsulated semiconductor device that prevents the occurrence of peeling, resin cracks and the like.
【００１７】[0017]
【課題を解決するための手段】前記目的を達成するた
め、本発明の樹脂封止型半導体装置は、半導体チップが
アイランドにダイボンド材を介して接着され、前記半導
体チップとリードとが金属細線でボンディングされ、前
記半導体チップ、アイランド、金属細線及びリードの一
部を樹脂封止してなる樹脂封止型半導体装置において、
アイランドの中央部に半導体チップサイズの４０〜８０
％の面積を有するダイボンドエリアを設けると共に、ダ
イボンドエリアを取り囲み、かつダイボンドエリアの周
囲を細分化するスリットを設けたアイランドを有し、前
記ダイボンドエリア内でダイボンド材を介して半導体チ
ップが接着されているか、あるいは前記アイランド中央
部に設けたダイボンドエリア内に、ダイボンドエリアを
分割するスリットを有し、該ダイボンドエリア内でダイ
ボンド材を介して半導体チップが接着されている。In order to achieve the above object, in a resin-sealed semiconductor device of the present invention, a semiconductor chip is bonded to an island via a die bond material, and the semiconductor chip and the lead are made of a fine metal wire. In a resin-sealed semiconductor device which is bonded, and is formed by resin-sealing a part of the semiconductor chip, the island, the thin metal wire and the lead,
A semiconductor chip size of 40-80 in the center of the island
% Of the die bond area having an area, and surrounding the die bond area, and having an island provided with slits for subdividing the periphery of the die bond area, the semiconductor chip is bonded through the die bond material in the die bond area. Or a slit that divides the die bond area is provided in the die bond area provided in the center of the island, and the semiconductor chip is bonded through the die bond material in the die bond area.
【００１８】[0018]
【作用】本発明によれば、半導体チップを搭載するアイ
ランドの中央部に、半導体サイズの略４０〜８０％のダ
イボンドエリアを設け、且つそのダイボンドエリアを取
り囲み、その周囲を細分化するスリットを有するアイラ
ンドとし、ダイボンドエリア内でダイボンド材を介して
接着することにより、従来のアイランドにスリットを設
けて応力緩和効果を得ることを維持し、半導体チップの
アイランドへの接着強度及び熱放散性を維持しながら、
従来のスリット入アイランド構造で問題とされたダイボ
ンド材のスリットからの漏出を防止することができる。According to the present invention, a die bond area of approximately 40 to 80% of the semiconductor size is provided in the center of an island on which a semiconductor chip is mounted, and a slit that surrounds the die bond area and subdivides the periphery thereof is provided. By forming an island and bonding it through the die bond material in the die bond area, it is possible to maintain the conventional island with a slit to maintain the stress relaxation effect, and to maintain the adhesive strength and heat dissipation of the semiconductor chip to the island. While
It is possible to prevent the die bond material from leaking from the slit, which has been a problem in the conventional island structure with slits.
【００１９】このため、本発明によれば、従来問題とな
っていたダイボンド後のベーキングなどの熱工程時にス
リットへ漏出したダイボンド材が熱膨張したアイランド
状態のスリット間で硬化することにより発生する、アイ
ランドを支持している吊りピンを含めたアイランドの寸
法の伸び、さらには前記アイランド寸法の伸びが引き起
こす半導体チップ及びアイランド位置の設計寸法からの
変位による樹脂封止後の半導体チップ及びアイランドの
シフトを防止することができ、容易な樹脂封止が可能と
なる。Therefore, according to the present invention, the die-bonding material leaked to the slits during the thermal process such as baking after die-bonding, which has been a problem in the past, is caused by hardening between the slits in the thermally expanded island state. The shift of the size of the island including the hanging pins supporting the island and the shift of the semiconductor chip and the island after resin sealing due to the displacement of the semiconductor chip and the position of the island from the designed size caused by the stretch of the size of the island. It can be prevented, and the resin can be easily sealed.
【００２０】この結果、従来薄型半導体装置において樹
脂封止後半導体チップあるいはアイランドが樹脂表面に
露出する不良が４０％近く発生していたものが、本発明
によれば該不良発生をゼロに抑えることが可能となる。As a result, in the conventional thin semiconductor device, a defect in which the semiconductor chip or the island was exposed on the resin surface after resin encapsulation occurred in about 40%, but according to the present invention, the defect generation can be suppressed to zero. Is possible.
【００２１】また、従来品質上重大な問題となっていた
半田付け時のモールド樹脂の吸湿に基づくアイランド−
封止樹脂間の剥離およびクラックの発生が、本発明によ
れば、その主原因となるダイボンド材のアイランドのス
リットからのアイランド裏面への漏れを防止することが
できるため、アイランド裏面の金属表面積が設計値通り
確保され、アイランド−封止樹脂間の密着性低下を防止
できるとともに、アイランド裏面へ漏出したダイボンド
材の吸湿をも防止でき、従来の半導体装置では半田付け
時の熱履歴にてアイランド−封止樹脂間が１００％剥離
し、６０％以上の樹脂クラックを発生していたものが、
本発明では該不良発生をゼロに抑えることができる。Further, an island caused by moisture absorption of the mold resin at the time of soldering, which has been a serious problem in the conventional quality,
According to the present invention, the peeling between the sealing resins and the occurrence of cracks can be prevented mainly from leaking from the slits of the island of the die bonding material to the back surface of the island. It is secured according to the design value, the adhesion between the island and the encapsulation resin can be prevented from decreasing, and the die bond material that has leaked to the back surface of the island can also be prevented from absorbing moisture. There was 100% peeling between the encapsulation resins and 60% or more resin cracks were generated.
In the present invention, the occurrence of defects can be suppressed to zero.
【００２２】さらに、本発明によれば、従来問題となっ
ていたダイボンド材のアイランドのスリットからの漏れ
によるダイボンド装置の汚染を防止することができるた
め、作業性及び生産性の低下の問題は解消され、良好な
半導体装置の生産性を保障することができる。Further, according to the present invention, it is possible to prevent the contamination of the die bonding apparatus due to the leakage of the die bonding material from the slits of the island, which has been a problem in the related art. Therefore, the problem of the deterioration of workability and productivity is solved. As a result, good productivity of semiconductor devices can be guaranteed.
【００２３】[0023]
【実施例】図面を参照して、本発明の実施例を以下に説
明する。Embodiments of the present invention will be described below with reference to the drawings.
【００２４】[0024]
【実施例１】図１は本発明の第１の実施例の樹脂封止型
半導体装置の断面図、図２及び図３はそのリードフレー
ムの平面図である。図１において前記従来例の説明に用
いた図７と同一の要素には同一の参照番号が附されてい
る。なお、本実施例の構成と前記従来例の構成との同一
部分の説明は省略する。Embodiment 1 FIG. 1 is a sectional view of a resin-sealed semiconductor device according to a first embodiment of the present invention, and FIGS. 2 and 3 are plan views of its lead frame. In FIG. 1, the same elements as those of FIG. 7 used to describe the conventional example are designated by the same reference numerals. The description of the same parts as those of the configuration of the present embodiment and the configuration of the conventional example will be omitted.
【００２５】図２及び図３に示すように、アイランド１
の中央部に搭載する半導体チップサイズの４０〜８０％
の面積を有するダイボンドエリア４を設け、ダイボンド
エリア４を取り囲むようにスリット２を設け、スリット
２はダイボンドエリア４の周囲を細分化している。As shown in FIGS. 2 and 3, the island 1
40-80% of the semiconductor chip size to be mounted in the center of
The die bond area 4 having an area of 2 is provided, the slit 2 is provided so as to surround the die bond area 4, and the slit 2 subdivides the periphery of the die bond area 4.
【００２６】また、図１に示すように、半導体チップ８
はダイボンドエリア４内においてダイボンド材９により
アイランド１と接着されている。Further, as shown in FIG. 1, the semiconductor chip 8
Are bonded to the island 1 by the die bond material 9 in the die bond area 4.
【００２７】本実施例に係る樹脂封止型半導体装置の製
造は、前記従来例と同様に、図２又は図３に示すよう
に、アイランド１の中央部に半導体チップサイズの４０
〜８０％の面積を有するダイボンドエリア４と、ダイボ
ンドエリア４を取り囲むように、かつダイボンドエリア
４の周囲を細分化するスリットを有するアイランド１と
インナーリード３とアイランド１を支持する吊りピン５
等を少なくとも有するリードフレーム１０を準備し、次
にダイボンドエリア４内においてダイボンド材９を介し
て半導体チップ８をアイランド１に固着後、図１に示す
ように半導体チップ８とインナーリード３とを金線６で
接続し、ついで全体を樹脂封止後、封止樹脂から露呈し
ているリードを所望の形状に成形して完成する。In the manufacture of the resin-sealed type semiconductor device according to this embodiment, as in the conventional example, as shown in FIG. 2 or FIG.
A die bond area 4 having an area of ˜80%, an island 1 having slits that surround the die bond area 4 and subdivide the periphery of the die bond area 4, inner leads 3, and suspension pins 5 that support the island 1.
Etc. are prepared, and then the semiconductor chip 8 is fixed to the island 1 through the die bond material 9 in the die bond area 4, and then the semiconductor chip 8 and the inner leads 3 are gold-plated as shown in FIG. The wire 6 is connected, then the whole is sealed with resin, and the leads exposed from the sealing resin are molded into a desired shape to complete the process.
【００２８】このような構造の半導体装置においては、
上記のようにダイボンド材９を介して半導体チップ８を
接着する部分であるダイボンドエリア４が半導体チップ
サイズの４０〜５０％以上であることから、半導体チッ
プの接着強度及び熱放散性を維持できる上、十分な接着
面積が確保されているため、ダイボンド材９がスリット
２から漏れ出すことを防ぐためのダイボンド材９の塗布
量の制御は前記従来例と同様に容易に実施することがで
きる。In the semiconductor device having such a structure,
As described above, since the die bond area 4 which is the portion to which the semiconductor chip 8 is bonded via the die bond material 9 is 40 to 50% or more of the semiconductor chip size, the adhesive strength and heat dissipation of the semiconductor chip can be maintained. Since the sufficient bonding area is secured, the control of the coating amount of the die bonding material 9 for preventing the die bonding material 9 from leaking out from the slit 2 can be easily performed as in the conventional example.
【００２９】また、ダイボンドエリア４は半導体チップ
サイズの８０％以下であるということから、スリットに
よる応力緩和効果を十分に維持することができる構造と
なっている。Further, since the die bond area 4 is 80% or less of the semiconductor chip size, the structure is such that the stress relaxation effect by the slit can be sufficiently maintained.
【００３０】[0030]
【実施例２】図４及び図５は本発明の第２の実施例の樹
脂封止型半導体装置の断面図とリードフレームの平面図
である。Second Embodiment FIGS. 4 and 5 are a sectional view of a resin-sealed semiconductor device according to a second embodiment of the present invention and a plan view of a lead frame.
【００３１】図５に示すように、本実施例では、前記第
１の実施例と同様なアイランド１の中央部に設けたダイ
ボンドエリア４内にさらにダイボンドエリア４を分割す
るスリット２を設けている。これにより、半導体チップ
サイズが例えば□１５mm以上と十分に大きい場合、ダイ
ボンド材９がスリット２から漏れ出すことを防止できる
塗布量が制御できる面積を確保しながら、スリット２に
よる応力緩和効果をより効果的にすることができる。な
お、本実施例においても、半導体チップ８のアイランド
１への接着は図４に示すようにダイボンドエリア４内で
行なう。As shown in FIG. 5, in this embodiment, a slit 2 for dividing the die bond area 4 is further provided in the die bond area 4 provided in the central portion of the island 1 similar to the first embodiment. . Thereby, when the semiconductor chip size is sufficiently large, for example, □ 15 mm or more, the stress relaxation effect by the slit 2 is more effective while ensuring the area where the coating amount can be controlled to prevent the die bond material 9 from leaking out from the slit 2. You can do it. Also in this embodiment, the semiconductor chip 8 is bonded to the island 1 within the die bond area 4 as shown in FIG.
【００３２】[0032]
【実施例３】図６は本発明の第３の実施例におけるリー
ドフレームの平面図である。Third Embodiment FIG. 6 is a plan view of a lead frame according to a third embodiment of the present invention.
【００３３】図６を参照して、本実施例に係るリードフ
レーム１０のアイランド１は前記第１の実施例あるいは
第２の実施例と同様に形成されたダイボンドエリア４の
周囲の部分をスリットにてより効果的に分割したもので
ある。即ち、細分化された各単位において、対向する辺
及びコーナーを結ぶ線上にスリット２が存在する形状と
され、かつダイボンドエリア４を十分確保するようにス
リット２をできるだけダイボンドエリア４外に配置した
構造としている。Referring to FIG. 6, the island 1 of the lead frame 10 according to this embodiment has slits around the die bond area 4 formed in the same manner as in the first or second embodiment. It is a more effective division. That is, in each of the subdivided units, the slit 2 is formed on the line connecting the opposite sides and the corners, and the slit 2 is arranged as much as possible outside the die bond area 4 so as to secure the die bond area 4 sufficiently. I am trying.
【００３４】以上、本発明を上記各実施例に即して説明
したが、本発明は上記態様にのみ限定されるものでな
く、本発明の原理に準ずる各種態様を含むことは勿論で
ある。Although the present invention has been described with reference to each of the above-described embodiments, the present invention is not limited to the above-described embodiments, and it goes without saying that various embodiments according to the principles of the present invention are included.
【００３５】[0035]
【発明の効果】以上説明したように本発明によれば、半
導体チップを搭載するアイランドの中央部に、半導体サ
イズの４０〜８０％のダイボンドエリアを設け、ダイボ
ンドエリアを取り囲み、その周囲を細分化するようにス
リットを設けたアイランドとし、ダイボンドエリア内で
ダイボンド材を介して接着することにより、応力緩和効
果を得ることを維持すると共に半導体チップのアイラン
ドへの接着強度及び熱放散性を維持しながら、ダイボン
ド材のスリットからの漏出を防止することができるとい
う効果を有する。As described above, according to the present invention, a die bond area of 40 to 80% of the semiconductor size is provided in the center of an island on which a semiconductor chip is mounted, the die bond area is surrounded, and the periphery thereof is subdivided. While maintaining the adhesive strength to the island of the semiconductor chip and heat dissipation while maintaining the stress relaxation effect by making the island with slits so that it is bonded through the die bond material in the die bond area This has the effect of preventing leakage of the die bond material from the slit.
【００３６】このため、本発明によれば、従来問題とな
っていたダイボンド後のベーキングなどの熱工程時にス
リットへ漏出したダイボンド材が熱膨張したアイランド
状態のスリット間で硬化することにより発生する、アイ
ランドを支持している吊りピンを含めたアイランドの寸
法の伸び、さらには前記アイランド寸法の伸びが引き起
こす半導体チップ及びアイランド位置の設計寸法からの
変位による樹脂封止後の半導体チップ及びアイランドの
シフトを防止することができ、容易な樹脂封止が可能と
なる。Therefore, according to the present invention, the die-bonding material leaked to the slits during the thermal process such as baking after die-bonding, which has been a problem in the past, is caused by hardening between the slits in the thermally expanded island state. The shift of the size of the island including the hanging pins supporting the island and the shift of the semiconductor chip and the island after resin sealing due to the displacement of the semiconductor chip and the position of the island from the designed size caused by the stretch of the size of the island. It can be prevented, and the resin can be easily sealed.
【００３７】この結果、本発明によれば、従来、薄型半
導体装置において樹脂封止後、半導体チップあるいはア
イランドが樹脂表面に露出する不良が４０％近く発生し
ていたものが、該不良発生をゼロに抑えることが可能と
なる。As a result, according to the present invention, in the conventional thin semiconductor device, after the resin encapsulation, the defect that the semiconductor chip or the island is exposed on the surface of the resin was close to 40%. It becomes possible to suppress it.
【００３８】また、従来品質上重大な問題となっていた
半田付け時のモールド樹脂の吸湿に基づくアイランド−
封止樹脂間の剥離およびクラックの発生が、本発明によ
れば、その主原因となるダイボンド材のアイランドのス
リットからのアイランド裏面への漏れを防止することが
できるため、アイランド裏面の金属表面積が設計値通り
確保され、アイランド−封止樹脂間の密着性低下を防止
できるとともに、アイランド裏面へ漏出したダイボンド
材の吸湿をも防止することができる。Further, the island caused by the moisture absorption of the mold resin at the time of soldering, which has been a serious problem in the conventional quality,
According to the present invention, peeling between the sealing resins and generation of cracks can be prevented mainly from leaking from the slits of the island of the die bonding material to the back surface of the island. It is ensured according to the design value, and it is possible to prevent the adhesion between the island and the sealing resin from being lowered, and also to prevent the die bond material leaking to the back surface of the island from absorbing moisture.
【００３９】そして、本発明によれば、従来の半導体装
置では半田付け時の熱履歴にてアイランド−封止樹脂間
が１００％剥離し、６０％以上の樹脂クラックを発生し
ていたものが、該不良発生をゼロに抑えることができ
る。According to the present invention, in the conventional semiconductor device, 100% of the island-sealing resin is peeled off due to the heat history during soldering, and 60% or more of resin cracks are generated. The occurrence of defects can be suppressed to zero.
【００４０】さらに、本発明によれば、従来問題となっ
ていたダイボンド材のアイランドのスリットからの漏れ
によるダイボンド装置の汚染を防止することができるた
め、作業性及び生産性の低下の問題は解消され、良好な
半導体装置の生産性を保障することができる。Further, according to the present invention, it is possible to prevent the contamination of the die bonding apparatus due to the leakage of the die bonding material from the slits of the island, which has been a problem in the past. Therefore, the problem of deterioration in workability and productivity is solved. As a result, good productivity of semiconductor devices can be guaranteed.
【図１】本発明の第１の実施例の半導体装置の構成を示
す断面図である。FIG. 1 is a sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention.
【図２】本発明の第１の実施例におけるリードフレーム
の平面図である。FIG. 2 is a plan view of the lead frame according to the first embodiment of the present invention.
【図３】本発明の第１の実施例における別のリードフレ
ームの平面図である。FIG. 3 is a plan view of another lead frame according to the first embodiment of the present invention.
【図４】本発明の第２の実施例の半導体装置の構成を示
す断面図である。FIG. 4 is a sectional view showing a configuration of a semiconductor device according to a second embodiment of the present invention.
【図５】本発明の第２の実施例におけるリードフレーム
の平面図である。FIG. 5 is a plan view of a lead frame according to a second embodiment of the present invention.
【図６】本発明の第３の実施例におけるリードフレーム
の平面図である。FIG. 6 is a plan view of a lead frame according to a third embodiment of the present invention.
【図７】従来の半導体装置の構成を示す図である。FIG. 7 is a diagram showing a configuration of a conventional semiconductor device.
【図８】従来の半導体装置におけるリードフレームの平
面図である。FIG. 8 is a plan view of a lead frame in a conventional semiconductor device.
【図９】従来の半導体装置における別のリードフレーム
の平面図である。FIG. 9 is a plan view of another lead frame in the conventional semiconductor device.
１ アイランド ２ スリット ３ インナーリード ４ ダイボンドエリア ５ 吊りピン ６ 金線 ７ 封止樹脂 ８ 半導体チップ ９ ダイボンド材 １０ リードフレーム 1 Island 2 Slit 3 Inner Lead 4 Die Bond Area 5 Hanging Pin 6 Gold Wire 7 Sealing Resin 8 Semiconductor Chip 9 Die Bond Material 10 Lead Frame
Claims (3)
を介して接着され、前記半導体チップとリードとが金属
細線及びリードの一部を樹脂封止してなる樹脂封止型半
導体装置において、 前記アイランドが、その中央部に前記半導体チップ寸法
の実質的主要領域に相当する面積を有するダイボンドエ
リアを具備すると共に、該ダイボンドエリアを囲繞し、
かつ、該ダイボンドエリアの周囲を細分化するスリット
を複数備え、 前記ダイボンドエリア内でダイボンド材を介して前記半
導体チップが接着されてなることを特徴とする樹脂封止
型半導体装置。1. A resin-sealed semiconductor device in which a semiconductor chip is bonded to an island via a die bond material, and the semiconductor chip and a lead seal a metal thin wire and a part of the lead with a resin. A die bond area having an area corresponding to a substantial main region of the semiconductor chip size is provided in a central portion thereof, and the die bond area is surrounded by the die bond area,
Further, a resin-encapsulated semiconductor device comprising a plurality of slits for subdividing the periphery of the die bond area, wherein the semiconductor chip is bonded in the die bond area via a die bond material.
体チップ寸法の略４０〜８０％の面積を有するダイボン
ドエリアを具備することを特徴とする請求項１記載の樹
脂封止型半導体装置。2. The resin-encapsulated semiconductor device according to claim 1, wherein the island has a die bond area having an area of approximately 40 to 80% of the size of the semiconductor chip in the central portion thereof.
ボンドエリア内に、該ダイボンドエリアを分割するスリ
ットを有することを特徴とする請求項１記載の樹脂封止
型半導体装置。3. The resin-encapsulated semiconductor device according to claim 1, wherein a slit for dividing the die bond area is provided in the die bond area provided at the center of the island.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7042517A JP2679664B2 (en) | 1995-02-07 | 1995-02-07 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7042517A JP2679664B2 (en) | 1995-02-07 | 1995-02-07 | Resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08213538A true JPH08213538A (en) | 1996-08-20 |
| JP2679664B2 JP2679664B2 (en) | 1997-11-19 |
Family
ID=12638278
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7042517A Expired - Fee Related JP2679664B2 (en) | 1995-02-07 | 1995-02-07 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2679664B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0862211A3 (en) * | 1997-02-27 | 2000-11-08 | Oki Electric Industry Co., Ltd. | Semiconductor apparatus and method for fabricating the same |
| JP2007311579A (en) * | 2006-05-19 | 2007-11-29 | Matsushita Electric Ind Co Ltd | Lead frame and semiconductor device using the same |
| JP2008300587A (en) * | 2007-05-31 | 2008-12-11 | Renesas Technology Corp | Semiconductor device and manufacturing method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58177168A (en) * | 1982-04-12 | 1983-10-17 | Nippon Wagner Supureetec Kk | Hydraulic spray gun |
| JPS59169160A (en) * | 1983-03-16 | 1984-09-25 | Hitachi Ltd | Electronic device |
| JPH06132442A (en) * | 1992-10-19 | 1994-05-13 | Hitachi Ltd | Semiconductor device and its manufacture |
| JPH06204389A (en) * | 1992-12-28 | 1994-07-22 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| JPH06268144A (en) * | 1993-03-17 | 1994-09-22 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPH06302754A (en) * | 1993-04-16 | 1994-10-28 | Mitsui High Tec Inc | Lead frame and manufacture thereof |
-
1995
- 1995-02-07 JP JP7042517A patent/JP2679664B2/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58177168A (en) * | 1982-04-12 | 1983-10-17 | Nippon Wagner Supureetec Kk | Hydraulic spray gun |
| JPS59169160A (en) * | 1983-03-16 | 1984-09-25 | Hitachi Ltd | Electronic device |
| JPH06132442A (en) * | 1992-10-19 | 1994-05-13 | Hitachi Ltd | Semiconductor device and its manufacture |
| JPH06204389A (en) * | 1992-12-28 | 1994-07-22 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| JPH06268144A (en) * | 1993-03-17 | 1994-09-22 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPH06302754A (en) * | 1993-04-16 | 1994-10-28 | Mitsui High Tec Inc | Lead frame and manufacture thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0862211A3 (en) * | 1997-02-27 | 2000-11-08 | Oki Electric Industry Co., Ltd. | Semiconductor apparatus and method for fabricating the same |
| EP1528595A1 (en) * | 1997-02-27 | 2005-05-04 | Oki Electric Industry Co., Ltd. | Lead frame, wire-bonding stage and method for fabricating a semiconductor apparatus |
| JP2007311579A (en) * | 2006-05-19 | 2007-11-29 | Matsushita Electric Ind Co Ltd | Lead frame and semiconductor device using the same |
| JP4738250B2 (en) * | 2006-05-19 | 2011-08-03 | パナソニック株式会社 | Semiconductor device |
| JP2008300587A (en) * | 2007-05-31 | 2008-12-11 | Renesas Technology Corp | Semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2679664B2 (en) | 1997-11-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6281566B1 (en) | Plastic package for electronic devices | |
| JP2972096B2 (en) | Resin-sealed semiconductor device | |
| JPWO2004004005A1 (en) | Semiconductor device and manufacturing method thereof | |
| JP2004048023A (en) | Method for manufacturing lead frame | |
| JPH09321212A (en) | Semiconductor device and its manufacture | |
| KR100355795B1 (en) | manufacturing method of semiconductor package | |
| JP2001250833A (en) | Semiconductor device and its manufacturing method | |
| JP2679664B2 (en) | Resin-sealed semiconductor device | |
| JPH02125651A (en) | Lead frame | |
| JPH10135249A (en) | Resin-sealed semiconductor device | |
| JP3528711B2 (en) | Lead frame, resin-sealed semiconductor device using the same, and method of manufacturing the same | |
| JPH0964266A (en) | Lead frame | |
| JP2002110884A (en) | Lead frame laminate | |
| JP2001185567A (en) | Semiconductor device and manufacturing method therefor | |
| JPH08288428A (en) | Resin-sealed semiconductor device | |
| JPH04168759A (en) | Semiconductor device, lead frame and fabrication thereof | |
| JPH08222585A (en) | Semiconductor device | |
| KR100268925B1 (en) | Lead frame and semiconductor package with such lead frame | |
| KR100229222B1 (en) | Loc package | |
| JPH0555412A (en) | Semiconductor device | |
| JP3514516B2 (en) | Method for manufacturing semiconductor device | |
| JPH0296357A (en) | Semiconductor device | |
| JPS61191055A (en) | Resin sealed type semiconductor device | |
| JPH0547835A (en) | Mounting structure of semiconductor device | |
| JPH02205351A (en) | Resin seal type semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19970701 |
|
| LAPS | Cancellation because of no payment of annual fees |