JPH08195893A - Synchronizing separator circuit - Google Patents

Abstract

PURPOSE: To surely perform synchronizing separation even when the level of the synchronizing signals of digital video signals is unknown or fluctuates. CONSTITUTION: This circuit is provided with a selection circuit 7 for selecting either slice level value of a slice level variable output circuit 8 or slice level value (center level) of a center level output circuit 13 and a comparator 6 for comparing the selected slice level value with the digital video signals. When the slice level value of the slice level variable output circuit 8 is gradually made large and the synchronizing signals are obtained from the output of the comparator 6, a sync chip level detection circuit 10 detects a sync chip level and a pedestal level detection circuit 12 detects a pedestal level respectively. By the detected result, the center level output circuit 13 outputs the intermediate value of both levels and supplies the intermediate value to the comparator 6 as the slice level value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync separation circuit for separating a sync signal from a digital video signal.

[0002]

2. Description of the Related Art In recent video equipment such as televisions and VTRs, digital signal processing is used because it can be easily integrated into an IC and downsized. Further, it has been proposed that the sync separation circuit necessary for performing digital signal processing is also digitized. This type of conventional sync separation circuit has a slice level output circuit and a comparator. The slice level output circuit outputs the digitized slice level value to the comparator, and the slice level value is set to a value slightly higher than the sync tip level of the video signal. The digitized video signal and the slice level value are input to the comparator, and the synchronization signal is obtained from the comparison result of the comparator.

[0003]

However, according to the above conventional configuration, since the slice level value is constant, the sync signal cannot be separated unless the level of the sync signal of the digitized video signal is within a predetermined range. There was a drawback. Further, there is a drawback that the sync signal cannot be separated even when the level of the sync signal varies.

Therefore, the present invention provides a sync separation circuit which can surely separate the sync even if the level of the sync signal of the video signal is unknown or the level of the sync signal varies. It is an issue. Another object of the present invention is to provide a sync separation circuit capable of performing reliable and stable sync separation not only when the level of the sync signal changes but also when the amplitude of the sync signal changes. .

[0005]

SUMMARY OF THE INVENTION To achieve the above object, a sync separation circuit of the present invention comprises a slice level variable output circuit capable of gradually varying the size of a slice level value of an output signal, and this slice level variable output. A comparator that compares the slice level value of the circuit with the level of the digital video signal, a synchronization signal detection circuit that detects whether a synchronization signal can be obtained from the output of this comparator, and this synchronization signal detection circuit detects the synchronization signal Otherwise, the slice level variable output circuit controls the slice level value to be gradually changed from the initial value, and when the synchronization signal detection circuit detects a synchronization signal, the slice level variable output circuit changes the slice level value. And a control means for controlling to stop changing.

Another sync separation circuit of the present invention is a slice level variable output circuit capable of gradually varying the slice level value of an output signal, a slice level value of this slice level variable output circuit, and a center level described below. A selection circuit that selects one of the slice level values of the level output circuit, a comparator that compares the slice level value selected by this selection circuit and the level of the digital video signal, and a synchronization signal is obtained from the output of this comparator. Sync signal detection circuit that detects whether or not the sync signal is obtained, a sync chip level detection circuit that detects the sync chip level of the digital video signal when the sync signal is obtained from the output of the comparator, and a sync signal is obtained from the output of the comparator. Pedestal level detection to detect the pedestal level of the digital video signal Circuit, a center level output circuit that outputs an intermediate value between the sync tip level detected by the sync tip level detection circuit and the pedestal level detected by the pedestal level detection circuit as a slice level value, and the synchronization signal detection circuit When the signal cannot be detected, the selection circuit selects the slice level value of the slice level variable output circuit, and the slice level variable output circuit controls the slice level value to gradually change from the initial value, and When the sync signal detection circuit detects a sync signal, the slice level variable output circuit is controlled to stop changing the slice level value, and the pedestal level is detected by the pedestal level detection circuit and the sync tip level detection circuit. Sync tip level is detected respectively, and In which 択回 path and control means for controlling so as to select a slice level of the center level detection circuit.

[0007]

According to the former invention, the slice level variable output circuit gradually changes (increases) the slice level value from the initial value, and when the slice level value exceeds the sync tip level of the video signal, the output from the comparator is synchronized. When a signal is obtained and this synchronizing signal is obtained, the slice level value of the slice level variable output circuit is fixed. When the synchronizing signal cannot be obtained from the output of the comparator, the above operation is repeated.

According to the latter invention, the slice level variable output circuit gradually changes (increases) the slice level value from the initial value, and when the slice level value exceeds the sync chip level of the video signal, the output from the comparator is synchronized. A signal is obtained, and when this sync signal is obtained, the slice level value of the slice level variable output circuit is fixed and the sync signal is controlled so as to obtain the sync signal after that. , The pedestal level detection circuit detects the pedestal level of the digital video signal, the center level output circuit outputs the intermediate value of both levels, and this intermediate value is sent to the comparator via the selection circuit as the slice level value. Is output. When the synchronizing signal cannot be obtained from the output of the comparator, the above operation is repeated.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 5 show an embodiment of the present invention. FIG. 5 shows a circuit block diagram of the video signal processing system. In FIG. 5, the video signal is digitized (for example, 8 bits) by the AD converter 1, and the digitized video signal is supplied to the digital signal processing unit 2 and the sync separation circuit 3, respectively. The sync separation circuit 3 separates the sync signal from the digital video signal and outputs the separated sync signal to the digital signal processing unit 2. The digital signal processing unit 2 performs a predetermined signal processing on the digital video signal and outputs it to the DA converter 4, where it is converted back into an analog signal.

The digital signal processing section 2 and the sync separation circuit 3 are all digital circuits, and they are integrated as a whole (in the area surrounded by a chain line in FIG. 5) or individually integrated into an IC.

FIG. 1 is a detailed circuit block diagram of the sync separation circuit 3. In FIG. 1, the digital video signal is supplied to a low pass filter (LPF) 5, where the high frequency component of the digital video signal is attenuated. This is because the malfunction of the sync separation is suppressed by attenuating the high frequency components. The digital video signal passed through the low-pass filter (LPF) 5 is supplied to one input terminal of the comparator 6, and the selection circuit 7 is connected to the other input terminal of the comparator 6.
The signal selected by is supplied as the slice level value. The comparator 6 compares the digital video signal with the slice level value and outputs the L level (digital value) only during the period when the slice level value is large.

The slice level variable output circuit 8 gradually changes the slice level value of the output signal and outputs it, and is composed of, for example, an up counter. A clock signal is input to the clock terminal of the up counter, and counts up each time the clock signal is input. Further, the up-counter is configured to prohibit the count-up by a count-up prohibition signal of the microcomputer 17 described below, and further, the count value is reset to zero (initial value) by a reset signal from the microcomputer 17. The initial value is not zero and may be any value as long as it is always lower than the sync chip level. The output of the slice level variable output circuit 8 configured as described above is supplied to the a terminal of the selection circuit 7.

The output of the comparator 6 is guided to the sync tip position signal generation circuit 9, and when the sync tip position signal generation circuit 9 obtains the sync signal from the output of the comparator 6, the sync tip position is detected based on the falling point. To do. Then, the sync chip position signal indicating the sync chip position is output to the sync chip level detection circuit 10.
The digital video signal is guided to the sync chip level detection circuit 10, and the sync chip level detection circuit 10 detects the sync chip level of the digital video signal based on the sync chip position signal.

The output of the comparator 6 is guided to the pedestal position signal generation circuit 11, and when the synchronization signal is obtained from the output of the comparator 6, the pedestal position signal generation circuit 11 detects the pedestal position based on its rising point. Then, a pedestal position signal indicating the pedestal position is output to the pedestal level detection circuit 12. A digital video signal is guided to the pedestal level detection circuit 12,
The pedestal level detection circuit 12 detects the pedestal level of the digital video signal based on the pedestal position signal.

The center level output circuit 13 includes an adder 14
And a divider 15. The sync tip level of the sync tip level detection circuit 10 and the pedestal level of the pedestal level detection circuit 12 are guided to the adder 14,
The adder 14 adds the two levels to obtain a divider 15
Output to. The divider 15 outputs the output level of the adder 14 to the terminal b of the selection circuit 7 as a level obtained by dividing the output level by 2, that is, a level of ½.

The selection circuit 7 selects either the slice level value (a terminal side) of the slice level variable output circuit 8 or the output (b terminal side) of the center level output circuit 13, and the switching will be described below. It is controlled by the switching control signal of the microcomputer 17.

The sync signal detection circuit 16 includes a comparator 6
Is output, and the sync signal detection circuit 16 detects from the output of the comparator 6 whether or not a sync signal is obtained. Then, for example, an L signal is output to the microcomputer 17 during the period when the synchronization signal is not obtained, and an H signal is output to the microcomputer 17 during the period when the synchronization signal is obtained.

Microcomputer 17 as control means
Controls each circuit based on a built-in software program including the above-mentioned control. The contents of the soft program will be explained together with the following operations.

The operation of the above configuration will be described below with reference to the operation flow of FIG. When a digital video signal is input,
The microcomputer 17 outputs a switching control signal to the selection circuit 7 to set the selection circuit 7 to the a terminal side and outputs a reset signal to the slice level variable output circuit 8. Then, the slice level value of the slice level variable output circuit 8 is reset to zero. The slice level value of the slice level variable output circuit 8 is input to the comparator 6 via the selection circuit 7 and compared there with the digital video signal.

The slice level value of the slice level variable output circuit 8 gradually increases, but as shown in FIG. 3A, the output of the comparator 6 remains at the H level during the period in which the sync chip level of the digital video signal is not exceeded. is there. When the slice level value exceeds the sync chip level of the digital video signal as shown in FIG. 3B, the output of the comparator 6 becomes L level in the sync signal portion of the digital video signal, and the output of the comparator 6 is more synchronized. The signal is obtained.

When a sync signal is obtained from the output of the comparator 6, the sync signal detection circuit 16 detects it and outputs it to the microcomputer 17. Then, the microcomputer 17 outputs a count-up prohibition signal to the slice level variable output circuit 8 and the slice level value of the slice level variable output circuit 8 is fixed. Since this slice level value exceeds the sync chip level of the digital video signal, the sync signal continues to be output from the comparator 6.

When the sync signal is obtained from the output of the comparator 6, the sync chip position signal generation circuit 9 detects the sync chip position and outputs the sync chip position signal, as shown in FIG. Based on this, the sync chip level detection circuit 10 detects the sync chip level of the digital video signal. Further, the pedestal position signal generation circuit 11 detects the pedestal position and outputs a pedestal position signal. Based on this, the pedestal level of the digital video signal is detected. The center level detection circuit 13 adds the sync tip level and the pedestal level and halves them to calculate the center level.

On the other hand, the microcomputer 17 fixes the slice level value of the slice level variable output circuit 8 and then outputs a switching control signal to the selection circuit 7 to set the selection circuit 7 to the b terminal side. Then, the center level detection circuit 13
Is guided to the comparator 6 via the selection circuit 7, and the center level value is set as the slice level value. This new slice level value is exactly the intermediate value between the sync tip level and the pedestal level of the digital video signal, so that the sync separation is surely performed. That is, even if the level of the sync signal of the digital video signal is unknown,
Even if the level of the sync signal changes, the sync can be reliably separated.

When the level of the sync signal of the digital video signal fluctuates and the sync signal cannot be obtained from the output of the comparator 6, the sync signal detection circuit 16 detects this and the microcomputer 17 repeats the above control. . Since the slice level value (center level value) based on the new sync signal level is set, even if the sync signal level of the digital video signal fluctuates, sync separation is performed. Further, when both the amplitudes of the sync signals fluctuate, the slice level value is set to the exact intermediate value of the sync signal that fluctuates, so that stable sync separation can be performed.

In the above embodiment, the center level output circuit 13 is configured to output just the intermediate value between the sync tip level and the pedestal level, but it may be configured to output a value having a certain width as the intermediate value. .

In the above embodiment, when the synchronizing signal is obtained from the output of the comparator 6, the intermediate value between the sync tip level and the pedestal level of the digital video signal is calculated, and this intermediate value is used as the slice level of the slice level variable output circuit 8. I configured it to be a slice level value instead of a value,
The slice level value of the slice level variable output circuit 8 may be used as it is. Then, the level of the sync signal of the digital video signal fluctuates, and the comparator 6
When the sync signal is no longer obtained from the output of, the slice level variable output circuit 8 is reset and control is performed again to find a value in which the slice level value exceeds the sync chip level of the digital video signal. Even in the case of such a configuration, even if the level of the sync signal of the digital video signal is unknown, the sync separation can be surely performed and the circuit scale can be reduced as compared with the above embodiment.

When the waveform of the digital video signal is an inverted waveform of the waveform of FIG. 3, the slice level variable output circuit 8 is configured to gradually reduce the slice level value of the output signal from the maximum value. It consists of a down counter.

[0028]

As described above, according to the present invention, a comparator for comparing a digital video signal with a slice level value of a slice level variable output circuit is provided, and the slice level value is gradually changed to enable the comparator. When the sync signal is obtained from the output, the variable slice level of the above-mentioned variable slice level output is configured to stop, so even if the sync signal level of the digital video signal is unknown, the sync signal level Even if fluctuates, there is an effect that the sync separation can be surely performed.

According to another aspect of the present invention, a comparator for comparing the digital video signal with the slice level value of the slice level variable output circuit is provided, and the slice level value is gradually changed to synchronize with the output of the comparator. When a signal is obtained, the sync tip level and pedestal level of the digital video signal are detected based on the position of this sync signal, and the intermediate value of both levels is provided to the comparator as a slice level value. Even if the sync signal level is unknown, sync separation can be performed, and even if the sync signal level of the digital video signal fluctuates and the sync signal amplitude fluctuates, reliable and stable sync separation is possible. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of a sync separation circuit (embodiment).

FIG. 2 is an operation flowchart of the sync separation circuit (embodiment).

3A and 3B are diagrams (examples) showing the magnitude of a digital video signal and a slice level value, respectively.

FIG. 4 is a time chart of each signal (example).

FIG. 5 is a circuit block diagram of a video signal processing system (embodiment).

[Explanation of symbols]

 3 ... Sync separation circuit 6 ... Comparator 7 ... Selection circuit 8 ... Slice level variable output circuit 10 ... Sync tip level detection circuit 12 ... Pedestal level detection circuit 13 ... Center level output circuit 16 ... Sync signal detection circuit 17 ... Microcomputer (control means).

Claims (2)

[Claims] 1. A slice level variable output circuit capable of gradually varying the size of a slice level value of an output signal, and a comparator for comparing the slice level value of this slice level variable output circuit with the level of a digital video signal, A sync signal detection circuit that detects whether a sync signal is obtained from the output of the comparator, and if this sync signal detection circuit cannot detect the sync signal, the slice level variable output circuit gradually changes the slice level value from the initial value. And a control means for controlling so that the slice level variable output circuit stops changing the slice level value when the synchronization signal detection circuit detects the synchronization signal. And sync separation circuit. 2. A slice level variable output circuit capable of gradually varying the size of a slice level value of an output signal, and a slice level value of the slice level variable output circuit and a slice level value of a center level output circuit described below. A selection circuit that selects either one of them, a comparator that compares the slice level value selected by this selection circuit with the level of the digital video signal, and a synchronization signal detection that detects whether a synchronization signal can be obtained from the output of this comparator. A circuit, a sync chip level detection circuit for detecting a sync chip level of the digital video signal when a sync signal is obtained from the output of the comparator, and a pedestal level of the digital video signal when a sync signal is obtained from the output of the comparator Pedestal level detection circuit, and the sync tip level A center level output circuit that outputs an intermediate value between the sync tip level detected by the red detection circuit and the pedestal level detected by the pedestal level detection circuit as a slice level value; and the synchronization signal detection circuit cannot detect the synchronization signal, The selection circuit selects a slice level value of the slice level variable output circuit, and controls the slice level variable output circuit to gradually change the slice level value from an initial value, and the synchronization signal detection circuit When a sync signal is detected, the slice level variable output circuit is controlled so as to stop changing the slice level value, and the pedestal level and the sync tip level are respectively supplied to the pedestal level detection circuit and the sync tip level detection circuit. And the selection circuit detects the center level. And a control means for controlling the slice level of the output circuit to be selected.