JPH0818353A - Operational amplifier circuit - Google Patents

Operational amplifier circuit

Info

Publication number
JPH0818353A
JPH0818353A JP6153150A JP15315094A JPH0818353A JP H0818353 A JPH0818353 A JP H0818353A JP 6153150 A JP6153150 A JP 6153150A JP 15315094 A JP15315094 A JP 15315094A JP H0818353 A JPH0818353 A JP H0818353A
Authority
JP
Japan
Prior art keywords
amplifier
state
main amplifier
input
auxiliary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6153150A
Other languages
Japanese (ja)
Inventor
Hidetoshi Fujimoto
英俊 藤本
Kenichi Arimura
健一 有村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP6153150A priority Critical patent/JPH0818353A/en
Publication of JPH0818353A publication Critical patent/JPH0818353A/en
Pending legal-status Critical Current

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  • Electronic Switches (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To reduce the error brought about in an amplified signal value by compensating the offset generated in an operational amplifier without especially expending labor on adjustment of a correction circuit. CONSTITUTION:A main amplifier 10, a main switch means 20 which designates the amplification state of giving an input signal Vi to the main amplifier and the reset state of connecting its two inputs to the same potential, an auxiliary amplifier 30 which receives the output signal of the main amplifier 10 to perform operational amplification in the opposite direction, a holding means 40 which holds its output signal value to feed back it to the main amplifier 10, and an auxiliary switch means 50 which connects or disconnects this means 40 and the auxiliary amplifier 30 are provided. After the auxiliary switch means 50 is set to the connected state in the reset state and the offset compensation signal value is held in the holding means 40, the auxiliary switch means 50 is set to the disconnected state in the next amplification state to give the compensation signal value to the main amplifier 10, and in this state, an amplified signal Vo is taken out from its output. Thus, the offset error is reduced to about 1/(the gain of the main amplifier 10).

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は信号の演算増幅の際に不
可避的に発生するいわゆるオフセットを減少させるため
の演算増幅回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operational amplifier circuit for reducing a so-called offset that is inevitably generated during operational amplification of a signal.

【0002】[0002]

【従来の技術】周知のように、演算増幅器はアナログな
信号の増幅,多くは差動増幅のために広く用いられ、最
近は集積回路に組み込まれるケースが非常に多くなって
おり、バイポーラトランジスタで構成される場合と,M
OSトランジスタで構成される場合とがあるが、いずれ
の場合でも構成トランジスタの特性の不揃い等の原因で
その増幅出力の信号値に固有のふつうは一定の誤差であ
るいわゆるオフセットが若干とも必ず発生する。このた
め、オフセットが許容できない用途では従来からその補
正回路を追加する必要があり、とくに集積回路ではそれ
を外付け接続するために補正端子を導出する必要があ
る。図5は演算増幅器に外付けの補正回路を接続する代
表的な例を簡略に示すものである。
2. Description of the Related Art As is well known, operational amplifiers are widely used for amplification of analog signals, and most of them are differential amplification. Recently, operational amplifiers are often incorporated in integrated circuits. When configured, M
It may be composed of an OS transistor, but in any case, a so-called offset, which is usually a constant error, is always peculiar to the signal value of the amplified output due to non-uniformity of the characteristics of the constituent transistors. . For this reason, it is necessary to add a correction circuit to the conventional case where the offset is unacceptable, and particularly in an integrated circuit, it is necessary to derive a correction terminal to externally connect the correction circuit. FIG. 5 schematically shows a typical example in which an external correction circuit is connected to the operational amplifier.

【0003】図5において、入力信号Viを出力信号Voに
増幅する演算増幅器70は図の例では反転増幅用であり、
通例のように入力信号Viを入力抵抗71を介しその反転入
力に与え、かつこの反転入力と出力の間に帰還抵抗72を
接続して両抵抗の抵抗値比により増幅度を設定するよう
になっており、その非反転入力は図の例では抵抗73を介
して基準電位, 例えば接地電位を受けている。この演算
増幅回路に図の左側の部分に示す補正回路80を接続する
ため演算増幅器70の反転入力から補正端子Tcが導出され
ている。補正回路80は反転入力に与えるオフセット補正
用の電圧ないし電流を発生するもので、例えば図示のよ
うに正の電圧を受ける調整抵抗81による設定電圧を抵抗
82を介して補正端子Tcに与えるようになっている。
In FIG. 5, an operational amplifier 70 for amplifying an input signal Vi into an output signal Vo is for inverting amplification in the example of the figure,
As usual, the input signal Vi is applied to its inverting input via the input resistor 71, and the feedback resistor 72 is connected between this inverting input and the output to set the amplification degree by the resistance value ratio of both resistors. The non-inverting input receives the reference potential, for example, the ground potential via the resistor 73 in the example of the figure. The correction terminal Tc is derived from the inverting input of the operational amplifier 70 in order to connect the correction circuit 80 shown on the left side of the figure to this operational amplifier circuit. The correction circuit 80 generates a voltage or current for offset correction given to the inverting input. For example, as shown in FIG.
It is adapted to be given to the correction terminal Tc via 82.

【0004】[0004]

【発明が解決しようとする課題】しかし、オフセットの
補正回路を上述のように外付けにしたのでは当然ながら
回路を集積化した効果が低下し、オフセット補正を要す
る多数の演算増幅回路を組み込む必要がある場合は集積
化する目的そのものが怪しくなって来る。また、集積化
しない場合でも各演算増幅回路ごとに補正回路に発生さ
せる電圧や電流を実際のオフセット値に合わせて設定す
る必要があるので、その際の調整に手間が少なからず掛
かってしまう問題がある。
However, if the offset correction circuit is externally attached as described above, the effect of circuit integration is naturally reduced, and it is necessary to incorporate a large number of operational amplifier circuits that require offset correction. If there is, the purpose of integration itself becomes questionable. In addition, even if it is not integrated, it is necessary to set the voltage and current generated in the correction circuit for each operational amplifier circuit according to the actual offset value. is there.

【0005】かかる問題点に鑑みて、本発明はオフセッ
ト補正回路を集積回路に外付けする必要がなく、かつ補
正回路の調整のためにとくに手間を要しない演算増幅回
路を提供することを目的とするものである。
In view of such problems, it is an object of the present invention to provide an operational amplifier circuit which does not require an offset correction circuit to be externally attached to an integrated circuit and which does not require any special labor for adjusting the correction circuit. To do.

【0006】[0006]

【課題を解決するための手段】本発明では入力信号を演
算増幅する主増幅器に対し、それに入力信号を与える増
幅状態とその2入力を同電位に接続するリセット状態と
を指定する主スイッチ手段と, 主増幅器の出力信号を受
けそれと逆方向に演算増幅する補助増幅器と,補助増幅
器の出力信号の値を保持して主増幅器の入力側に帰還す
る保持手段と,保持手段に対する補助増幅器の出力信号
の賦与状態と分離状態とを指定する補助スイッチ手段と
を設け、リセット状態では補助スイッチ手段を賦与状態
におき、増幅状態では補助スイッチ手段を分離状態にお
いて主増幅器の出力を増幅信号として取り出すことによ
って上述の目的を達成する。
According to the present invention, there is provided main switch means for designating, for a main amplifier which performs operational amplification of an input signal, an amplification state in which the input signal is applied and a reset state in which two inputs thereof are connected to the same potential. An auxiliary amplifier that receives the output signal of the main amplifier and performs operational amplification in the opposite direction, holding means that holds the value of the output signal of the auxiliary amplifier and returns it to the input side of the main amplifier, and the output signal of the auxiliary amplifier to the holding means. By providing the auxiliary switch means for designating the applied state and the separated state of the main switch, the auxiliary switch means is placed in the applied state in the reset state, and in the amplified state, the output of the main amplifier is taken out as the amplified signal in the separated state of the auxiliary switch means. The above objective is achieved.

【0007】なお、上記構成にいう主増幅器と補助増幅
器の演算増幅の方向は例えば前者が反転増幅のとき後者
に非反転増幅の動作をさせるものとする。また、両者の
入力信号や主増幅器の出力信号を受ける入力以外の入力
を相互に接続して一定電位を共通に賦与するのが両者の
関連動作を正確にする上で望ましい。さらに、保持手段
は最も簡単にはキャパシタとすることでもよいが、その
保持動作を確実にするにはこれを補助増幅器の出力信号
を受けるキャパシタと,その充電電圧を受けて同じ電圧
値を出力する演算増幅器を用いるホールド回路とから構
成するのがよい。いずれの場合でも、主スイッチにより
本発明回路のリセット状態と増幅状態とを所定の短い周
期で反復指定するのが動作状態中の保持手段の保持値を
正確にする上で非常に有利である。
The directions of operational amplification of the main amplifier and the auxiliary amplifier in the above configuration are such that, for example, when the former is inverting amplification, the latter is operated as non-inverting amplification. Further, it is desirable to connect the inputs other than the input signals of both and the input signal for receiving the output signal of the main amplifier to each other so as to commonly apply a constant potential in order to make the related operation of both of them accurate. Further, the holding means may be a capacitor in the simplest case, but in order to ensure the holding operation, the holding means outputs the same voltage value as the capacitor receiving the output signal of the auxiliary amplifier and the charging voltage thereof. A hold circuit using an operational amplifier is preferable. In any case, it is very advantageous to use the main switch to repeatedly specify the reset state and the amplification state of the circuit of the present invention at a predetermined short cycle in order to make the holding value of the holding means accurate during the operating state.

【0008】本発明の有利な実施態様では保持手段に単
一のキャパシタを用い、これを補助増幅器の一方の入力
と出力との間に接続し、かつ主増幅器の出力と補助増幅
器の他方の入力との間に補助スイッチ手段を挿入するこ
とによって回路の全体構成の簡略化を図る。本発明の別
の有利な実施態様では、主増幅器の入力信号を受けるべ
き入力側にサンプリングスイッチ手段を挿入するととも
に、1個のサンプルホールド回路を主増幅器を利用し
て,例えばその入力と出力の間にキャパシタを接続する
ことにより構成して、サンプリングスイッチ手段を本発
明回路の増幅状態の間にオンのサンプリング指定状態か
らオフのホールド指定状態に切り換えることにより増幅
信号を主増幅器自体にサンプルホールドさせておき、こ
れを必要に応じた適宜なタイミングで取り出し得るよう
にする。
A preferred embodiment of the invention uses a single capacitor for the holding means, which is connected between one input and the output of the auxiliary amplifier and which outputs the main amplifier and the other input of the auxiliary amplifier. By inserting an auxiliary switch means between and, the overall configuration of the circuit is simplified. In another advantageous embodiment of the invention, sampling switch means is inserted on the input side of the main amplifier which is to receive the input signal and one sample and hold circuit is used for the main amplifier, for example for its input and output. A capacitor is connected between the sampling switch means and the sampling signal is sampled and held by the main amplifier itself by switching the sampling switch means from the sampling designation state of ON to the hold designation state of OFF during the amplification state of the circuit of the present invention. In advance, this can be taken out at an appropriate timing as needed.

【0009】本発明のさらに異なる有利な実施態様で
は、主増幅器の入力信号を受ける入力から入力端子を,
出力から出力端子をそれぞれ導出しておいて、入力端子
に入力信号を受ける入力抵抗を,入力端子と出力端子の
間に帰還抵抗をそれぞれ外付け接続することにより、本
発明回路に賦与すべき増幅率を所望値に指定,ないしは
随時変更できるようにする。また、主増幅器の入力信号
用以外の入力および補助増幅器の主増幅器の出力信号を
受ける入力以外の入力の前述の相互接続点からも電位端
子を導出しておき、指定増幅率に適した一定の電位を外
部から賦与できるようにしておくのが便利である。な
お、かかる態様では主増幅器の一対の入力の相互間に抵
抗を固定接続し、かつ主スイッチ手段を単純なオンオフ
動作形にしておき、本発明回路に対しそのオンにより増
幅状態を,オフによりリセット状態をそれぞれ指定でき
るようにするのが有利である。
In a further advantageous embodiment of the invention, the input terminal of the main amplifier receives the input signal from the input terminal,
The output terminals are derived from the outputs, and the input resistors for receiving the input signals are externally connected to the input terminals, and the feedback resistors are externally connected between the input terminals and the output terminals. Designate the rate to a desired value or change it at any time. The potential terminals are also derived from the above-mentioned interconnection points of the inputs other than the input signal of the main amplifier and the input other than the input of the auxiliary amplifier for receiving the output signal of the main amplifier, and the constant potential suitable for the designated amplification factor is obtained. It is convenient to be able to apply the electric potential from the outside. In such a mode, a resistor is fixedly connected between a pair of inputs of the main amplifier, and the main switch means is made into a simple on / off operation type, and the amplification state is reset by turning on the circuit of the present invention and reset by turning off. It is advantageous to be able to specify each state.

【0010】[0010]

【作用】本発明は演算増幅回路の動作状態を入力信号に
対する増幅状態と, いわばその準備用のリセット状態と
に分け、まずリセット状態では主増幅器のオフセットを
補償するための信号値を補助増幅器に発生させて保持手
段により保持しておき、これに続く増幅状態では主増幅
器にこの補償用の信号保持値によりオフセットを補償し
ながら正規の増幅作用を行なわせてそれからオフセット
誤差のごく少ない増幅信号を取り出すようにするもので
ある。
According to the present invention, the operation state of the operational amplifier circuit is divided into an amplification state for an input signal and, so to speak, a reset state for its preparation. First, in the reset state, a signal value for compensating the offset of the main amplifier is supplied to the auxiliary amplifier. After being generated and held by the holding means, in the subsequent amplification state, the main amplifier is caused to perform a normal amplification operation while compensating the offset by this signal holding value for compensation, and then an amplified signal with a very small offset error is generated. It should be taken out.

【0011】このため前項の構成にいうように本発明の
演算増幅回路では、入力信号を演算増幅すべき主増幅器
に付随して主スイッチ手段をまず設けて、これに増幅状
態とリセット状態とを指定させながら,増幅状態では主
増幅器に入力信号を与えるがリセット状態では2入力を
同電位接続して信号入力を完全になくすようにする。ま
た、主増幅器の出力信号を受けてそれと逆方向に演算増
幅する補助増幅器と,その出力信号の信号値を保持する
保持手段と, それへの補助増幅器の出力信号の賦与状態
と分離状態を指定する補助スイッチ手段とを設ける。
Therefore, in the operational amplifier circuit of the present invention as described in the above paragraph, the main switch means is first provided in association with the main amplifier for operational amplification of the input signal, and the main switch means is set to the amplification state and the reset state. While designating, the input signal is supplied to the main amplifier in the amplification state, but in the reset state, the two inputs are connected to the same potential to completely eliminate the signal input. Also, an auxiliary amplifier that receives the output signal of the main amplifier and performs operational amplification in the opposite direction, holding means that holds the signal value of the output signal, and the state of giving and separating the output signal of the auxiliary amplifier to it are specified. Auxiliary switch means is provided.

【0012】このように構成された本発明回路では、リ
セット状態では補助スイッチ手段を賦与状態にして補助
増幅器の出力信号値を保持手段に与え,保持値を主増幅
器の入力側に帰還,制御原理上は負帰還することにより
主増幅器がもつオフセットを補償しておき、次の増幅状
態では補助スイッチ手段を分離状態にして保持手段に保
持値をそのまま維持させることにより主増幅器のオフセ
ットを補償した状態でその出力を増幅信号として取り出
すようにする。
In the circuit of the present invention having such a configuration, in the reset state, the auxiliary switch means is set to the applied state, the output signal value of the auxiliary amplifier is given to the holding means, and the held value is fed back to the input side of the main amplifier to control the principle. Above is the state in which the offset of the main amplifier is compensated by performing negative feedback, and in the next amplification state, the auxiliary switch means is separated and the holding means keeps the held value as it is to compensate the offset of the main amplifier. Then, the output is taken out as an amplified signal.

【0013】従って、本発明では主増幅器のオフセット
を原理的には完全に補償できるが、実際には補助増幅器
にもオフセットがあるために若干の誤差が発生する。い
ま、主増幅器と補助増幅器がもつオフセットをそれぞれ
δmとδaとし,主増幅器の増幅率ないしはゲインをGm
とすると、増幅信号のオフセット誤差の本発明による減
少率は後述のようにほぼδa /Gmδm となり、δm とδ
a が同じ程度であるとするとこの減少率は1/Gmとな
る。これからわかるよう、本発明では主増幅器のゲイン
Gmを利用してオフセット誤差を減少させることができ、
例えばゲインGmを100とすると増幅信号のオフセット誤
差は従来の約1%に減少する。
Therefore, in the present invention, the offset of the main amplifier can be completely compensated in principle, but in reality, the auxiliary amplifier also has an offset, so that a slight error occurs. Now, let the offsets of the main amplifier and the auxiliary amplifier be δm and δa, respectively, and let the amplification factor or gain of the main amplifier be Gm.
Then, the reduction rate of the offset error of the amplified signal according to the present invention becomes approximately δa / Gmδm as described later, and δm and δm
If a is the same, this reduction rate is 1 / Gm. As can be seen, in the present invention, the gain of the main amplifier is
Offset error can be reduced using Gm,
For example, when the gain Gm is 100, the offset error of the amplified signal is reduced to about 1% of the conventional value.

【0014】[0014]

【実施例】以下、図を参照して本発明の若干の実施例を
説明する。図1〜図4は本発明のそれぞれ異なる実施例
を示す演算増幅回路の回路図であり、いずれにも対応す
る部分に同じ符号が付けられている。なお、これら実施
例のいずれでも便宜上から主増幅器が反転増幅形であ
り, 補助増幅器が非反転増幅形であるするが、本発明で
は両増幅器に互いに逆方向の演算増幅をさせれば足り、
従って主増幅器の方を非反転増幅形とし, 補助増幅器の
方を反転増幅形としても両者の動作上の電位を適宜に選
定しさえすればなんら支障は生じない。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention will be described below with reference to the drawings. 1 to 4 are circuit diagrams of operational amplifier circuits each showing a different embodiment of the present invention, and the same reference numerals are given to corresponding portions. In any of these embodiments, the main amplifier is an inverting amplification type and the auxiliary amplifier is a non-inverting amplification type for the sake of convenience, but in the present invention, it suffices to have both amplifiers perform operational amplification in opposite directions.
Therefore, even if the main amplifier is of the non-inverting amplification type and the auxiliary amplifier is of the inverting amplification type, no problem will occur as long as the operating potentials of both are appropriately selected.

【0015】図1において、主増幅器10は入力信号Viを
反転入力の方に受ける反転増幅形であり、通例のように
入力抵抗11に対する帰還抵抗12の抵抗値比により設定さ
れた増幅率で増幅動作を行なう演算増幅器であって、そ
の非反転入力には所定の基準電圧Vrが賦与されている。
その入力側に挿入された主スイッチ手段20は切り換え動
作の電子スイッチであり、図示の状態で入力信号Viを主
増幅器10に与える増幅状態を指定し、図とは反対の状態
で主増幅器10の両入力を入力抵抗11を介し同じ電位に接
続するリセット状態を指定する。
In FIG. 1, a main amplifier 10 is an inverting amplification type which receives an input signal Vi toward its inverting input, and amplifies it with an amplification factor set by a resistance value ratio of a feedback resistor 12 to an input resistor 11 as usual. This is an operational amplifier that operates, and a predetermined reference voltage Vr is applied to its non-inverting input.
The main switch means 20 inserted on the input side is an electronic switch for switching operation, and specifies the amplification state in which the input signal Vi is given to the main amplifier 10 in the state shown, and the main amplifier 10 in the state opposite to that shown in the figure. A reset state is specified in which both inputs are connected to the same potential via input resistor 11.

【0016】補助増幅器30は主増幅器10とは逆方向の非
反転増幅動作を行なう演算増幅器であって、主増幅器10
の出力をその非反転入力に受け、その反転入力は図の例
では主増幅器10の非反転入力と接続されて同じ基準電圧
Vrを共通に受けている。図の左上部に一点鎖線で囲んで
示された保持手段40はこの実施例では補助増幅器30の出
力信号を受けるキャパシタ41と, その充電電圧を受けて
同じ電圧値を出力するホールド動作の演算増幅器42から
構成され、その保持信号値を別の帰還抵抗13を介して主
増幅器10の反転入力に与える。この演算増幅器42による
ホールド回路は主増幅器10がバイポーラトランジスタを
用いる電流動作形のときキャパシタ41の充電状態を保全
する役目を果たす。この保持手段40と補助増幅器30の出
力側との間に挿入された補助スイッチ手段50はオンオフ
動作の電子スイッチであり、そのオンで補助増幅器30の
出力信号を保持手段40に与える賦与状態を指定し、オフ
で保持手段40の補助増幅器30からの分離状態を指定す
る。
The auxiliary amplifier 30 is an operational amplifier which performs a non-inverting amplification operation in a direction opposite to that of the main amplifier 10.
At its non-inverting input, whose inverting input is connected to the non-inverting input of the main amplifier 10
We receive Vr in common. In this embodiment, the holding means 40 shown in the upper left part of the figure by the one-dot chain line is a capacitor 41 for receiving the output signal of the auxiliary amplifier 30 and an operational amplifier for holding operation for receiving the charging voltage and outputting the same voltage value. 42, and supplies the held signal value to the inverting input of the main amplifier 10 via another feedback resistor 13. The hold circuit by the operational amplifier 42 serves to maintain the charge state of the capacitor 41 when the main amplifier 10 is a current operation type using a bipolar transistor. The auxiliary switch means 50 inserted between the holding means 40 and the output side of the auxiliary amplifier 30 is an electronic switch for ON / OFF operation, and when the auxiliary switch means 50 is turned on, the state of giving the output signal of the auxiliary amplifier 30 to the holding means 40 is designated. Then, the off state designates the separation state of the holding means 40 from the auxiliary amplifier 30.

【0017】以上のように構成された本発明の演算増幅
回路では、主スイッチ手段20によりリセット状態と増幅
状態とを交互に所定周期で反復指定するのがよく、リセ
ット状態では補助スイッチ手段50を賦与状態におき、増
幅状態ではこれを分離状態において主増幅器10の出力か
ら増幅信号Voを取り出すようにする。まず、リセット状
態について説明すると、主増幅器10には入力がないから
オフセットがなければその出力信号値は基準電圧Vrにな
るはずであるが、実際には最大でも数mVと僅かではある
がオフセットδm が入力側にあり、これが主増幅器10の
ゲインGmにより増幅されるので出力電圧値は基準電圧Vr
からGmδm だけずれて来る。このずれは補助増幅器30に
よりそのゲインGaだけ逆の方向に増幅されて保持手段40
を介して主増幅器10の入力側にオフセットδm を補償す
るよう負帰還される。
In the operational amplifier circuit of the present invention constructed as described above, it is preferable that the reset state and the amplified state are alternately and repeatedly designated by the main switch means 20 in a predetermined cycle, and the auxiliary switch means 50 is designated in the reset state. In the giving state, in the amplifying state, the amplified signal Vo is taken out from the output of the main amplifier 10 in the separating state. First, the reset state will be explained. Since there is no input in the main amplifier 10, its output signal value should be the reference voltage Vr if there is no offset. Is on the input side, and this is amplified by the gain Gm of the main amplifier 10, so the output voltage value is the reference voltage Vr.
Deviates by Gmδm from. This deviation is amplified in the opposite direction by the gain Ga by the auxiliary amplifier 30, and the holding means 40
Is negatively fed back to the input side of the main amplifier 10 to compensate the offset Δm.

【0018】しかし、補助増幅器30側にもオフセットδ
a があり、これもそのゲインGaだけ増幅されて負帰還さ
れる信号値に加わって来る。そこで、このリセット状態
での主増幅器10の出力信号値の基準電圧Vrからのずれを
仮にeとすると、これと補助増幅器30のオフセットδa
の和e+δa がゲインGaだけ増幅されて保持手段40に与
えられ、これが主増幅器10の入力側に帰還されてそのオ
フセットδm とともにゲインGmだけ増幅されてずれeに
なるのであるから、次式が成立する。
However, the offset δ also exists on the auxiliary amplifier 30 side.
There is a, and this also adds to the signal value that is negatively fed back after being amplified by that gain Ga. Therefore, assuming that the deviation of the output signal value of the main amplifier 10 from the reference voltage Vr in this reset state is e, this is offset by the offset δa of the auxiliary amplifier 30.
The sum e + δa of the above is amplified by the gain Ga and given to the holding means 40, and this is fed back to the input side of the main amplifier 10 and amplified by the gain Gm together with the offset δm to become the deviation e, so that the following equation holds. To do.

【0019】e=−GmGa (e+δa)−Gmδm この式をeについて解くと次式が得られる。 e=−δa G/(1+G) −δm Gm/(1+G) ただしG=GmGaであり、この系全体のゲインGは非常に
大きく、さらに上式中の第2項は第1項よりずっと小さ
いから、実用的にはごく簡単に、 e=−δa としても差し支えない。
E = -GmGa (e + δa) -Gmδm By solving this equation for e, the following equation is obtained. e = −δa G / (1 + G) −δm Gm / (1 + G) However, G = GmGa, the gain G of the whole system is very large, and the second term in the above equation is much smaller than the first term. In practice, it is very easy to set e = -δa.

【0020】次に、増幅状態では補助スイッチ手段50を
分離状態におき、かつ主増幅器10に入力信号Viを与えて
基準電圧Vrとの差を増幅させるが、この際にもリセット
状態から引き続いて保持手段40に保持されている信号値
が主増幅器10の入力側に与えられるので、それに対応す
る上式によるずれeがこの増幅状態でも主増幅器10の出
力信号に重複することになり、このずれeが本発明の演
算増幅回路による増幅信号Voに生じるオフセット誤差と
して残る。
Next, in the amplification state, the auxiliary switch means 50 is placed in the separation state, and the input signal Vi is given to the main amplifier 10 to amplify the difference from the reference voltage Vr. At this time, the reset state is continued. Since the signal value held in the holding means 40 is given to the input side of the main amplifier 10, the shift e corresponding to the above equation overlaps with the output signal of the main amplifier 10 even in this amplification state. e remains as an offset error generated in the amplified signal Vo by the operational amplifier circuit of the present invention.

【0021】この本発明回路のオフセット誤差eないし
δa の値をオフセット補償をしない場合と比較すると、
補償なしの時は主増幅器10のオフセットδm が前述のよ
うにゲインGmにより増幅されて出力信号値にGmδm だけ
のずれが発生するはずであるから、前の作用の項で述べ
たように本発明による増幅信号Voのオフセット誤差の減
少率rはほぼ次式で表せる。
Comparing the values of the offset errors e to δa of the circuit of the present invention with the case without offset compensation,
When there is no compensation, the offset δm of the main amplifier 10 should be amplified by the gain Gm as described above and a deviation of Gmδm should occur in the output signal value. The reduction rate r of the offset error of the amplified signal Vo due to is approximately expressed by the following equation.

【0022】r=δa /Gmδm = (δa/δm)・1/Gm これからわかるように、補助増幅器30側にオフセットδ
a がなけれは誤差は0になるが、δa は主増幅器10側の
δm とふつう同程度なのでr=1/Gmとしてよい。このよ
うに主増幅器10のゲインGmが高いほど増幅信号Voのオフ
セット誤差を減少させ得るのは本発明の一つの利点であ
る。
R = δa / Gm δm = (δa / δm) 1 / Gm As can be seen, the offset δ on the auxiliary amplifier 30 side
If a is not present, the error will be 0, but since δa is almost the same as δm on the main amplifier 10 side, r = 1 / Gm may be set. It is one of the advantages of the present invention that the offset error of the amplified signal Vo can be reduced as the gain Gm of the main amplifier 10 is higher.

【0023】なお、前述のように増幅信号Voに生じるオ
フセット誤差eが補助増幅器30側のオフセットδa とほ
ぼ等しくなる理由は、主増幅器10側のオフセットδm が
補助増幅器30と保持手段40によってほぼ完全に補償され
るに対し、補助増幅器30側のオフセットδa の方にはと
くに補償手段がなくほぼそのまま残ってしまうためと考
えられる。また、この図1の実施例のように保持手段40
にホールド動作の演算増幅器42を組み込む場合はそのオ
フセットも実際には加わって来るが、この演算増幅器42
の増幅率は1であってそのオフセットは主増幅器10の入
力側にそのまま加えられるので、主増幅器10のオフセッ
トδm とともに補助増幅器30によりほぼ完全に補償され
るものとしてよい。
As described above, the reason why the offset error e generated in the amplified signal Vo is almost equal to the offset δa on the auxiliary amplifier 30 side is that the offset δm on the main amplifier 10 side is almost perfect by the auxiliary amplifier 30 and the holding means 40. It is considered that the offset Δa on the auxiliary amplifier 30 side has almost no compensation means, and the offset Δa on the auxiliary amplifier 30 side remains almost as it is. Further, as in the embodiment of FIG. 1, the holding means 40
If the operational amplifier 42 for hold operation is installed in the, the offset is actually added, but this operational amplifier 42
The amplification factor is 1 and the offset is added to the input side of the main amplifier 10 as it is, so that it may be almost completely compensated by the auxiliary amplifier 30 together with the offset Δm of the main amplifier 10.

【0024】図2に示す実施例では保持手段としてのキ
ャパシタ41を例えば図のように補助増幅器30の反転入力
と出力の間に接続して、補助増幅器30に出力値の保持機
能をもたせることにより回路構成を簡易化する。また、
これに対応して補助スイッチ手段50を主増幅器10の出力
側と補助増幅器30の入力側, 図示の例ではその非反転入
力との間に挿入する。他の部分の回路構成は図1と同じ
であり、この実施例の回路動作および増幅信号Voのオフ
セット誤差を減少させる効果もほぼ同様であるから重複
を避けるため説明を省略する。
In the embodiment shown in FIG. 2, a capacitor 41 as a holding means is connected, for example, between the inverting input and the output of the auxiliary amplifier 30 as shown in the figure, so that the auxiliary amplifier 30 has a function of holding the output value. Simplify the circuit configuration. Also,
Correspondingly, the auxiliary switch means 50 is inserted between the output side of the main amplifier 10 and the input side of the auxiliary amplifier 30, that is, its non-inverting input in the illustrated example. The circuit configuration of the other portions is the same as that of FIG. 1, and the circuit operation and the effect of reducing the offset error of the amplified signal Vo of this embodiment are almost the same, and therefore the description thereof will be omitted to avoid duplication.

【0025】次の図3の実施例では主増幅器10によりサ
ンプルホールド回路を構成し、それから増幅信号Voを随
時ないしは適宜なタイミングで読み出せるようにする。
このため、図1の主増幅器10用の帰還抵抗12のかわりに
キャパシタ14を増幅信号Voのホールド用に接続するとと
もに、主増幅器10の入力側に, 例えば図のように入力抵
抗60に直列にサンプリングスイッチ手段60を挿入する。
他の部分の回路構成は図1と同じである。
In the next embodiment shown in FIG. 3, the main amplifier 10 constitutes a sample and hold circuit, and the amplified signal Vo can be read out at any time or at an appropriate timing.
Therefore, instead of the feedback resistor 12 for the main amplifier 10 of FIG. 1, a capacitor 14 is connected for holding the amplified signal Vo, and is connected to the input side of the main amplifier 10, for example, in series with the input resistor 60 as shown in the figure. The sampling switch means 60 is inserted.
The circuit configuration of the other parts is the same as that of FIG.

【0026】サンプリングスイッチ手段60は単純なオン
オフ形の電子スイッチでよく、図のような挿入位置では
常時はオンの状態にしておき、主スイッチ手段20が図の
切換位置にある増幅状態の期間内にオンのサンプリング
指定状態からオフのホールド指定状態に切り換わるよう
に動作させる。このホールド指定状態では主スイッチ手
段20の状態は任意であってよいが、補助スイッチ手段50
を分離状態にしておくのが望ましい。増幅信号Voは主増
幅器10をこのサンプルホールド状態にした後に適宜なタ
イミングで読み取ることができる。
The sampling switch means 60 may be a simple on-off type electronic switch, and is always turned on at the insertion position as shown in the figure, and the main switch means 20 is in the switching position in the figure and within the amplification state. Then, it is operated so as to switch from the sampling designation state of ON to the hold designation state of OFF. In this hold designation state, the state of the main switch means 20 may be arbitrary, but the auxiliary switch means 50
It is desirable to keep them separated. The amplified signal Vo can be read at an appropriate timing after the main amplifier 10 is put in the sample hold state.

【0027】さらに、図4の実施例では集積回路の中に
組み込まれた主増幅器10の増幅率を外部から所望値に設
定できるようにする。このため、主増幅器10の入力信号
Viを受ける反転入力から入力端子Tiを, その出力から出
力端子Toをそれぞれ導出しておき、細線で示すように入
力抵抗11を入力端子Tiに, 帰還抵抗12を入力端子Tiと出
力端子Toの間にそれぞれ外付け接続し、両抵抗の抵抗値
比により主増幅器10の増幅率を所望値に設定できるよう
にする。また、図の例では主増幅器10の非反転入力と補
助増幅器30の反転入力の相互接続点からも電位端子Tpを
導出しておき、これに主増幅器10の増幅率の設定値に適
合した値の基準電圧Vrの電位を外部から賦与できるよう
になっている。
Further, in the embodiment shown in FIG. 4, the amplification factor of the main amplifier 10 incorporated in the integrated circuit can be externally set to a desired value. Therefore, the input signal of the main amplifier 10
The input terminal Ti is derived from the inverting input that receives Vi, and the output terminal To is derived from that output.As shown by the thin line, the input resistor 11 is the input terminal Ti, and the feedback resistor 12 is the input terminal Ti and the output terminal To. Externally connected to each other so that the amplification factor of the main amplifier 10 can be set to a desired value by the resistance value ratio of both resistors. Further, in the example of the figure, the potential terminal Tp is also derived from the interconnection point of the non-inverting input of the main amplifier 10 and the inverting input of the auxiliary amplifier 30, and a value suitable for the set value of the amplification factor of the main amplifier 10 is derived from this. The potential of the reference voltage Vr can be externally applied.

【0028】この実施例でも図1と同じ切り換え形の主
スイッチ手段20を用いてもよいが、図示の例では主増幅
器10の両入力の相互間に抵抗15を接続するとともに、単
純なオンオフ形の主スイッチ手段21を用いてそのオンに
より増幅状態を, オフによりリセット状態をそれぞれ指
定するようになっている。その他の部分の回路構成は図
1と同じである。主スイッチ手段21がオフのリセット状
態では、主増幅器10の両入力が抵抗15を介して同電位接
続されているので、この図4の実施例の動作は主増幅器
10の増幅率が外部回路により設定されている点を除いて
図1の実施例ととくに異なるところはない。
In this embodiment as well, the same switching type main switching means 20 as in FIG. 1 may be used, but in the illustrated example, a resistor 15 is connected between both inputs of the main amplifier 10 and a simple on / off type is used. The main switch means 21 is used to specify the amplification state when turned on and the reset state when turned off. The circuit configuration of the other parts is the same as that of FIG. In the reset state in which the main switch means 21 is off, both inputs of the main amplifier 10 are connected to the same potential via the resistor 15, so that the operation of the embodiment of FIG.
There is no particular difference from the embodiment of FIG. 1 except that the amplification factor of 10 is set by an external circuit.

【0029】以上説明したいずれの実施例でも主スイッ
チ手段20や21によりリセット状態と動作状態を所定の短
い周期で反復指定するのが保持手段40の信号保持値を正
確に維持する上で有利であり、この反復周波数は例えば
100kHz程度に設定するのがよい。反復周波数をこのよ
うに高く設定すれば、保持手段40内のキャパシタ41を数
〜数十pFの小さな静電容量で済ませることができる。
In any of the embodiments described above, it is advantageous to maintain the signal holding value of the holding means 40 accurately by repeatedly designating the reset state and the operating state by the main switch means 20 and 21 in a predetermined short cycle. Yes, this repetition frequency is
It is better to set it to about 100 kHz. If the repetition frequency is set high in this way, the capacitor 41 in the holding means 40 can have a small capacitance of several to several tens pF.

【0030】[0030]

【発明の効果】以上述べたとおり本発明の演算増幅回路
では、主増幅器に付随する主スイッチ手段により回路の
増幅状態とリセット状態とを指定しながら、リセット状
態では主増幅器の出力信号を受ける補助増幅器にオフセ
ット補償用信号を作らせて保持手段にその信号値を保持
させておき、増幅状態では補助スイッチ手段により保持
手段を補助増幅器から分離した上で保持信号値を主増幅
器の入力側に帰還させることによって、次の効果を上げ
ることができる。
As described above, in the operational amplifier circuit of the present invention, the main switch means attached to the main amplifier designates the amplification state and the reset state of the circuit, and in the reset state, the auxiliary signal receiving the output signal of the main amplifier is received. The amplifier is made to generate the offset compensation signal, and the holding means holds the signal value. In the amplification state, the holding means value is fed back to the input side of the main amplifier after the holding means is separated from the auxiliary amplifier by the auxiliary switch means. By doing so, the following effects can be achieved.

【0031】(a) 主増幅器のオフセットを補助増幅器と
保持手段により補償して増幅信号に生じるオフセット誤
差を原理上はほぼ完全になくすことができる。実際には
補助増幅器にもオフセットがあってその影響が補償し切
れずに残るが、従来と比べて増幅信号のオフセット誤差
をほぼ主増幅器のゲイン分の1に, 例えば1%程度にま
で減少させることができる。
(A) In principle, the offset error of the main amplifier can be completely eliminated by compensating the offset of the main amplifier with the auxiliary amplifier and the holding means. In reality, the auxiliary amplifier also has an offset and its effect remains uncompensated, but the offset error of the amplified signal is reduced to about 1 / gain of the main amplifier, for example, to about 1% compared to the conventional case. be able to.

【0032】(b) 主増幅器がもつオフセットをその大き
さに応じて補助増幅器と保持手段が自動的に補償して呉
れるので、従来のようにオフセット補償回路を一々調整
するような余分な手間を一切省くことができる。 (c) 演算増幅回路を集積回路に組み込む場合でもオフセ
ット補償付きの本発明回路を単に組み込むだけでよいの
で、従来のようにオフセット補償回路を外付け接続する
際に必要であったいわばむだな実装スペースや余分な手
間を一切なくすことができる。
(B) Since the auxiliary amplifier and the holding means can automatically compensate for the offset of the main amplifier according to the magnitude of the offset, it is unnecessary to adjust the offset compensation circuit one by one as in the conventional case. It can be omitted altogether. (c) Even when an operational amplifier circuit is incorporated in an integrated circuit, it is sufficient to simply incorporate the circuit of the present invention with offset compensation, so it is necessary to mount the offset compensation circuit externally as in the conventional case. You can eliminate any space or extra effort.

【0033】(d) 増幅信号のオフセット誤差は主増幅器
のゲインが高いほど減少するので、本発明を実施するこ
とによりオフセット誤差が小さくしかも高ゲインの演算
増幅回路を容易に構成することができる。 なお、保持手段用に補助増幅器の入出力間にキャパシタ
を接続し,主増幅器と補助増幅器の間に補助スイッチ手
段を挿入する本発明の実施態様は、回路構成を最も簡易
化できる効果を有し、主増幅器の入力側にサンプリング
スイッチ手段を挿入し,かつ主増幅器によりサンプルホ
ールド回路を構成する実施態様は、増幅状態中にサンプ
リングスイッチ手段によりサンプリング状態からホール
ド状態に移した後にサンプルホールドされた増幅信号を
主増幅器から所望のタイミングで随時取り出せる利点を
備える。
(D) Since the offset error of the amplified signal decreases as the gain of the main amplifier increases, an operational amplifier circuit with a small offset error and a high gain can be easily constructed by implementing the present invention. The embodiment of the present invention in which a capacitor is connected between the input and output of the auxiliary amplifier for the holding means and the auxiliary switch means is inserted between the main amplifier and the auxiliary amplifier has the effect that the circuit configuration can be most simplified. In the embodiment in which the sampling switch means is inserted on the input side of the main amplifier and the sample-hold circuit is constituted by the main amplifier, the sample-and-hold amplification is performed after the sampling switch means moves from the sampling state to the holding state during the amplification state. It has the advantage that the signal can be extracted from the main amplifier at any desired timing.

【0034】さらに、主増幅器の入出力から入力端子お
よび出力端子を導出し,入力端子に入力入力抵抗を,入
力端子と出力端子の間に帰還抵抗をそれぞれ外付け接続
する実施態様は、集積回路に組み込まれた演算増幅回路
の増幅率を外部から所望値にとくに正確に設定し,ある
いは必要に応じて随時変更できる効果を有し、さらに主
増幅器の両入力間に抵抗を固定接続する態様は、主スイ
ッチ手段にごく簡単なオンオフ形のものを用いて演算増
幅回路に対して増幅状態とリセット状態を指定できる利
点がある。
Furthermore, an embodiment in which an input terminal and an output terminal are derived from the input and output of the main amplifier, and an input input resistance is externally connected to the input terminal and a feedback resistance is externally connected between the input terminal and the output terminal is an integrated circuit. Has the effect that the amplification factor of the operational amplifier circuit incorporated in the external amplifier can be set to a desired value particularly accurately from the outside, or can be changed at any time as necessary, and a mode in which a resistor is fixedly connected between both inputs of the main amplifier is There is an advantage that the amplification state and the reset state can be designated for the operational amplification circuit by using a very simple on / off type main switch means.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による演算増幅回路の第1実施例を示す
回路図である。
FIG. 1 is a circuit diagram showing a first embodiment of an operational amplifier circuit according to the present invention.

【図2】本発明による演算増幅回路の第2実施例を示す
回路図である。
FIG. 2 is a circuit diagram showing a second embodiment of the operational amplifier circuit according to the present invention.

【図3】本発明による演算増幅回路の第3実施例を示す
回路図である。
FIG. 3 is a circuit diagram showing a third embodiment of the operational amplifier circuit according to the present invention.

【図4】本発明による演算増幅回路の第4実施例を示す
回路図である。
FIG. 4 is a circuit diagram showing a fourth embodiment of the operational amplifier circuit according to the present invention.

【図5】従来の演算増幅回路の例を示す回路図である。FIG. 5 is a circuit diagram showing an example of a conventional operational amplifier circuit.

【符号の説明】[Explanation of symbols]

10 主増幅器 20,21 主スイッチ手段 30 補助増幅器 40 保持手段 41 オフセット補償用信号値を保持するキャパシ
タ 50 補助スイッチ手段 Vi 増幅すべき入力信号 Vo 増幅信号
10 Main amplifier 20, 21 Main switch means 30 Auxiliary amplifier 40 Holding means 41 Capacitor holding the signal value for offset compensation 50 Auxiliary switch means Vi Input signal to be amplified Vo Amplified signal

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】入力信号を演算増幅する主増幅器と、これ
に入力信号を与える増幅状態とその2入力を同電位接続
するリセット状態を指定制御する主スイッチ手段と、主
増幅器から出力信号を受けて主増幅器と逆の方向に演算
増幅する補助増幅器と、補助増幅器の出力信号値を保持
して主増幅器の入力側に帰還する保持手段と、保持手段
への補助増幅器の出力信号の賦与状態と分離状態とを指
定する補助スイッチ手段とを備え、リセット状態で補助
スイッチ手段を賦与状態にし、増幅状態では補助スイッ
チ手段を分離状態にして主増幅器の出力から増幅信号を
取り出すようにしたことを特徴とする演算増幅回路。
1. A main amplifier for operational amplification of an input signal, main switch means for designating and controlling an amplification state for applying the input signal and a reset state for connecting the two inputs to the same potential, and an output signal from the main amplifier. An auxiliary amplifier for performing operational amplification in a direction opposite to that of the main amplifier, holding means for holding the output signal value of the auxiliary amplifier and feeding it back to the input side of the main amplifier, and a state of giving the output signal of the auxiliary amplifier to the holding means. Auxiliary switch means for specifying the separated state is provided, and the auxiliary switch means is set in the applied state in the reset state, and the auxiliary switch means is set in the separated state in the amplification state to extract the amplified signal from the output of the main amplifier. And an operational amplifier circuit.
【請求項2】請求項1に記載の回路において、保持手段
として補助増幅器の一方の入力と出力との間に接続され
たキャパシタを用い、主増幅器の出力と補助増幅器の他
方の入力の間に補助スイッチ手段を挿入するようにした
ことを特徴とする演算増幅回路。
2. The circuit according to claim 1, wherein a capacitor connected between one input and the output of the auxiliary amplifier is used as the holding means, and the capacitor is connected between the output of the main amplifier and the other input of the auxiliary amplifier. An operational amplifier circuit characterized in that an auxiliary switch means is inserted.
【請求項3】請求項1に記載の回路において、主増幅器
の入力信号を受ける入力側にサンプリングスイッチ手段
を挿入するとともに主増幅器によりサンプルホールド回
路を構成し、増幅状態の間にサンプリングスイッチ手段
をオンのサンプリング指定状態からオフのホールド指定
状態に切り換えた後に主増幅器によりサンプルホールド
された増幅信号をその出力から取り出し得るようにした
ことを特徴とする演算増幅回路。
3. The circuit according to claim 1, wherein a sampling switch means is inserted on an input side for receiving an input signal of the main amplifier, and a sample hold circuit is constituted by the main amplifier, and the sampling switch means is provided during an amplification state. An operational amplifier circuit characterized in that an amplified signal sample-held by a main amplifier can be taken out from its output after switching from an on-sampling specified state to an off-hold specified state.
【請求項4】請求項1に記載の回路において、主増幅器
の入力信号を受ける入力から入力端子を,その出力から
出力端子をそれぞれ導出し、入力端子に入力信号を受け
る入力抵抗を,入力端子と出力端子の間に帰還抵抗をそ
れぞれ外付け接続できるようにしたことを特徴とする演
算増幅回路。
4. The circuit according to claim 1, wherein an input terminal for receiving an input signal of the main amplifier is derived from an input terminal, and an output terminal is derived from the output thereof, and an input resistor for receiving the input signal is input to the input terminal. An operational amplifier circuit characterized in that a feedback resistor can be externally connected between the output terminal and the output terminal.
【請求項5】請求項4に記載の回路において、主増幅器
の一対の入力の間に抵抗を接続し、主スイッチ手段によ
って主増幅器に入力信号を与える増幅状態と主増幅器か
ら入力信号を遮断するリセット状態を指定制御するよう
にしたことを特徴とする演算増幅回路。
5. The circuit according to claim 4, wherein a resistor is connected between a pair of inputs of the main amplifier, and the main switch means cuts off the input signal from the amplification state in which the input signal is applied to the main amplifier. An operational amplifier circuit characterized in that a reset state is designated and controlled.
【請求項6】請求項1に記載の回路において、保持手段
が補助増幅器の出力信号を受けるキャパシタとその充電
電圧を受けて同じ電圧値を出力するホールド動作の演算
増幅器回路とから構成されることを特徴とする演算増幅
回路。
6. The circuit according to claim 1, wherein the holding means comprises a capacitor for receiving the output signal of the auxiliary amplifier and an operational amplifier circuit for holding operation for receiving the charging voltage and outputting the same voltage value. An operational amplifier circuit characterized by.
【請求項7】請求項1に記載の回路において、主増幅器
と補助増幅器のそれぞれ入力信号と主増幅器の出力信号
を受ける以外の入力を相互に接続して共通の一定電位を
賦与するようにしたことを特徴とする演算増幅回路。
7. The circuit according to claim 1, wherein the inputs of the main amplifier and the auxiliary amplifier other than the input signals of the main amplifier and the inputs other than the output signal of the main amplifier are connected to each other to provide a common constant potential. An operational amplifier circuit characterized by the above.
JP6153150A 1994-07-05 1994-07-05 Operational amplifier circuit Pending JPH0818353A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6153150A JPH0818353A (en) 1994-07-05 1994-07-05 Operational amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6153150A JPH0818353A (en) 1994-07-05 1994-07-05 Operational amplifier circuit

Publications (1)

Publication Number Publication Date
JPH0818353A true JPH0818353A (en) 1996-01-19

Family

ID=15556118

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6153150A Pending JPH0818353A (en) 1994-07-05 1994-07-05 Operational amplifier circuit

Country Status (1)

Country Link
JP (1) JPH0818353A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004093311A1 (en) * 2003-04-17 2004-10-28 Fujitsu Limited Differential voltage amplifier circuit
US7084700B2 (en) 2003-04-17 2006-08-01 Fujitsu Limited Differential voltage amplifier circuit
US7253679B2 (en) 2005-03-09 2007-08-07 Fujitsu Limited Operational amplifier and method for canceling offset voltage of operational amplifier
US7342443B2 (en) 2006-02-16 2008-03-11 Fujitsu Limited Operational amplifier
JP2008205544A (en) * 2007-02-16 2008-09-04 Toko Inc Offset correction circuit
JP2010004193A (en) * 2008-06-19 2010-01-07 Mitsumi Electric Co Ltd Semiconductor integrated circuit device and offset cancel setting system
US8513938B2 (en) 2011-02-23 2013-08-20 Fujitsu Semiconductor Limited Reference voltage circuit and semiconductor integrated circuit
US8786358B2 (en) 2010-03-19 2014-07-22 Spansion Llc Reference voltage circuit and semiconductor integrated circuit

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004093311A1 (en) * 2003-04-17 2004-10-28 Fujitsu Limited Differential voltage amplifier circuit
US7084700B2 (en) 2003-04-17 2006-08-01 Fujitsu Limited Differential voltage amplifier circuit
US7253679B2 (en) 2005-03-09 2007-08-07 Fujitsu Limited Operational amplifier and method for canceling offset voltage of operational amplifier
US7368983B2 (en) 2005-03-09 2008-05-06 Fujitsu Limited Operational amplifier and method for canceling offset voltage of operational amplifier
US7342443B2 (en) 2006-02-16 2008-03-11 Fujitsu Limited Operational amplifier
JP2008205544A (en) * 2007-02-16 2008-09-04 Toko Inc Offset correction circuit
JP2010004193A (en) * 2008-06-19 2010-01-07 Mitsumi Electric Co Ltd Semiconductor integrated circuit device and offset cancel setting system
US8786358B2 (en) 2010-03-19 2014-07-22 Spansion Llc Reference voltage circuit and semiconductor integrated circuit
US8513938B2 (en) 2011-02-23 2013-08-20 Fujitsu Semiconductor Limited Reference voltage circuit and semiconductor integrated circuit

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