JP2654142B2 - Sample hold circuit - Google Patents

Description

Description: Object of the Invention (Industrial Application Field) The present invention relates to a sample and hold circuit, and more particularly, to a sample and hold circuit suitable for an integrated circuit that uses a difference voltage from a predetermined reference voltage. Circuit.

(Prior Art) Conventionally, in a color television receiver or the like, automatic white level adjustment has been performed. White reference levels are inserted at predetermined timings into the R (red), G (green), and B (blue) color signals obtained by the matrix circuit, respectively, and further amplified by a gain control amplifier. Supplying to cathode. By comparing the levels of the R, G, and B signals supplied to the cathode of the picture tube with the white reference level at the predetermined timing, and adjusting the gain of the gain control amplifier based on the difference voltage between the two, the white level is reduced. Automatic adjustment is performed. As described above, when it is desired to compare the instantaneous values at predetermined timings of the R, G, and B signals supplied to the cathode of the picture tube with the white reference level, a sampling and holding circuit is used.

FIG. 2 is a circuit diagram showing such a conventional sample and hold circuit.

Switch 3 connected between input terminal 1 and output terminal 2
Is turned on in the sampling cycle. That is, the switch 3 is turned on during the sampling period of the input signal Si, and turned off during the hold period. Switch 3 during sampling period
Is turned on, the hold capacitor 4 charges up to the level of the input signal Si introduced to the input terminal 1. During the hold period, the switch 3 is turned off, and the hold capacitor 4 holds the input signal Si. In the automatic white level adjustment described above, the R, G, B signals supplied to the cathode of the picture tube are introduced into the input terminal 1, and the switch 3 is turned on when the white reference level is inserted. The differential amplifier 5 is connected to the output terminal 2
A level difference voltage based on the difference between the R, G, B signals and the white reference level Vs is output. The difference voltage is output to the gain control amplifier, and the gain of the R, G, B signals is adjusted.

The timing of inserting the white reference level into the R, G, B signals is at the start of the vertical scanning period, and the sampling period is one vertical period. For this reason, it is necessary for the hold capacitor 4 to hold the R, G, B signals for one vertical period,
Thus, if the sampling period is relatively long,
It is necessary to use a large-capacity capacitor as the hold capacitor 4.

When such a conventional sample-and-hold circuit is formed into an integrated circuit (IC), the hold capacitor occupies an extremely large area in the IC. For this reason, usually, the hold capacitor 4 is often provided externally. However, even in this case, there is a problem that a board having a large area is required to mount the hold capacitor 4 on the circuit board. Therefore, a circuit that can sample and hold an input signal using a small-capacity hold capacitor that can be implemented as an IC has been proposed.

FIG. 3 is a circuit diagram showing such a conventional sample and hold circuit, which is disclosed in Japanese Patent Application Laid-Open No. Sho 60-186186. 4 is a timing chart for explaining the operation of FIG. 3. FIG. 4 (a) shows the terminal voltage of the capacitor C1, and FIG. 4 (b) shows the terminal voltage of the capacitor C2. 4 (C) shows the difference voltage from the differential amplifier 8. FIG.

The switches S1 and S2 are controlled by a timing pulse P introduced to the input terminal 7, and are turned on during a sampling period and turned off during a hold period. When the switches S1 and S2 are turned on during the sampling period, the hold capacitor C1 charges up to the level of the input signal Si introduced to the input terminal 6, while the hold capacitor C2 is connected to the reference power supply 9
To the reference voltage Vs. Switch during hold period
S1 and S2 are turned off, and the hold capacitor C1
i holds the input signal voltage Vi, and the hold capacitor C2 holds the reference voltage Vs. The differential amplifier 8 receives the input signal voltage Vi and the reference voltage Vs and outputs a difference voltage between them.

It is assumed that the capacitances of the hold capacitors C1 and C2 are relatively small. Then, as shown in FIGS. 4 (a) and 4 (b), the terminal voltages of the hold capacitors C1 and C2 decrease due to leakage current during the hold period, and include ripples. Here, switches S1 and S2, capacitors C1 and C2
When the balance of the differential amplifier 8 and the like are uniform,
The ripple cycle of the terminal voltages of the capacitors C1 and C2 matches the sampling cycle, and the slope of the ripple also matches.
Therefore, the output of the differential amplifier 8 is constant irrespective of the ripple of the terminal voltage of the capacitors C1 and C2, as shown in FIG. 4 (c). Thus, in the circuit of FIG. 3, the difference voltage between the input signal Si and the reference voltage Vs can be kept constant during the hold period even when the capacitance of the hold capacitors C1 and C2 is small.

Incidentally, the circuit in FIG. 3 is based on the premise that the input offset current of the differential amplifier 8 is zero. However, in the integrated differential amplifier 8, the bias currents at the two input terminals are slightly different. Therefore, the hold capacitors C1 and C during the hold period
2, the discharge amount is different, and the ripple inclination is different. Normally, the input bias current differs between the two terminals by about 5 to 10% and the hold capacitors C1, C
When the capacity of 2 is small, the difference between the discharge amounts of the hold capacitors C1 and C2 increases. For this reason, the capacity of the hold capacitors C1 and C2 is limited to about 1/10 compared to the capacity value of the hold capacitor 4 in FIG. Therefore, when the sampling period is relatively long as in the automatic white level adjustment described above, if the hold capacitor is formed into an IC, the area occupancy on the IC chip becomes extremely large and the manufacturing cost increases. For this reason, normally, the hold capacitors C1 and C2 are externally mounted, and there is a problem that a large board area is required for mounting the two hold capacitors C1 and C2.

Further, as shown in FIGS. 4 (a) and 4 (b), the terminal voltages of the hold capacitors C1 and C2 greatly fluctuate, so that the dynamic range is reduced. There is also a problem that it is difficult to use a circuit that has no room for distribution.

(Problems to be Solved by the Invention) As described above, in the conventional sample and hold circuit described above, it is difficult to integrate a hold capacitor into an integrated circuit, and two hold capacitors are mounted on a circuit board as external components. Therefore, there is a problem that the substrate area becomes extremely large.

The present invention has been made in view of such a problem, and provides a sample-and-hold circuit that can reduce the size of a circuit by reducing the number of external capacitors to one without reducing the power supply utilization rate. With the goal.

According to the present invention, an input signal voltage is introduced to one end and the other end is connected to a first output terminal, and is turned on during a sampling period and turned off during a hold period. And a second switch, in which a reference voltage is introduced to one end and the other end is connected to the second output terminal and turned on during a sampling period and turned off during a hold period.
And a hold capacitor connected between the other ends of the first and second switches and charged to a difference voltage between the input signal voltage and the reference voltage during a sampling period and holding the difference voltage during a hold period, A midpoint voltage generating means for generating a midpoint voltage between the input signal voltage and the reference voltage, and adding the midpoint voltage to a voltage approximately half of the difference voltage and supplying it to the second output terminal And a voltage synthesizing circuit.

(Operation) In the present invention, during the sampling period, the terminal voltage of the hold capacitor rises to the difference voltage between the input signal voltage and the reference voltage. The hold capacitor holds this difference voltage during the hold period, and the potential difference between the first and second output terminals becomes constant. The voltage synthesizing circuit adds the midpoint voltage to a voltage approximately half of the difference voltage held by the hold capacitor and supplies the resulting voltage to the second output terminal. Thus, the voltage appearing at the second output terminal during the hold period becomes the same as the voltage appearing at the second output terminal during the sampling period. Therefore, even during the hold period, the same voltage as the voltage output during the sampling period appears at the first and second output terminals.

Hereinafter, the present invention will be described in detail with reference to the drawings. First
FIG. 1 is a circuit diagram showing one embodiment of a sample hold circuit according to the present invention.

An input signal Si is introduced to the input terminal 11, and a reference voltage Vs is applied to the input terminal 12. The input signal Si and the reference voltage Vs are supplied to the terminals a of the switches S3 and S4 of the switch circuit 14, respectively, and are also supplied to the midpoint voltage generation circuit 13. The midpoint voltage generating circuit 13 is a midpoint voltage between the voltage of the input signal Si and the reference voltage Vs.
Vim is generated and supplied as a reference potential to a non-inverting terminal of a differential amplifier 24 described later via a resistor 21. It is assumed that the voltage of the input signal Si (input signal voltage) during the sampling period is Vi.

Switches S3 and S4 are turned on during the sampling period,
It is off during the hold period. Terminal b of switches S3 and S4
Are connected to the input terminals of buffer amplifiers 15 and 16, respectively.
Hold capacitor C between terminals b of switches S3 and S4
3 is connected. The buffer amplifiers 15 and 16 are amplifiers having a gain of 1. The output terminals of the buffer amplifiers 15 and 16 are connected to the output terminals 17 and 18, respectively, and are connected to the inverting terminal and the non-inverting terminal of the differential amplifier 24 via the resistors 19 and 20, respectively. Connect each one. The output terminal of the differential amplifier 24 is connected to the inverting input terminal via the resistor 22 and
Is connected to the input terminal of the buffer amplifier 16. In addition,
The resistance value of the resistors 19 and 20 is 2R, and the resistance value of the resistors 21 and 22 is R
It is. The resistors 19 to 22 and the differential amplifier 24 constitute a voltage synthesis circuit 25. The voltage synthesizing circuit 25 outputs the output terminal 17 to the midpoint voltage Vim obtained by the midpoint voltage generation circuit 13.
A voltage Vcm obtained by adding a half of the potential difference of the signal appearing at 18 in the opposite phase is output.

Next, the operation of the thus configured embodiment circuit will be described.

During the sampling period, the switches S3 and S4 of the switch circuit 14 are both turned on, and the hold capacitor C
The terminal voltage Vc of 3 rises to Vi−Vs. The input signal voltage Vi and the reference voltage Vs appear at the output terminals 17 and 18, respectively.

During the hold period, the switch S of the switch circuit 14
3, S4 is turned off, the potential difference between the input terminals of the buffer amplifiers 15, 16 is fixed to the terminal voltage Vc of the capacitor C3, and the output terminal
The potential difference of 17, 18 is also fixed at Vc.

The resistance value of the resistors 19 and 20 is 2R, the resistance value of the resistors 21 and 22 is R, and the midpoint voltage Vim is given to the voltage synthesizing circuit 25 from the midpoint voltage generation circuit 13 as a reference potential. Therefore, at the output terminal of the voltage synthesizing circuit 25, the voltage of the midpoint voltage V
A voltage obtained by adding im in the opposite phase appears. That is, the voltage synthesis circuit
The output terminal 25 supplies the voltage Vcm shown in the following equation (1) to the input terminal of the buffer amplifier 16.

Vc = Vi−Vs, Therefore, the voltage Vcm shown in the following equation (2) is supplied to the input terminal of the buffer amplifier 16.

That is, a voltage having the same level as the reference voltage Vs introduced to the switch S4 is applied to the input terminal of the buffer amplifier 16 immediately before the switch 14 is turned off and the hold period is started, during the hold period. In addition, buffer amplifier 15
A voltage obtained by adding the terminal voltage Vc of the hold capacitor C3 to the input terminal voltage of the buffer amplifier 16, that is, the same voltage as the input signal voltage Vi introduced to the switch S3 immediately before the start of the hold period is applied to the input terminal of the buffer amplifier 16. Will do. Therefore, the same voltages Vi and Vs as those in the sampling period are output from the output terminals 17 and 18 even in the hold period.

As described above, in the present embodiment, the input signal can be sampled and held by providing one hold capacitor C3 for holding the difference between the output voltages, and the number of the hold capacitors is one. The substrate area can be reduced.

In practice, the output voltage Vcm of the voltage synthesizing circuit 25 is not exactly equal to the voltage Vs introduced to the switch S4 immediately before the hold period due to the offset of the switch circuit 14, the synthesis error of the voltage synthesizing circuit 25, and the like. It does not match. However, even in this case, there is no change in the potential difference Vc between the output terminals 17 and 18, and there is no problem when utilizing the difference between the voltages appearing at the output terminals 17 and 18. Also, such an output voltage Vcm and a reference voltage V
The error from s is an extremely small value compared to the power supply voltage, and the error does not significantly reduce the dynamic range. When a differential amplifier is connected to the output terminals 17 and 18, even if the input bias current between the two input terminals of the differential amplifier is different, the hold capacitor C3 is connected to the input signal voltage Vi and the reference voltage. Since the difference voltage from the voltage Vs is held, the capacitance of the hold capacitor C3 can be smaller than that of the conventional circuit shown in FIG.

[Effects of the Invention] As described above, according to the present invention, it is possible to sample and hold an input signal by providing one hold capacitor.
The mounting substrate area can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a sample-hold circuit according to the present invention, FIGS. 2 and 3 are circuit diagrams showing a conventional sample-hold circuit, and FIG. 4 explains the operation of FIG. FIG. 11, 12 input terminals, 13 midpoint voltage generating circuit, 14 switch circuits, 17, 18 output terminals, 19 to 23 resistors, 24 differential amplifiers, 25 voltage synthesis circuit.

Claims (1)

(57) [Claims] An input signal voltage is introduced to one end, a first switch is connected to a first output terminal at the other end, is turned on during a sampling period and is turned off during a hold period, and a reference voltage is introduced to one end. A second switch having the other end connected to the second output terminal and turned on during a sampling period and turned off during a hold period; and a second switch connected between the other ends of the first and second switches, the input signal being connected during the sampling period. A hold capacitor that charges to a difference voltage between the voltage and the reference voltage and holds the difference voltage during a hold period; a midpoint voltage generation unit that generates a midpoint voltage between the input signal voltage and the reference voltage; A sample-and-hold circuit, comprising: a voltage combining circuit that adds the midpoint voltage to approximately half of the voltage and supplies the voltage to the second output terminal.