JPH02146194A - Sample-and-hold circuit - Google Patents

Abstract

PURPOSE:To sample and hold an input signal and to minimize a substrate area by providing one holding capacitor to hold the difference in output voltage. CONSTITUTION:In a sampling period, both of switches S3 and S4 are turned on, and terminal voltage Vc of a holding capacitor C3 rises up to Vi-Vs. The input signal voltage Vi and the reference voltage Vs respectively appear at output terminals 17 and 18. When a holding period starts, the switches S3 and S4 are turned off, the potential difference between the input terminals of buffer amplifiers 15 and 16 is fixed to the voltage Vc, and the potential difference between the terminals 17 and 18 is also fixed to Vc. A voltage synthesizing circuit 25 to input midpoint voltage Vim from a midpoint voltage generating circuit 13 supplies voltage Vim-Vc/2 to the input terminal of the amplifier 16 and impresses voltage obtained by adding the voltage Vc to the input terminal voltage of the amplifier 16 to the input terminal of the amplifier 15. Consequently, the same voltage Vi and Vs as that in the sampling period are respectively outputted from the terminals 17 and 18. Further, since the number of the capacitor is 1, the substrate area can be minimized.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a sample and hold circuit, and particularly to a sample and hold circuit that is integrated and is suitable for a circuit that utilizes a voltage difference from a predetermined reference voltage. Regarding circuits.

(Prior Art) Conventionally, automatic white level adjustment has been performed in color television receivers and the like. For the R (red), G (green), and B (blue) color signals obtained by the matrix circuit,
A white reference level is inserted at a predetermined timing, further amplified by a gain control amplifier, and then supplied to the cathode of the picture tube. The white level is determined by comparing the levels of the R, G, and B signals supplied to the cathode of the picture tube with the white reference level at the predetermined timing described in 11a, and adjusting the gain of the gain control amplifier based on the difference voltage between the two. automatic adjustment is performed.

In this way, R, G, B supplied to the cathode of the picture tube
A sample and hold circuit is used when an instantaneous value of a signal at a predetermined timing is to be compared with a white reference level.

FIG. 2 is a circuit diagram showing such a conventional sample and hold circuit.

A switch 3 connected between the input terminal 1 and the output terminal 2 is turned on at the sampling period. That is, the switch 3 is turned on during the sampling period of the input signal Si, and turned off during the hold period. Switch 3 during sampling period
When turned on, the hold capacitor 4 charges up to the level of the input signal Si introduced into the input terminal 1. During the hold period, switch 3 is turned off and hold capacitor 4 holds input signal 3i. In the automatic white level adjustment described above, the R, G, and B signals supplied to the cathode of the picture tube are introduced into the input terminal 1, and the switch 3 is turned on when the white reference level is inserted. The differential amplifier 5 outputs a differential voltage having a level based on the difference between the R, G, and B signals of the output terminal 2 and the white reference level Vs. This differential voltage is output to a gain control amplifier to adjust the gains of the R, G, and B signals.

By the way, the white standard level is 11. The timing of insertion into the G and B signals is the start of the vertical scanning period, and the sampling period is one vertical period. Therefore, it is necessary for the hold capacitor 4 to hold the R, G, and B signals for one vertical cycle period.In this way, when one non-pulling cycle is relatively long, a Daikan M capacitor is used as the hold capacitor 4. There is a need to.

This kind of integrated circuit (
If the IC becomes large, the hold capacitor will occupy an extremely large area within the IC. For this reason, the hold capacitor 4 is usually provided externally. However, even in this case, there is a problem in that a large area board is required to mount the hold capacitor 4 on the circuit board. Therefore, a circuit that can sample and hold an input signal using a small-capacity hold capacitor that can be integrated into an IC has been proposed.

FIG. 3 is a circuit diagram showing such a conventional sample and hold circuit, which is disclosed in Japanese Patent Application Laid-Open No. 186186/1986. Moreover, FIG. 4 is a timing chart for explaining the operation of FIG. 3, and FIG. 4(a) shows the terminal voltage of capacitor C1, and FIG. 4(b) shows the terminal voltage of capacitor C2. , FIG. 4(C) shows the differential voltage from the differential amplifier 8.

The switches 81 and S2 are controlled by a timing pulse P introduced to the input terminal 7, and are turned on during the sampling period and turned off during the hold period. During the sampling period, switch Sl.

When S2 is turned on, the hold capacitor c1 charges up to the level of the input signal St introduced into the input terminal 6, while the hold capacitor C2 charges the reference voltage Vs of the reference power supply 9.
Charge up to. During the hold period, the switch 31.82 is turned off, the hold capacitor C1 holds the input signal voltage Vi of the input signal Si, and the hold capacitor C2 holds the reference voltage Vs. The differential amplifier 8 inputs these input signal voltage Vi and reference voltage Vs, and outputs the difference voltage between the two.

It is assumed that each day of the hold capacitors CI and C2 is relatively small. Then, Fig. 4(a).

As shown in (b), the terminal voltage of the hold capacitor C1°C2 decreases due to the leakage current during the hold period and includes ripples.

Here, switches 31 and 82 and capacitor CI.

When C2, the differential amplifier 8, etc. are balanced, the ripple period of the terminal voltages of the capacitors CI and C2 matches the sampling period, and the slope of the ripple also matches. Therefore, the output of the differential amplifier 8 is as shown in FIG.
As shown in C), it remains constant regardless of the ripples in the terminal voltages of capacitors CI and C2. In this way, in the circuit of FIG. 3, even if the capacitance 4 of the hold capacitors CI and C2 is small, the differential voltage between the input signal Si and the reference voltage VS can be kept constant during the hold period.

Incidentally, the circuit shown in FIG. 3 is based on the premise that the input offset current of the differential amplifier 8 is O. However, in the differential amplifier 8 that is integrated circuit, the bias currents at the two input terminals are slightly different.

For this reason, hold capacitors C1 and C during the hold period
Since the radiation N4 of the two is different, the slope of the ripple becomes different. Typically, the input bias current differs by about 5-10% between the two terminals, and the hold capacitor C
If the capacitances of I and C2 are small, the difference in the discharge fields of the hold capacitors CI and C2 will become large. For this reason, the capacitance of hold capacitors CI and C2 is approximately 1
/10 is the limit.

Therefore, when the sampling period is relatively long as in the above-mentioned automatic white level adjustment, if the hold capacitor is set to tC, the area occupation rate on the IC chip becomes extremely large and the manufacturing cost becomes high. For this reason, a hold capacitor CI is usually used.

Since C2 has to be externally attached, there is a problem in that a large board area is required to mount the two hold capacitors CI and C2.

Furthermore, as shown in Figures 4(a) and (b), the terminal voltages of the hold capacitors CI and C2 fluctuate greatly, reducing the dynamic range. There was also the problem that it was difficult to use vA in circuits that did not have enough allocation.

(Problems to be Solved by the Invention) As described above, in the conventional sample-and-hold circuit described above, it is difficult to integrate the hold capacitor into an integrated circuit, and the two hold capacitors cannot be attached externally to the circuit board as components. Since it needs to be mounted, there is a problem in that the board area becomes extremely large.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a sample and hold circuit that can reduce the size of the circuit by reducing the number of external capacitors to one without reducing power utilization.

[Structure of the Invention] (Means for Solving the Problems) The present invention introduces an input signal voltage to one end, and the other end
A first switch is connected to the output terminal of the switch and is turned on during the sampling period and turned off during the hold period, and a reference voltage is introduced into one end of the switch, and the other end is connected to the second output terminal, which is turned on during the sampling period and turned off during the hold period. A second switch that is turned off is connected between the other ends of the first and second switches, and is charged to the difference voltage between the input signal voltage and the reference voltage during the sampling period, and this difference voltage is used during the hold period. a hold capacitor for holding; a midpoint voltage generating means for generating a midpoint voltage between the input signal voltage and the reference voltage;
Add the midpoint voltage to approximately 1/2 of the voltage difference.
C, the voltage combining circuit that supplies the voltage to the second output terminal is omitted.

(Function) In the present invention, during the sampling period, the terminal voltage of the hold capacitor increases to the voltage difference between the input signal voltage and the reference voltage. The hold capacitor holds this differential voltage during the hold period, and the potential difference between the first and second output terminals becomes constant. The voltage synthesis circuit adds a midpoint voltage to approximately 1/2 of the differential voltage held in the hold capacitor and supplies the added voltage to the second output terminal. Thereby, the voltage appearing at the second output terminal during the hold period is the same as the voltage appearing at the second output terminal during the sampling period. Therefore, even during the hold period, the same voltage appears at the first and second output terminals as the voltage output during the sampling period.

(Example) Hereinafter, the present invention will be described in detail based on the drawings. FIG. 1 is a circuit diagram showing an embodiment of a sample and hold circuit according to the present invention.

Input signal S1 is introduced into input terminal 11, and input signal S1 is introduced into input terminal 12.
A reference voltage Vs is applied to. The input signal 3i and the reference voltage VS are supplied to the terminals a of the switches 83 and 84 of the switch circuit 14, respectively, and are also supplied to the midpoint voltage generation circuit 13. The midpoint voltage generation circuit 13 generates a midpoint voltage Via+ between the voltage of the input signal 3i and the reference voltage Vs, and
llI based on the non-inverting end of the differential amplifier 24 to be described later via
! Supplied as electric potential. Note that it is assumed that the voltage of the input signal Si (input signal voltage) during the sampling period is Vi.

Switches 33, 34 are on during the sampling period and off during the bold period. The terminals of switches S3 and 84 are connected to the input terminals of buffer amplifiers 15 and 16, respectively, and a hold capacitor C3 is connected between the terminals of switches 83 and S4. Buffer amplifiers 15 and 16 are amplifiers with a gain of 1, and their output terminals are connected to output terminals 17 and 18, respectively, and resistors 19.
20 are connected to the inverting end and the non-inverting end of the differential amplifier 24, respectively.

The output terminal of the differential amplifier 24 is connected to the inverting input terminal via a resistor 22, and is also connected to the buffer amplifier 1 via a resistor 23.
Connect to the input terminal of 6. Note that the resistance value of the resistor 19.20 is 2R, and the resistance value of the resistor 21.22 is R. These resistors 19 to 22 and differential amplification? The voltage synthesis circuit 25 is configured by S24. The voltage synthesis circuit 25 converts the midpoint voltage ■1IIl obtained by the midpoint voltage generation circuit 13 into
A voltage Vcm obtained by adding 1/2 voltage of the potential difference between the signals appearing at the output terminals 17 and 18 in opposite phase is outputted τ
There is.

Next, the operation of the embodiment circuit configured as described above will be explained.

During the sampling period, both switches 83 and 84 of the switch circuit 14 are turned on, and the terminal voltage VC of the hold capacitor C3 rises to 1-VS. The input signal voltage Vi and the reference voltage VS appear at the output terminals 17 and 18, respectively.

During the hold period, the switch 8 of the switch circuit 14
3.84 is turned off, the potential difference between the input terminals of the buffer amplifiers 15 and 16 is fixed to the terminal voltage VC of the capacitor C3, and the potential difference between the output terminals 17 and 18 is also fixed to VC.

The resistance value of resistor 19.20 is 2R, and the resistance value of resistor 21.22
Since the resistance value of is R and the voltage synthesis circuit 25 is given the midpoint voltage Vil from the midpoint voltage generation circuit 13 as a reference potential, the output terminal of the voltage synthesis circuit 25 is
A voltage that is obtained by adding the midpoint voltage vim of the midpoint voltage generation circuit 13 in opposite phase to the voltage that is 1/2 of the potential difference Vc between the output terminals 17 and 18 appears. That is, the output terminal of the voltage synthesis circuit 25 supplies the voltage Vcm shown in the following equation (1) to the input terminal of the buffer amplifier 16.

Since VC=Vl-Vs and Vim=, the voltage VCI11 shown in the following equation (2) is supplied to the input terminal of the buffer amplifier 16.

=Vs...
(2) That is, a voltage at the same level as the 33 i 1 voltage VS applied to the switch S4 immediately before the switch 14 is turned off and the hold period begins is applied to the input terminal of the buffer amplifier 16 during the hold period. I will do it. Also, at the input terminal of buffer amplifier 150 (buffer amplifier 1
6 plus the terminal voltage Vc of the hold capacitor C3, that is, the same voltage as the input signal voltage v1 introduced into the switch S3 immediately before the start of the hold period. Therefore, the same voltages i and VS as in the sampling period are output from the output terminals 17 and 18 during the hold period, respectively.

In this way, in this embodiment, by providing one hold capacitor C3 that holds the difference in output voltage, it is possible to sample and hold the input signal, and since the number of hold capacitors is one, The board area can be reduced.

In reality, due to the offset of the switch circuit 14 and the synthesis N+ >C of the voltage synthesis circuit 25, the output voltage Vcm of the voltage synthesis circuit 25 is not exactly the voltage VS introduced into the switch S4 immediately before the hold period. does not match. However, even in this case, there is no change in the potential difference VC between the output terminals 17 and 18 (there is no problem when using the difference in voltage appearing at the output terminals 17 and 18. The error with the voltage VS is an extremely small value compared to the power supply voltage, and the dynamic range will not be significantly reduced by this error.

Furthermore, when a differential amplifier is connected to the output terminals 17 and 18, even if the input bias currents between the two input terminals of this differential amplifier are different, the hold capacitor C3 is connected to the input signal voltage Vi and the reference Since the voltage difference from the voltage VS is held by -4, the capacitance of the hold capacitor C3 can be made smaller than that of the conventional circuit shown in FIG.

[Effects of the Invention] As explained above, according to the present invention, by providing one hold capacitor, it is possible to sample and hold the input signal, and when it is integrated into an integrated circuit, the mounting board area can be reduced. be able to.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the non-pull hold circuit according to the present invention, FIGS. 2 and 3 are circuit diagrams showing conventional sample and hold circuits, and FIG. 4 shows the operation of FIG. 3. This is a timing chart for explanation. 11, 12... Input terminal, 13... Midpoint voltage generation circuit, 14... Switch circuit, 17.18... Output terminal, 19 to 23... Resistor, 24... Differential amplifier ,
25...Voltage synthesis circuit. 14 switch circuit Figure 1 Figure 3 Figure 2 (C) Difference! Detour - 1111 Figure 4

Claims (1)

[Claims] A first switch that introduces an input signal voltage into one end, connects the other end to a first output terminal, turns on during a sampling period and turns off during a hold period, and introduces a reference voltage into one end. a second switch whose other end is connected to the second output terminal and which is turned on during the sampling period and turned off during the hold period; and a second switch which is connected between the other ends of the first and second switches and which is connected to the input terminal during the sampling period. a hold capacitor that charges up to a voltage difference between a signal voltage and a reference voltage and holds this voltage difference during a hold period; a midpoint voltage generating means that generates a midpoint voltage between the input signal voltage and the reference voltage; and a voltage difference between the input signal voltage and the reference voltage. and a voltage synthesis circuit that adds the midpoint voltage to approximately 1/2 of the voltage and supplies the resultant to the second output terminal.