JPS60186186A - Sample holding circuit - Google Patents

Abstract

PURPOSE:To hold a sample value by using a small capacity capacitor formed in an IC circuit by applying two sample holding values to a differential circuit. CONSTITUTION:Switches 71 and 72 which are turned on and off with smapling pulses P sample an input signal Si and a constant reference voltage Vs obtained from a reference power source 74, and their sampling values are held in capacitors C1 and C2. Small-capacity capacitors are used as C1 and C2, and consequently the held voltages are signals including a ripple because of leak currents of the capacitors C1 and C2. Those signals are applied to a differential amplifier 75 in a trailing stage, but the periods and inclinations of ripples of the held signals are equal, so the output signal So of the amplifier 75 is constant.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a sample and hold circuit applicable to IC circuits and the like.

BACKGROUND ART AND PROBLEMS THEREOF FIG. 1 shows a circuit system of a conventional television receiver including an automatic white balance adjustment circuit to which the present invention can be applied.

In the figure, a television signal selected by a tuner 2 from a received signal received by an antenna 1 is added to an intermediate frequency circuit 6 and converted into an intermediate frequency signal of a predetermined frequency, and this intermediate frequency signal is used for movie movies. It is added to the safety detection circuit 4 for video detection. The video No. 49 sv obtained from the video detection circuit 4 is added to the synchronization separation circuit 5, and
The signal is added to the 10 minute 14t11 circuit 6 and separated into a Y signal (luminance signal) and a C signal (chroma signal). The Y signal is applied to a gain control amplifier 7, and the C signal is applied to a gain control amplifier 7.
It is added to the i+1 amplifier B and is also supplied to the burst gate circuit 9I. The above 5i'u gain control increase "1] device 7,
B is used as a picture adjustment circuit, and the control obtained from the variable resistor 10! The gain is controlled by the 11-tonne pressure (ζxg), and the picture adjustment of the Y signal and the 0-signal is performed. The picture-adjusted Y signal is level-clamped by a clamp circuit 11 and then applied to a matrix circuit 12 after 7c. In addition, the picture adjustment awn nine C signal is inputted to the color adjustment circuit 161, and the color v!
After performing the 4 adjustment, the signal is sent to the color demodulation circuit 15. Further, the color burst signal extracted from No. 904g by the burst gate circuit ψ drives the subcarrier oscillator 16, and the subcarrier obtained from this oscillator 16 is sent to the phase shift circuit 17, where the control voltage 1 is obtained from the variable resistor 18.
After the phase adjustment is completed, the color demodulation circuit 151 is added. R- obtained from this color demodulation circuit 15
Y.

43-Y color difference signals are sent to matrix circuits 1j2f.

On the other hand, horizontal and vertical synchronization signals obtained from the synchronization separation circuit 5 are applied to a horizontal deflection circuit 19 and a vertical deflection circuit 20. These horizontal and vertical deflection circuits 19, 2'0 generate a horizontal blanking pulse HP and a vertical blanking pulse VPi based on the synchronization signal, and in addition to the timing pulse generation circuit 21 and the matrix circuit 121, the horizontal deflection No. 48 HF and vertical deflection signal VF are generated to horizontal and vertical deflection coils (not shown) 1 of the cathode ray tube 22.
Add this. The timing generation circuit 21 generates the above pulse 11P.
The burst gate circuit generates a burst extraction pulse based on 1VP? In addition, a white timing pulse 1w and a black timing pulse PB, which will be described later, are generated and output.

The above Mal-1) Tux circuit 12 is configured to perform a
(, G, B color signals are demodulated. These R, G,
B signal is the reference level insertion circuit 23R123G, 25. B
At this time, a white reference level V8W and a black reference level VSB, which will be described later, are inserted for a predetermined period. Next, gain control is performed on the gain control amplifiers 24R, 24G, and 24B, and the white level is adjusted using control signals SWR% SWG, SWB, which will be described later. , 25, , 25, +, a control signal SBR% 880% SBB f to be described later is level shifted to perform black level adjustment. After the above-mentioned white level adjustment and black level adjustment are performed, the white balance-adjusted R, G, and B signals are then amplified by video intensifiers 26R, 26G, and 26B, and sent to the cathode theater 22.
The cathodes 27R127o and 27Bl are added.

The current flowing through the cathode 27R is detected as a tail current of the cathode] (2
) The detection signal is applied to sample and hold circuits 29R and 30. The current flowing through the cathode 27G is detected by the cathode current detection circuit 28G,
This detection signal is transmitted to the sample hold circuit 29G/3 [JG
In addition to. The current flowing through the cathode 27B is detected by a cathode current detection circuit 28B, and this detection signal is applied to sample and hold circuits 29B and 30B.

The above sample hold circuit 29 It, 29 os2
9, the black timing pulse PB generated from the timing pulse generation circuit 21 is added as a sampling pulse, and the sample hold circuits 6oR, 30G,
Is 30B from the timing pulse generation circuit 21 mentioned above? 4
A white timing pulse Pwf is added as a suffixing pulse.

The above-mentioned pulse PWs "B is obtained at the timing shown in FIG. 2 with respect to the original video signal Sv. That is, the video signal Sv
If the vertical blanking period (V', denoted by BLK) is, for example, 21 H periods long, then the first H period (denoted by IH) 1 from the end of this vertical blanking period
This pulse Pw is obtained, and the pulse PB (indicated by I) in period (2) of the second scan is obtained. In addition, these 1H and 2H
The period is the video period, but the first screen on the receiver is the video t5.
I can't do it.

The pulse PWb"B obtained at the above-mentioned timing is used as a single sampling pulse as described above, and the pulse Pw drives the white reference level generation circuit 33w, and the pulse PB drives the black reference level. The generating circuit 33w is driven.

As a result, the white reference level generating circuit 33w outputs the white reference level VSW, which is represented by a level of 50 to 6[JIRE, for example, as shown in FIG.

This reference level VSW is the reference level insertion circuit 23R.
126o, 26B1 here! ll, G, and 84g are inserted into the IH period, respectively. At the same time, the black reference level generating circuit 66B outputs a black reference level VSB expressed at a level of, for example, 5.degree. E as shown in FIG. This reference level VSII is the above-mentioned Yuzu quasi-level insertion circuit 231% 23G, 26B1! ll 几, U,
They are inserted into each of the 2H periods of the B signal.

If any of the cathodes 27n, 27a, 27n I flow or 7i flow changes and the white balance collapses, the reference level V SW s ■ SB inserted between the 1H period and 2HM described above will change. The change in Vsw is detected by the sample and hold circuits 5U, 30G, and 30B, and the change in 'l'sH is detected by the sample and hold circuit 29.
Detected by R, 29G, 29B. sample hold circuit 30R3UG, 30. The detected value is added to the differential amplifiers 32R, 32(-, 62B1), respectively, and the difference with the reference voltage vw corresponding to the 50 to 60 IRE is determined. No. S
The gain fljll as WR% SWG% SWB
In addition to the OMI amplifier, 24R124G, 24B-), gain control of the F, OMI, CI, and B signals is added to perform white level adjustment. tyc sample hold circuit 29R129G, 29. The detected value is the differential amplifier 3
1R131G and 31BF were added to the above 5
The difference between the direct pressure vB and the direct pressure vB equivalent to 1RE can be seen. This difference signal controls (f14NM No. S'llR55IIGs SB
n and the level shift circuits 25R, 25G, 2
By being sold by 5Bi, R,G.

A 91C level shift of the B signal is performed to adjust the black level.

If the above f is completed, the R channel, G channel, and B channel f will each be composed of 5 controlling lube forces.The above black level adjustment will be performed by these side diagonal loops.)-27 ,,27G.

In addition to matching the cut-off points of the voltage-current characteristics of each cathode 27B (the white level adjustment described above is in line 4-), the slopes of the voltage-current characteristics of each of the cathodes 27B and 27B are made to be the same. I can do it. As a result, the cathode electrode 27n
, 27G, 27B + each flowing cathode -'
i! , 3° current ratio can be maintained at a predetermined level, and the white balance of the screen can be stabilized.

In the above-mentioned automatic white balance adjustment circuit 1, there are six sample hold circuits 29 R, 290, 296.
, 30B, 30G, and 30B are used, and they have a pulse PW applied every 1■ (■: field).
%PB is used as a sampling pulse. In such a sample hold circuit having a relatively long sampling period, a capacitor of large capacity is used to hold the sample value. Since most of the automatic white balance i and Pj adjustment circuits are configured as IC circuits, the capacitors must be connected externally to the IC circuit. In the case of FIG. 1, six capacitors are connected, so the number of terminal pins of the IC circuit increases, and the number of external TFC components increases, causing an increase in cost.

OBJECTS OF THE INVENTION The present invention uses a small capacitance capacitor inside an IC circuit to hold sample values.

The present invention provides a sample and hold circuit that can perform the following steps.

Summary of the Invention The present invention samples and holds an input signal using a sampling pulse, and also samples and holds a constant reference level using the same sampling pulse.

However, two sample and hold values are added to the differential circuit. This makes it possible to realize a sample and hold circuit using a small capacitor.

7M examples are added, and this input signal is turned on and off by the sampling pulse P applied to the terminal 71 of the switch 72.
It will be expanded by. This sampled value is held in capacitor C1.

At the same time, the sampling pulse Pl turns on.
When the switch 76 is turned off, a reference voltage Vs obtained from the reference power source 74 is sampled, and the sampled value is applied to the capacitor 021.

Capacitors 01 and 02 are of small capacity, so the voltage held in these capacitors C1 and C2 is 1% (see Figure 4 for leakage and current in 2). As shown, the ripples are removed as signals.These signals are applied to the differential amplifier 75 at the next stage.

If the switches 72 and 73, capacitors C1 and C2, and the differential amplifier 75, etc. are all aligned, the capacitors C1 and C21 will be held, and the period of the ripple in the pressure will be constant at the sampling period. Therefore, the slope of the Matari Tsuburu also matches. Therefore, this number So becomes constant as shown in FIG. That is, the differential amplifier 75 exhibits the ability to remove the two common-mode input signals, and the output signal So f ? I can do V. The level of this output signal SO is determined by the gain E of the differential amplifier 75, and has a magnitude of 7C according to the Zangle value of the input signal 81. Therefore, the circuit shown in FIG. 6 becomes a simple sample-and-hold circuit for the input signal St by setting the differential amplifier 75 to 1. Furthermore, since the gain of the differential amplifier 75 can be freely changed, matching to the subsequent circuit can be performed appropriately.

FIG. 5 shows an example of the specific circuit configuration of FIG. 6, and parts 1 corresponding to those in FIG. 6 are given the same reference numerals.

In FIG. 5, transistors Qs1s and Qsy are emitter follower buffers, and transistors Q32 and C
55, C38, and C39 constitute the switches 72 and 76, which are turned on and off by the sampling pulse P1 applied to the terminal 71. Transistor Qsa
Notes Qgs・C36 and C40・Qa+・C42 are buffers consisting of a 6-stage connection circuit, and the capacitors C1, 0□ are provided between this buffer and the switches 72 and 73. . Transistor Q43
・Q44%Q45・C46, C47, diode “1)
++.D12.Di3 constitute the differential amplifier 75. In addition, transistors Q45, C47, diode D1+
and transistor C46% diode D+2, I)+5
constitutes a current mirror circuit. A resistor R1o, a diode 14, and a transistor Qas=C53 constitute a current source circuit.

According to the above configuration, the voltage held in the capacitor C1 is applied to the base of the transistor Q44 through the buffer, and is held in the capacitor C2.
The voltage is applied to the base of transistor Qa3 through the buffer. The output signal S of this differential sling 75
O is the current l at the output terminal 76. Obtained as 1.

FIG. 6 shows an embodiment in which the present invention is applied to the automatic white balance adjustment circuit of FIG. 1, and parts corresponding to those in FIG. 1 are given the same reference numerals.

In FIG. 6, the sample hold circuits 29n, 2
9G, 29B, 3LIR, 50G, 30B are capacitors C3 to C5, C7 to C2 and switch 77rt,
77G, 77, 78R17aG, 78. ), the configuration formula can be obtained as shown in the figure. Also, the differential amplifier 7 in FIG.
5, the differential amplifier 31n% 31a, 31n,
32R162G, 32. There are used awns. The switch 77 is turned on and off by the pulse PB together with the switches 77n and 77B%77B, and the reference voltage VI3 is sampled and held in the capacitor C6. Further, the switch 7B and the switch 7'Itv 780s76B are turned on and off by one pulse Pw, and the &A<
Sample A and hold the capacitor 01o). Input terminal 79I! , 79. ．． 79n+ is the cathode current detection circuit 28R, 28G in FIG.
Detection signals RLK, OIK, and BiK are applied from 28Il.

As described above, when the present invention is applied to one automatic white balance adjustment circuit, the circuit configuration shown in FIG. This is advantageous because it can be done as follows. still,
Each capacitor is selected, for example C3=. Since these capacitors 03 to C1° can be formed inside the IC circuit, the number of external terminal pins and the number of external parts can be greatly reduced.

Effects of the Invention Long period sample and hold can be performed using a small capacitance capacitor. Therefore, inside the IC circuit there is a
It is possible to use capacitors with i, -g.

Therefore, the number of terminal bins of the IC3 circuit and the number of external parts can be reduced.

[Brief explanation of the drawing]

Figure 1 shows the application of the present invention? 2 is a block diagram of a television receiver including a conventional automatic white balance adjustment circuit, FIG. 2 is a timing chart of FIG. 1, FIG. 6 is a block diagram showing an embodiment of the present invention, and FIG. 5 is a circuit diagram showing an example of the specific circuit configuration of FIG. 6, and FIG. 6 is a timing chart of FIG. 7 when the present invention is applied to the automatic white balance adjustment circuit of FIG. 1. In the block diagram showing the example, in the reference numerals used in the drawings, 72...... Switch 76...
・・・・・・Switch 75・・・・・・・・・・・・
Differential amplifier 01.02...Capacitor Vs...Reference level P...
......This is a sampling pulse. Agent: Satoshi N. Katsutsune Kae Yoshio Figure 2 Figure 3 Figure 4 50-1111

Claims (1)

[Claims] a first sample-and-hold circuit that is operated by a sampling pulse to sample and hold an input signal; a second sample-and-hold circuit that is operated by the sampling pulse to sample and hold a certain reference level;
A sample and hold circuit comprising a differential circuit to which the outputs of the first and second sample hold circuits are applied.