JP2008205544A - Offset correction circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an offset correction circuit little affecting a feedback control loop and preventing an error based on offset from remaining in an output current or an output voltage. <P>SOLUTION: An input terminal of an offset holding circuit 7 is connected to a circuit contact where a signal to be fed back from the output side of an error amplifier OP1 to an inverting input terminal of the error amplifier OP1 is generated. The output side of a signal synthesis circuit 6 is connected to a non-inverting input terminal of the error amplifier OP1. Then, the output side of the offset holding circuit 7 and the output side of a first switch circuit 5 are connected to the input side of the signal synthesis circuit 6. An offset signal accumulated in a capacitor C10 in an offset detection period is synthesized with a control signal in the signal synthesis circuit 6 and the synthesized signal acts so as to cancel the offset of all circuit portions of a driver circuit 2 and the offset correction circuit 4. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an offset correction circuit attached to a driver circuit for supplying a current or voltage to a load, and relates to a technique for eliminating an error based on an offset generated in a current or voltage supplied to a load.

  In recent years, precision instruments that perform digital data processing and drive load devices such as motors and actuators in analog fashion according to the results obtained by the data processing have become mainstream. Taking a camera as a specific example of a precision instrument, the required focal length, exposure, and lens movement are calculated digitally, and the motor that actually moves the lens is controlled in an analog fashion. It has been broken. In such a device, a digital control target value obtained by data processing is converted into an analog value, and the current or voltage supplied to the load device is changed according to the analog control target value. Therefore, a D / A converter for converting a control target value from a digital quantity to an analog quantity and a driver circuit for adjusting a current or voltage supplied to the load device according to the control target value are provided inside the device. Will be configured.

FIG. 2 shows connection examples of the DA converter, driver circuit, and load device, and a specific example of a conventional driver circuit.
In FIG. 2, 1 is a D / A converter, 2 is a driver circuit, and 3 is a load device. The signal output terminal of the D / A converter 1 is connected to the control signal input terminal 2 a of the driver circuit 2, and the current supply terminal 2 b of the driver circuit 2 is connected to the power supply line V _DD via the load device 3. It is assumed that the D / A converter 1 is configured to receive data from a data processing device (not shown).

  Here, the driver circuit 2 includes a control transistor M1 having one end of the main current path connected to the current supply terminal 2b, and a detection resistor R1 connected between the other end of the main current path of the control transistor M1 and the ground. And an error amplifier OP1 whose output terminal is connected to the gate of the control transistor M1. The non-inverting input terminal of the error amplifier OP1 is connected to the control signal input terminal 2a, and the inverting input terminal is connected to a connection point between the control transistor M1 and the detection resistor R1.

  In the driver circuit 2 having the above configuration, the control transistor M1, the detection resistor R1, and the error amplifier OP1 form a current source using a voltage supplied to the control input terminal 2a as a reference voltage. For this reason, the driver circuit 2 performs an operation such that the current flowing through the load device 3 is set to a magnitude corresponding to the signal supplied from the D / A converter 1. Note that the value of the current flowing through the load device 3 is stabilized by a feedback control loop formed by the control transistor M1, the detection resistor R1, and the error amplifier OP1.

  By the way, it is well known that an actual error amplifier has an offset. When an error amplifier having an offset is used in the driver circuit 2, an error occurs in the magnitude of the current supplied to the load device due to the offset. Naturally, if the offset is large, the error of the load current also becomes large. Therefore, when high accuracy is required for the output signal, it is necessary to use a small offset error amplifier OP1 or to add a circuit for correcting an error due to the offset.

  A method of adding a circuit for correcting an error due to an offset (hereinafter, “correcting an error due to an offset is referred to as“ offset correction ”, and a circuit for this is referred to as an“ offset correction circuit ”) to the error amplifier. For the above, offset correction circuits having various structures have been proposed. Among them, for example, as shown in FIG. 3A, there is a method of connecting a circuit assembled by elements having substantially the same characteristics so as to cancel the offset of the error amplifier. . Apart from this, as shown in FIG. 3B, the output voltage of the error amplifier generated based on the offset of the error amplifier is temporarily held in a capacitor, and the input signal is corrected with the voltage held in the capacitor. There was also a thing. Specifically, the former method is disclosed in Patent Document 1, and the latter method is disclosed in Patent Document 2 and Patent Document 3.

The offset correction circuits of Patent Document 2 and Patent Document 3 that use the voltage held in the capacitor are similar to the offset correction circuit of Patent Document 1 when the error amplifier and the offset correction circuit are created. There is no need to pay special attention to element placement. In addition, there is an advantage that errors based on the offset generated in the output signal can be almost eliminated. For this reason, in a scene where high accuracy is required for the output signal of the error amplifier, the opportunity to use an offset correction circuit as shown in Patent Document 2 and Patent Document 3 is increasing.
Japanese Patent Laid-Open No. 10-2233636 Japanese Patent Laid-Open No. 06-164258 JP-A-2005-159511

  The error amplifier is used not only for amplifying a signal but also for obtaining an output corresponding to a difference between two signals in a feedback control loop. When the error amplifier is used in the feedback control loop, requirements other than the offset must be taken into consideration so that inconvenient phenomena such as circuit oscillation and operation delay do not occur. For example, the offset correction circuit disclosed in Patent Document 3 has a configuration in which a capacitor is directly connected to one input terminal of an error amplifier. When such an offset correction circuit is connected to an error amplifier that constitutes a feedback control loop, the phase of the feedback signal transitions due to an offset correction capacitor, which does not cause oscillation or operation delay. You have to be careful.

Further, the offset correction circuit disclosed in Patent Document 2 has a configuration including a follower circuit therein. This follower circuit is provided to prevent consumption of the voltage held in the capacitor. If this follower circuit has an offset, an error based on the offset remains in the output signal of the main error amplifier.
Therefore, an object of the present invention is to provide an offset correction circuit that has little influence on the feedback control loop and does not leave an error based on the offset in the output current or output voltage.

  The present invention for solving the above problems comprises a control transistor for adjusting an output current or an output voltage and an error amplifier for supplying a drive signal to the control transistor. An offset correction circuit that is connected to a driver circuit that forms part of a feedback control loop for stabilizing an output current or output voltage and corrects an error based on an offset generated in the output current or output voltage, A first switch circuit configured to selectively supply either an input signal supplied from the outside or a voltage signal at a reference potential point to the signal synthesis circuit; and a signal from the first switch circuit and an offset A signal synthesis circuit for synthesizing a signal from the holding circuit and supplying the synthesized signal to the error degree amplifier; and a control transistor An offset holding circuit for detecting and holding an offset signal corresponding to the offset of the driver circuit from the current or voltage generated according to the operating state of the star, and for supplying the held offset signal to the signal synthesis circuit. The configuration is as follows.

  Here, in the offset detection period provided before the driving period, the first switch circuit operates so as to supply the voltage signal at the reference potential point to the signal synthesis circuit, and the offset holding circuit is connected to the control transistor. It is assumed that an offset signal corresponding to the offset of the driver circuit is detected from the current or voltage generated according to the operating state, and the detected offset signal is held. In the driving period in which the driver circuit operates the load according to the input signal supplied from the outside, the first switch circuit operates to supply the input signal from the outside to the signal synthesis circuit, and the offset holding circuit Shall operate so as to supply the held offset signal to the signal synthesis circuit.

According to the configuration of the present invention, offsets caused by all circuit portions of the error amplifier and the offset correction circuit can be corrected together, and an error based on the offset does not remain in the output current or output voltage supplied to the load device. In addition, since the capacitor is not directly connected to the error amplifier and the signal before being supplied to the error amplifier is corrected, the circuit is likely to oscillate due to the influence of the offset correction capacitor and the operation delay is increased. The phenomenon is unlikely to occur.
Furthermore, even if the control transistor and the error amplifier are combined so as to have optimum characteristics as a driver circuit for a specific load device, or even if they are modularized or made into one chip, There is also an incidental effect that an offset correction circuit can be added.

The input terminal of the offset holding circuit is connected to a detection point of current or voltage, in other words, a circuit contact where a signal fed back from the output side of the error amplifier to one input terminal of the error amplifier is generated. The output side of the signal synthesis circuit is connected to the other input terminal of the error amplifier. The input side of the signal synthesis circuit connects the output side of the offset holding circuit and the output side of the first switch circuit.
Here, the first switch circuit receives the control input signal from the outside and the voltage signal at the reference potential point on its input side, and selectively outputs either the control signal or the voltage signal by the switching operation. The configuration is such that it is supplied to the synthesis circuit.

  The offset holding circuit is held by a capacitor for holding a voltage used as an offset signal, a second switch circuit connected between one end of the capacitor and a circuit contact for generating a feedback signal, and the capacitor. The voltage follower circuit for supplying the offset signal to the signal synthesis circuit while preventing the consumption of the voltage, and the voltage follower circuit is connected to the input terminal of the voltage follower circuit and one end of the capacitor. And a third switch circuit that selectively supplies one of the signals to the input terminal of the voltage follower circuit.

The signal synthesis circuit receives a signal from the first switch circuit and outputs an output signal with an inverted polarity, and performs an addition process on the output signal and the offset signal of the amplification circuit, And an adder circuit for supplying the obtained synthesized signal to the other terminal of the error amplifier.
Each part of the offset correction circuit configured as described above operates as follows in the operation period and the offset detection period.

  First, in the offset detection period provided before the operation period, the first switch circuit supplies a voltage signal at the reference potential point to the signal synthesis circuit. On the other hand, inside the offset holding circuit, the second switch circuit connects between one end of the capacitor and a current or voltage detection point. The third switch circuit supplies a voltage signal at the reference potential point to the input terminal of the voltage follower circuit. The signal synthesis circuit supplies a synthesized signal obtained by synthesizing the signal from the first switch circuit and the signal from the offset holding circuit to the error amplifier. At this time, the signal (= voltage) appearing at the detection point of the current or voltage is generated based on the offset of all the circuit parts included in the driver circuit and the offset correction circuit, and passes through the second switch circuit. It is supplied to the capacitor of the offset holding circuit. This signal is accumulated in the capacitor as an offset signal.

  During the operation period, the first switch circuit supplies an external control input signal to the signal synthesis circuit. On the other hand, the second switch circuit constituting the offset holding circuit opens between one end of the capacitor and the current or voltage detection point. The third switch circuit constituting the offset holding circuit supplies the offset signal accumulated in the capacitor to the signal synthesis circuit via the voltage follower circuit. The signal synthesis circuit generates a synthesized signal obtained by synthesizing the control input signal and the offset signal, specifically, a synthesized signal obtained by correcting the magnitude of the control input signal with the offset signal, to the error amplifier. Supply. Here, the component of the offset signal included in the combined signal acts so as to cancel the offset of all the circuit portions of the driver circuit and the offset correction circuit when the driver circuit operates according to the combined signal. As a result, an error based on the offset does not remain in the output current or output voltage.

FIG. 1 shows a configuration of a driver circuit for driving a load device and an offset correction circuit according to the present invention added to the driver circuit.
In FIG. 1, a control transistor M1 having one end of the main current path connected to the current supply terminal 2b, a detection resistor R1 connected between the other end of the main current path of the control transistor M1 and the ground, The driver circuit 2 is configured by the error amplifier OP1 whose output terminal is connected to the gate of the control transistor M1. The connection configuration between each element in the driver circuit 2 is the same as that in FIG. The offset correction circuit 4 according to the present invention is connected to the control signal input terminal 2a of the driver circuit 2.

Here, the offset correction circuit 4 of FIG. 1 is configured as follows.
An input terminal 4a to which an external control signal (for example, a signal generated in the D / A converter 1 in FIG. 2) is supplied is connected to an inverting input terminal of the error amplifier OP11 via a switch SW11 and a resistor R11. . A switch 12 is connected between the connection point of the switch SW11 and the resistor R11 and the ground. The first switch circuit 5 is formed by the switches SW11 and SW12.

  The non-inverting input terminal of the error amplifier OP11 is connected to the ground, and the output terminal of the error amplifier OP11 is connected to the inverting input terminal of the error amplifier OP12 via the resistor R13. The non-inverting input terminal of the error amplifier OP12 is connected to the ground, and the output terminal of the error amplifier OP12 is connected to the control signal input terminal 2a of the driver circuit 2. A resistor R12 is connected between the inverting input terminal and the output terminal of the error amplifier OP11, and a resistor R15 is connected between the inverting input terminal and the output terminal of the error amplifier OP12. The inverting input terminal of the error amplifier OP12 is also connected to the output terminal of the error amplifier OP13 via the resistor R14. A signal synthesis circuit 6 is formed by the error amplifiers OP11 and OP12 and the resistors R11, R12, R13, R14, and R15.

  The inverting input terminal of the error amplifier OP13 is directly connected to its own output terminal, and its non-inverting input terminal is connected to the ground via the switch SW32. The non-inverting input terminal of the error amplifier OP13 is connected to one end of the capacitor C10 via the switch SW31, and the other end of the capacitor C10 is connected to the ground. One end of the capacitor C10 is further connected to a connection point between the control transistor M1 and the detection resistor R1 via the switch SW21. Note that an offset holding circuit 7 is formed by the error amplifier OP13, the switches SW31, SW32, SW21, and the capacitor C10.

  The circuit of FIG. 1 configured as described above needs to store a voltage as an offset signal in the capacitor C10 before driving the load device in accordance with a control signal supplied from the outside. Therefore, when the circuit of FIG. 1 is actually used, a logic for storing the offset signal in the capacitor C10 is incorporated in the control device of the precision instrument. Then, at an appropriate time such as immediately after the precision device is started up or just before the driver circuit drives the load device, the circuit shown in FIG. In the following description, a period in which the circuit of FIG. 1 operates so as to accumulate an offset signal in the capacitor C10 is referred to as an “offset detection period”, and a period in which the load device is operated in accordance with an external control signal. Is called a “driving period”.

First, in the offset detection period, the circuit of FIG. 1 operates as follows.
At the start of the offset detection period, each switch in the offset correction circuit 4 is set to the following state.
SW11 = OFF
SW12 = ON
SW21 = ON
SW31 = OFF
SW32 = ON

  When the switch SW11 is turned off and the switch SW12 is turned on, the ground potential is supplied to the inverting input terminal of the error amplifier OP1. Then, a signal based on the offset of the error amplifier OP11 is generated at the output terminal of the error amplifier OP11. Similarly, when the switch SW31 is turned off and the switch SW32 is turned on, the ground potential is supplied to the non-inverting input terminal of the error amplifier OP13. Then, a signal based on the offset of the error amplifier OP13 is generated at the output terminal of the error amplifier OP13. Signals based on the offsets of the two error amplifiers OP11 and OP13 are supplied to the error amplifier OP12 via resistors R13 and R14, respectively.

  Here, since OP12, R13, R14, and R15 constitute an adding circuit, the signals output from the two error amplifiers OP11 and OP13 are added and supplied to the driver circuit 2. Inside the driver circuit 2, the control transistor M1 is driven in accordance with a signal supplied to the error amplifier OP1 via the control signal input terminal 2a. As a result, the current flowing through the control transistor M1 flows into the resistor R1, and also flows into the capacitor C10 via the switch SW21. The capacitor C10 is charged to a voltage value corresponding to the current flowing through the control transistor M1 and the resistance value of the resistor R1. The voltage stored in the capacitor C10 is used as an offset signal for canceling an error based on the offset included in the output current of the driver circuit 2 in the next driving period.

  After the charging of the capacitor C10 ends, the offset detection period ends at an appropriate timing. All switches that were ON immediately before the end of the offset detection period are switched OFF. At this time, when the switch SW21 is turned off, the accumulated voltage (offset signal) of the capacitor C10 is stored.

Next, in the driving period, the circuit of FIG. 1 operates as follows.
At the start of the driving period, each switch in the offset correction circuit 4 is set to the following state.
SW11 = ON
SW12 = OFF
SW21 = OFF
SW31 = ON
SW32 = OFF

  When the switch SW11 is turned on and the switch SW12 is turned off, a control signal is supplied to the inverting input terminal of the error amplifier OP1 from the outside (for example, the D / A converter in FIG. 2) via the input terminal 4a. The Then, a signal corresponding to the control signal with the polarity reversed is generated at the output terminal of the error amplifier OP11. On the other hand, when the switch SW31 is turned on and the switch SW32 is turned off, an offset signal is supplied from the capacitor C10 to the non-inverting input terminal of the error amplifier OP13. Since the error amplifier OP13 has a voltage follower configuration, a signal having the same magnitude as the offset signal is naturally generated at the output terminal of the error amplifier OP13.

  The signals output from the two error amplifiers OP11 and OP13 are added by an adder circuit composed of OP12, R13, R14, and R15, and supplied to the driver circuit 2. The error amplifier OP1 constituting the driver circuit 2 drives the control transistor M1 according to the output signal of the error amplifier OP12 supplied via the control signal input terminal 2a. As a result, the control transistor causes a current corresponding to the control signal to flow, and the load device (not shown) connected to the driver circuit 2 is driven by the current corresponding to the control signal.

  In the above circuit operation, the offset signal is obtained from the voltage that appears at the connection point between the resistor R1 and the control transistor M1 during the offset detection period. The connection point between the resistor R1 and the control transistor M1 is also a current (voltage) detection point for feedback control of the control transistor M1. If the error amplifier OP1 is operating normally, the voltages supplied to its inverting and non-inverting input terminals are substantially the same. For this reason, in the offset detection period, it can be considered that a voltage having the same magnitude as the offset signal is equivalently generated at the position of the control signal input terminal 2a. Actually, a voltage that appears equivalently at the control signal input terminal 2a (hereinafter referred to as an equivalent voltage) always appears during the operation of the circuit and causes an error in the output current (or voltage) of the driver circuit 2. . Therefore, it can be considered that this equivalent voltage equivalently shows the offset of the entire circuit of FIG.

In the circuit configuration of FIG. 1, the error amplifier OP11 and the amplifier OP12 perform an inverting amplification operation. Therefore, each output signal has a polarity opposite to that of the input signal. Then, the signal output from the error amplifier OP12 during the driving period is {− {− (control signal) + (offset signal)}}.
In effect, the magnitude is obtained by subtracting the offset signal from the control signal. As described above, an equivalent voltage appears at the position of the control signal input terminal 2a. Then, the voltage supplied to the non-inverting input terminal of the error amplifier OP1 during the driving period is {− {− (control signal) + (offset signal)} + (equivalent voltage)}
It becomes.

  Here, since the equivalent voltage has the same magnitude as the offset signal, only the control signal remains in the above equation. That is, equivalently, offsets (that is, equivalent voltages) included in all circuit portions of the offset correction circuit 4 and the driver circuit 2 are canceled by the offset signal, and only the control signal is applied to the non-inverting input terminal of the error amplifier OP1. Supplied. As a result, the current of the control transistor M1 driven by the error amplifier OP1 has a magnitude corresponding to only the control signal, and an error based on the offset does not remain in the output current.

  In the above description of the operation, it is assumed that the offset polarity of all circuit portions of the offset correction circuit 4 and the driver circuit 2 is positive. When the polarity of the offset becomes negative, the circuit having the configuration shown in FIG. 1 cannot detect an offset signal because no current flows through the control transistor M1 during the offset detection period. For this reason, when the polarity of the offset of the entire circuit becomes negative, an error based on the offset remains in the output current of the driver circuit 2.

  In designing and manufacturing a semiconductor device, it is difficult to eliminate the offset and to adjust the size to a predetermined value. However, it is possible to design and manufacture such that the polarity of the offset is always positive or negative. For example, if the offset of the offset correction circuit is positive and larger than the offset of the driver circuit, the polarity will be positive overall even if the offset of the driver circuit is negative. 1 can be used.

Incidentally, in order to make the offset correction circuit according to the present invention compatible with the case where the polarity of the offset of the entire circuit becomes negative, the circuit of FIG. 1 may be modified as follows. That is, in the circuit of FIG.
(1) The ground side terminal of the switch SW12 is connected to the ground via a reference voltage source.
(2) Between the ground side terminal of the capacitor C10 and the ground, the ground side terminal is connected to the ground via the reference voltage source in the offset detection period, and the ground side terminal is directly connected to the ground in the driving period. A new switch circuit will be installed.
If such a modification is added, it is possible to cope with the case where the polarity of the offset is negative.

  In the circuit of the embodiment of the present invention shown in FIG. 1, the polarity of the signal from the first switch circuit 5 is inverted in the error amplification OP11. If the polarity of the signal supplied via the input terminal 2a is negative, the error amplification OP11 can be omitted from the circuit of FIG. Even when the polarity of the signal supplied via the input terminal 2a is positive, the circuit portion including the error amplifier OP12 at the subsequent stage constitutes a “subtraction circuit” instead of the “addition circuit”. The error amplification OP11 can be omitted. When the error amplifier OP11 is omitted, the resistors R11 and R12 are also omitted together.

  In recent years, a driver circuit specialized for a specific load device has appeared in a form that is mounted on an integrated circuit and formed into a single chip, or a form that is modularized in one package. The offset correction method “directly connecting a capacitor to the input terminal of the error amplifier” exemplified in the section of the prior art is often difficult to apply to a one-chip, modularized driver circuit. On the other hand, the offset correction circuit of the present invention is special if the chip or the module has a configuration that can be electrically connected from the outside to the input terminal of the control signal and the current or voltage detection point for feedback control. Applicable as long as there are no restrictions. Thus, the offset correction circuit of the present invention has an advantage that it can be added to an existing driver circuit.

The circuit diagram which shows the structure of a driver circuit and the offset correction circuit by this invention. The circuit diagram which shows each connection relation of DA converter, a driver circuit, and a load apparatus, and the structure of the conventional driver circuit. The circuit diagram which shows the structure of the conventional offset correction circuit.

Explanation of symbols

2: Driver circuit 2a: Control signal input terminal 3: Load device 4: Offset correction circuit 4a: Input terminal 5: First switch circuit 6: Signal synthesis circuit 7: Offset holding circuit M1: Control transistor OP1: Error amplifier C10 : Capacitor SW21: switch SW31 of the second switch circuit: switch SW32 of the third switch circuit: switch OP13 of the second switch circuit: error amplifier OP12 of the voltage follower circuit: error amplifier of the adder circuit

Claims (3)

A control transistor for adjusting an output current or an output voltage and an error amplifier for supplying a drive signal to the control transistor are provided, and the control transistor and the error amplifier stabilize the output current or the output voltage. An offset correction circuit that is connected to a driver circuit that forms part of a feedback control loop for correcting an error based on an offset that occurs in an output current or an output voltage thereof,
A first switch circuit configured to selectively supply one of an externally supplied input signal and a reference potential point voltage signal to the signal synthesis circuit;
The signal synthesis circuit for synthesizing the signal from the first switch circuit and the signal from the offset holding circuit, and supplying the synthesized signal to the error degree amplifier;
For detecting and holding an offset signal corresponding to the offset of the driver circuit from the current or voltage generated according to the operating state of the control transistor, and further supplying the held offset signal to the signal synthesis circuit The offset holding circuit;
Comprising
In the offset detection period provided before the drive period, the first switch circuit operates to supply a voltage signal at a reference potential point to the signal synthesis circuit, and the offset holding circuit includes the control transistor The offset signal corresponding to the offset of the driver circuit is detected from the current or voltage generated according to the operation state of the driver, and the detected offset signal is held.
In the driving period in which the driver circuit operates a load in accordance with an input signal supplied from the outside, the first switch circuit operates to supply an input signal from the outside to the signal synthesis circuit, and The offset holding circuit operates to supply the held offset signal to the signal synthesis circuit. The offset holding circuit is
A capacitor for holding the offset signal;
A voltage follower circuit for supplying the offset signal to the signal synthesis circuit;
A second switch circuit which is turned on during the offset detection period and connects one end of the capacitor to a detection point of a current or voltage generated according to an operating state of the control transistor;
A third switch circuit that connects the input terminal of the voltage follower circuit to the reference potential point during the offset detection period, and connects the input terminal of the voltage follower circuit to one end of the capacitor during the driving period;
The offset correction circuit according to claim 1, comprising: The signal synthesis circuit is
An inverting differential amplification type amplifier circuit for receiving a signal from the first switch circuit;
An inverting differential amplification type addition circuit that receives a signal from the amplification circuit and a signal from the offset holding circuit and outputs a combined signal obtained by adding both signals;
The offset correction circuit according to claim 1, further comprising:

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