JP2734244B2 - Output level control circuit of high frequency power amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output level control circuit of a high frequency power amplifier, and more particularly to a TDMA wireless communication system and a digital cellular mobile telephone system (Group S).
The present invention relates to a control circuit of this type which is suitable for a high-frequency power amplifier of a communication type transmitting apparatus using a high-frequency signal having a plurality of selectable output levels such as intermittent and specific mobile.

[0002]

2. Description of the Related Art In order to maintain the transmission power of a radio communication apparatus at a predetermined output level, a high-frequency power signal level detection circuit (hereinafter, referred to as a high-frequency detection circuit) for detecting a peak value of a high-frequency signal to be transmitted is provided. Means for controlling the power amplifier in response to the output of the high frequency detection circuit is required. In particular, to maintain the transmission power constant at a plurality of predetermined levels over a wide temperature range, the high-frequency detection circuit includes:
It is necessary to detect high-frequency power levels strictly, preferably linearly, over a wide dynamic range of transmission power and over a wide temperature range.

Reference (RJTURNER "A TEMPERATURE STABILI"
ZED RF DETECTOR WITH EXTENDEDDYNAMIC RANGE "32nd I
EEE Vehicular Technology Conference Record May 23-
26 1982, pp 231-242) and U.S. Patent No. 4,523,1.
55 (issued on June 11, 1985) is a circuit for satisfying the above-mentioned requirements, and is applicable not only to the above-mentioned intermittent high-frequency signal but also to a continuous high-frequency signal. Applicable. These prior art circuits consist of a detection diode that produces an output in response to the envelope of a high-frequency signal, and a temperature compensation diode that has the same characteristics as the detection diode and is thermally coupled.
Requires two diodes. In this circuit, the same forward bias voltage is applied to two diodes, and the difference between the load voltage of the detection diode and the load voltage of the temperature compensation diode is used as a high-frequency power level detection output. Since this detection output is obtained by subtracting the forward voltage of the temperature compensating diode from the forward voltage of the detecting diode, the former fluctuation accompanying the temperature change is eliminated by the corresponding latter fluctuation. Is done. Therefore, the high-frequency detection circuit can generate a detection output voltage that is substantially proportional to the peak value of the high-frequency signal without being affected by temperature changes.

[0004]

However, the above-described high-frequency detection circuit of the output level control circuit has a problem in that the characteristics of the circuit elements used vary, particularly the forward voltage and the forward voltage of both the detection and temperature compensation diodes. Difference in temperature characteristics,
In general, it is difficult to make the bias of both diodes the same over a wide temperature range because variations in the resistance values of the bias voltage supply resistor and the load resistor are generally unavoidable. Usually, since both components are used as individual components so that a high-frequency signal can be detected with high sensitivity, it may be difficult to thermally couple and install them at a place under the same temperature condition. For these reasons, the detected output voltage fluctuates due to a temperature change. Further, in order to compensate for the variations in the characteristics of the circuit elements, fine adjustments such as offsetting the bias voltage between the two diodes are required. Further, since both of the above diodes need to be constituted by two individual diodes, all of the high-frequency detection circuit and the power amplifier control circuit must be integrated with each other to reduce the cost and size.
It is difficult to convert. Accordingly, a first object of the present invention is to provide a high-frequency power amplifier for transmitting an intermittent high-frequency signal at a selected one of a plurality of predetermined output levels, and to stabilize each of the output levels over a wide temperature range. And an output level control circuit for maintaining the output level.

A second object of the present invention is to provide a high frequency detection circuit which constitutes a main part of the output level control circuit and detects all of the plurality of output levels with sufficient accuracy over the temperature range. .

A third object of the present invention is to provide a high-frequency power amplifier which is temperature-compensated and has a wide dynamic range.

A fourth object of the present invention is to provide a high-frequency detection circuit suitable for IC.

[0008]

A high-frequency detection circuit, which characterizes a high-frequency power amplifier output level control circuit of the present invention, transmits ON / OFF high-frequency power in bursts as in the case of the GSM cellular mobile telephone system. Suitable for controlling a high frequency power amplifier.

The high-frequency detection circuit includes a detection diode including a detection diode for generating a detection output corresponding to a peak value of a high-frequency signal taken as a part of the power amplifier output by a directional coupler from the output side of the high-frequency power amplifier. And a sample-and-hold circuit that samples and holds the detection output during the OFF period of the high-frequency power amplifier output. The sampled and held hold voltage and the detection output are input to a subtractor. The subtractor subtracts the former from the latter to generate an output corresponding to the peak value. The detection output and the hold voltage are detected by the detectors having substantially the same characteristics as described above, and the subtraction unit turns the output of the high-frequency power amplifier ON / OFF from the detection output for one cycle to turn the output of the power amplifier OFF. Since the detection output in the period is subtracted, the change in the detection output accompanying the temperature change is eliminated by this subtraction. As described above, the detection output of the high-frequency power amplifier output during the ON period is corrected by the detection output of the OFF period immediately before the period, and the change due to the temperature fluctuation is removed. Represents the high frequency power amplifier output faithfully over a wide temperature range. Also, since a bias voltage of about the forward voltage is applied to the detection diode, the high-frequency detection circuit can realize linear detection, and the high-frequency signal peak value versus the high-frequency signal level can be compared with the case where no bias voltage is applied. Is improved, and the dynamic range of high-frequency detection is widened.

In another example of the high-frequency detection circuit used in the present invention, a high-frequency signal from the directional coupler is first input to a detector including a detection diode to which a substantially forward bias voltage is applied. . The detection output from the detector is input to the current control circuit that controls the bias current of the detection diode so that the detection output of the high-frequency signal always becomes a predetermined value during the OFF period of the power amplifier. The bias current control circuit applies the bias current to the O during the ON period immediately after the OFF period.
It is kept at the constant value set during the FF period. That is, this bias current is corrected each time the power amplifier output is turned off, thereby eliminating fluctuations in the high-frequency detection output caused by temperature changes of circuit elements in the high-frequency detection circuit.

[0011]

Next, the present invention will be described with reference to the drawings.

Referring to the block diagram of the transmitter of FIG. 1 and the control signal waveform diagram of FIG. 2, a TDM embodying the present invention will be described.
The transmitter in the A or GSM wireless communication device includes a preamplifier 2 for amplifying a TDMA / GSM transmission signal RF supplied to an input terminal 1 and a power amplifier 3 for amplifying an output of the amplifier 2. Directional coupler 4 for guiding power-amplified burst transmission signal RF to antenna 5
And A high-frequency signal Vin, which is a part of the output of the power amplifier 3, is supplied from the directional coupler 4 to a high-frequency detection circuit 8, which generates a detection output voltage Vout corresponding to the peak value Va of the signal Vin. Detection output voltage Vout
Are supplied to the power amplifier control circuit 7 and correspond to a predetermined output power level of the power amplifier 3.
Is compared with a plurality of reference voltages set in advance. The power amplifier control circuit 7 supplies a control voltage according to the comparison result to the power amplifier 3, and automatically controls the power amplifier 3, that is, the output power level of the transmitter to a predetermined value. The transmitter can arbitrarily select one of a plurality of output power levels having a maximum difference of 2 dB at a maximum of 20 W or a maximum of 8 W and transmit.

Still referring to FIG. 1, the control signal Cont (burst ON signal) from the control signal input terminal 6 has an ON period of the transmission signal RF and an OFF period longer than the ON period.
Define a period. FIG. 2 shows a control signal Cont in the GSM standard digital car telephone system, the waveform of which is shown in FIG.
Defines a transmission power ON period of 0.577 msec and an OFF period of 4.039 msec (transmission OFF).
The ON / OFF cycle of the transmission power by the control signal Cont is 4.616 msec. The control signal Cont is
The power amplifier control circuit 7 and the high frequency detection circuit 8 are controlled. That is, the transmission signal RF and the high-frequency signal Vin are turned on.
During the period, the power amplifier control circuit 7 and the high frequency detection circuit 8 perform the transmission power control operation of the power amplifier 3. on the other hand,
During the transmission OFF period of the transmission signal RF and the high-frequency signal Vin, the transmission power control circuit 7 stops the operation of the power amplifier 3, so that the high-frequency detection circuit 8 does not receive the high-frequency signal Vin and the output voltage of the detection diode. Is stored or corrected.

Referring to the circuit diagram of the high-frequency detection circuit of FIG. 3, a high-frequency input terminal 81 of a high-frequency detection circuit 8A, which is a first example of the high-frequency detection circuit 8 in the transmitter of FIG.
A high-frequency signal Vin whose waveform is shown in FIG. 2 is input. The signal Vin is detected by the detector 83 including the detection diode D11, and the detector output voltage Vdet is output to the intermediate terminal 8.
4 is output. The detector output voltage Vdet is input to the sample and hold circuit 87. Sample hold circuit 8
7, the hold timing is controlled by a control signal Cont supplied from the control input terminal 6 of the high frequency detection circuit 8A. That is, the sample hold circuit 87 shuts off the input of the detector output voltage Vdet during the transmission power ON period, and shuts off the detector output voltage Vd during the transmission power OFF period.
sample and hold et. Thus, the sample hold circuit 87 outputs the detector output voltage Vdet as the hold voltage Vh. The detector output voltage Vdet and the hold voltage Vh are input to a subtractor 88, and a subtraction result Vout obtained by subtracting the former from the latter is output to an output terminal 89 of the high frequency detection circuit 8A. This high frequency detection output voltage Vo
ut is linearly proportional to the peak value Va of the high-frequency signal RF during the ON period.

The value of the detection output voltage Vout fluctuates during the OFF period and the ON period of the high-frequency signal Vin due to the temperature change of the forward voltage Vf of the detection diode D11. However, since the temperature fluctuation is extremely small between the OFF period and the subsequent ON period, the detector output voltage Vdet and the hold voltage Vh supplied to the subtractor 88 are detected under the same temperature condition. You can think that there is. Since the subtraction of the voltage Vh from the voltage Vdet by the subtracter 88 cancels out the fluctuation due to the temperature change of the diode D11 included in the voltage Vdet, the detection output voltage Vout faithfully represents the peak value Va of the high-frequency signal Vin.

In the above-described high-frequency detection circuit 8A, the detector 83 is provided with a capacitor C that receives the supply of the high-frequency signal Vin.
11, a detecting diode D11 connected in series to the capacitor C11, and a smoothing circuit including capacitors C13 and C14 and a choke coil L12. At the output end of the choke coil L12, a DC voltage Vd proportional to the peak value Va is generated. This DC voltage Vd is applied to the resistor R
13, R14 and an operational amplifier AMP11.
Becomes The peak value Va is the forward voltage V of the diode D11.
When it is sufficiently larger than f, the detection of the high-frequency signal in the detector 83 is a linear detection, and a detector output voltage Vdet almost proportional to the peak value Va is obtained. However, when the peak value Va becomes equal to or less than the forward voltage Vf, the detection by the detector 83 is performed by the detection diode D11.
Deviates significantly from linear detection, and therefore has a reduced dynamic range. In the detector 83, a bias current Ib substantially corresponding to a forward voltage of the diode D11 flows through the detection diode D11 to reduce the nonlinearity. Diode D11
, A bias current Ib flows from the positive bias terminal 82 to the negative bias terminal 85 through the resistor R11, the choke coils L11 and L12, and the resistor R12. The bias current Ib is set such that the DC voltage Vd applied to the + terminal of the operational amplifier AMP11 becomes 0 V during the OFF period of the high-frequency signal Vin, and the bias voltages + Vb and −V
Initially, Vb and the resistance values of the resistors R11 and R12 are initialized. Note that the DC voltage Vd does not necessarily have to be initially set to 0 V, and may vary depending on temperature fluctuations after the initial setting. By setting the bias current Ib of the detection diode D11 as described above, in the detector 83, the nonlinearity of the forward characteristic of the detection diode D11 is reduced, and a wide dynamic range can be obtained.

In the high-frequency detection circuit 8A, the sample hold circuit 87 receives the detector output voltage Vdet from the intermediate terminal 84 and turns ON / OFF in response to the control signal Cont from the control signal input terminal 6. An analog switch S21 that operates, and an operational amplifier AMP2 having a gain of 1 receiving a signal from the switch S21 at a + terminal.
1 (the-terminal connects the output terminal) and a capacitor C21 inserted between the + terminal and the ground potential. When the control signal Cont is OFF (that is, corresponding to the OFF period of the output of the high-frequency power amplifier), the switch S21 outputs the detector output voltage Vdet to the operational amplifier AMP2.
1 and supplies this voltage Vdet to the subtraction circuit 88 in the form of a hold voltage Vh. On the other hand, when the control signal Cont is ON (corresponding to the ON period of the output of the high-frequency power amplifier), the analog switch S21 is opened, and as a result, the detector output voltage Vdet is stored in the capacitor C21 as the hold voltage Vh. Therefore, the operational amplifier AMP21
Represents the detector output voltage Vdet in the immediately preceding OFF period over the ON period as the hold voltage Vh.
Continue feeding to 8. That is, the sample hold circuit 8
The hold voltage Vh from 7 is always substantially equal to the detector output voltage Vdet during the OFF period, and the value is updated every one ON / OFF cycle of the control voltage Cont.

Next, the above-mentioned subtraction circuit 88 comprises an operational amplifier AMP31 and resistors R31, R32, R33 and R3.
4 Detector output voltage Vd from intermediate terminal 84
et is connected to the + of the operational amplifier AMP31 via the resistor R32.
On the other hand, the hold voltage Vh from the sample hold circuit 87 is applied to the minus terminal of the operational amplifier AMP31 via the resistor R31. Operational amplifier A
MP31 calculates the hold voltage V from the detector output voltage Vdet.
The detection output voltage Vout is output to the output terminal 89 by subtracting h.

During the OFF period of the high-frequency signal Vin, the detector output voltage Vdet is at the level of the detection voltage during the OFF period, and the hold voltage Vh is also at the level of the detector output voltage during the OFF period. Output voltage Vo
ut becomes zero. On the other hand, in the ON period of the high-frequency signal Vin, a subtraction is performed between the detector output voltage Vdet in the period and the hold voltage Vh equal to the detector output voltage Vdet in the OFF period immediately before the ON period. The result is the detected output voltage Vout.

As described above, in the high frequency detection circuit 8A,
From the detector output voltage Vdet during the ON period, the OFF
Since the detector output voltage Vdet during the period is subtracted, it is possible to almost completely eliminate the influence of the fluctuation due to the temperature change of the forward voltage Vf of the detection diode D11. In addition, since the detector 83 requires only one diode for detection, the forward voltage V
The manufacturing cost can be reduced as compared with the above-described related art in which it is necessary to consider variations in f. Further, it is possible to prevent a decrease in the detection accuracy of the high-frequency signal level due to a temperature change inevitably in a circuit employing two diodes. Furthermore, since the sample and hold operation of the detector output voltage Vdet and the subtraction operation of subtracting the hold voltage Vh from the detector output voltage Vdet can secure the operation speed, the detection output voltage Vout can be obtained with high fidelity and a short response time. . Therefore, this high frequency detection circuit 8A is effective as an output level control circuit of a power amplifier of a high-speed TDMA / GSM transmitter.

The circuit including the sample and hold circuit 87, the subtraction circuit 88, the smoothing circuit of the detector 83 and the DC amplifier of the high frequency detection circuit 8A is a μPC3593 type IC.
(Made by NEC Corporation).
By adopting a circuit including this IC and the high frequency detection circuit 8A, the transmission power of the transmitter (FIG. 1) having a maximum power output of 8 W and set to 16 levels with an equal difference of 2 dB can be reduced by -30 ° C.
It can be controlled with an error of ± 1 dB in the temperature range from to + 85 ° C.

Referring to the circuit diagram of the high-frequency detection circuit of FIG. 4, a high-frequency detection circuit 8B, which is a second example of the high-frequency detection circuit 8 in the transmitter of FIG.
The same function as A is realized by a digital circuit (excluding the detector 83). In this high frequency detection circuit 8B,
The high-frequency signal Vin input to the high-frequency input terminal 81 becomes a detector output voltage Vdet by the detector 83, and is further converted by the A / D converter 91 into a digital detector output voltage Vd.
It is converted to et1. This digital detector output voltage Vd
et1 is a control signal Cont from the control signal input terminal 6.
Is input to a register 95 that samples and holds the input at every rising edge of the ON period defined by. The sampled and held hold voltage signal Vh1 is applied to a subtractor 93.
Is input to the-terminal. The subtractor 93 receives the supply of the digital detector output voltage Vdet1 at the + terminal, subtracts the hold voltage signal Vh1 from the detector output voltage Vdet1, and inputs the resulting difference voltage signal to the D / A converter 94. The D / A converter 94 converts the difference voltage signal into a detection output Vout which is converted into an analog signal, and outputs it to the output terminal 89. The A / D converter 91, the register 95, the subtractor 93, and the D / A converter 94 receive a common clock CLK from the clock input terminal 92. Here, register 9
5 and the subtractor 93 perform operations corresponding to the sample-hold circuit 87 and the subtractor 88 in the above-described high-frequency detection circuit 8A, respectively. That is, the detector output voltage Vdet1 during the OFF period is subtracted from the detector output voltage Vdet1 during the ON period to detect a peak value Va that eliminates the influence of a temperature change on the forward voltage Vf of the detection diode D11. it can. This high frequency detection circuit 8
B has a merit that it is easily formed into an IC because it is constituted by a digital circuit except for the detector 83.

Referring to the circuit diagram of the high-frequency detection circuit in FIG. 5, a high-frequency detection circuit 8C as a third example of the high-frequency detection circuit 8 in the transmitter in FIG.
As in the case of (1), the high-frequency signal Vin is received by the input terminal 81 and detected by the detector 83 to generate a detector output voltage Vout. Unlike the above-described examples 8A and 8B, in this example 8C, the detector output voltage Vdet obtained at the output of the detector 83 is used.
Is used as the detection output voltage Vout as it is. A bias circuit 97 is connected to the negative bias terminal 85 of the detector 83,
The bias current Ib is supplied to the detection diode D11 based on the potential difference between the positive bias terminal 82 and the bias circuit 97. The value of the bias current Ib is controlled by the bias current setting circuit 98. O of the high frequency power amplifier output
During the OFF period of the high-frequency signal Vin corresponding to the FF period, the high-frequency detection circuit 8C forms a negative feedback loop, and adjusts the value of the bias current Ib so that the detection output voltage Vout is set to a predetermined value, preferably 0V. Adjust by feedback loop. On the other hand, in the ON period immediately after the OFF period, the bias current setting circuit 98 controls the bias circuit 97 so that the bias current continues the bias current Ib in the OFF period. Thus, the bias current Ib is corrected at the beginning of each of the OFF periods of the high-frequency signal Vin, and the detected output voltage Vou during the ON period is corrected.
t is clearly determined as an increase from the detection output voltage Vout of the predetermined value in the OFF period. As a result, the high-frequency detection circuit 8C can prevent the influence of the temperature change on the detection diode D11 and the fluctuation of the detection output due to the variation of the constants of the circuit elements of the detector 83.

In the high-frequency detection circuit 8C shown in FIG. 5, a bias circuit 97 includes transistors TR41 and TR42 having a base and an emitter commonly connected, respectively, and a resistor R
41. The collector of the transistor TR41 is connected to the negative bias terminal 85 of the detector 83, and is connected to the output terminal of the bias current setting circuit 98 via the resistor R41. Transistor T
The collector current of R41, that is, the detection diode D1
The bias current Ib of 1 is substantially equal to the collector current of the transistor TR42, depends on the resistance value of the resistor R41 and the output voltage Vs of the bias current setting circuit 98, and changes in the output voltage Vs in the negative direction and the resistance of the resistor R41. Decreases with increasing resistance. The bias current Ib is determined by the resistor R12, the transistor TR41, and the bias voltage −
It flows to the circuit including the negative bias terminal 99 receiving the application of Vb.

In the high-frequency detection circuit 8C of FIG. 5, the bias current setting circuit 98 includes an operational amplifier AMP5
2. An inverting amplifier that includes resistors R52 and R53 and inverts the polarity of the detection output voltage Vout output from the detector 83. The control signal Con from the control signal input terminal 6 is controlled so that the polarity-inverted detection output voltage is closed during the OFF period of the high-frequency power amplifier output and opened during the ON period.
The signal is supplied to the analog switch S51 controlled at t.
The (polarized) inverted detection output voltage from the switch S51 is applied to an integration circuit including an operational amplifier AMP51, a resistor R51, and a capacitor C51. The output voltage Vs of this integration circuit is a voltage that changes in the negative direction when the detected output voltage Vout increases in the positive direction, and is supplied to the bias circuit 97. On the other hand, when the control signal Cont is transmitted O
During the N period, the analog switch S51 is opened,
Since the inverted output voltage is not applied to the integration circuit, the output voltage Vs in the immediately preceding OFF period is supplied to the bias circuit 95.

[0026]

As described above, the high-frequency detection circuit suitable for detecting the peak value of the intermittent high-frequency signal in the output level control circuit of the high-frequency power amplifier according to the present invention comprises a detector for each of the OFF periods of the output of the high-frequency power amplifier. Using the output as the reference value,
The peak value during the ON period of the output is determined as an increment from the reference value. Therefore, the high-frequency detection circuit is a circuit element indispensable for detecting the peak value, and the above-described configuration makes it possible to use only one diode whose characteristics are easily changed by a temperature change. Since the fluctuation is substantially eliminated by subtracting the peak value in the ON period and the peak value in the OFF period, a peak value with high fidelity can be obtained over a wide temperature range and a wide input peak value level. . Further, since this high-frequency detection circuit does not require a high-frequency diode for temperature compensation, which is indispensable for a conventional circuit of this kind, it is not only necessary to adjust a bias offset but also suitable for use in an IC. Therefore, the high-frequency power amplifier output level control circuit of the present invention employing this high-frequency detection circuit is suitable as a control circuit of a transmission device of a TDMA or GSM communication device using an intermittent high-frequency signal.

[Brief description of the drawings]

FIG. 1 is a block diagram of an example of a TDMA or GSM type transmitter embodying the present invention.

FIG. 2 is a waveform diagram of a control signal supplied to a power amplifier of the transmitter of FIG.

FIG. 3 is a circuit diagram of a high-frequency detection circuit forming a part of the transmitter of FIG. 1;

FIG. 4 is a circuit diagram of another example of the high frequency detection circuit.

FIG. 5 is a circuit diagram of still another example of the high-frequency detection circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Input terminal 2 Preamplifier 3 Power amplifier 4 Directional coupler 5 Antenna 6 Control signal input terminal 7 Power amplifier control circuit 8, 8A-8C High frequency detection circuit 81 High frequency input terminal 82 Positive bias terminal 83 Detector 84 Intermediate terminal 85 , 99 Negative bias terminal 87 Sample hold circuit 88, 93 Subtraction circuit 89 Output terminal 91 A / D converter 92 Clock input terminal 94 D / A converter 95 Register 97 Bias circuit 98 Bias current setting circuit AMP11, AMP21, AMP31, AMP51 , A
MP52 Operational amplifier C11 to C14, C21, C51 Capacitor D11 Diode L11, L12 Choke coil R11 to R14, R31 to R34, R41, R51 to R
53 Resistor S21, S51 Analog switch TR41, TR42 Transistor CLK Clock Cont Control signal Ib Bias current RF transmission signal Va Peak value Vb Bias voltage Vd DC voltage Vdet Detector output voltage Vdet1 Digital detector output voltage Vf Forward voltage Vin High frequency signal Vh Hold voltage Vh1 Hold voltage signal Vout Detection output voltage Vs Integration voltage

Claims (14)

(57) [Claims] 1. An output level of a high-frequency power amplifier that responds to a control signal having an ON period and an OFF period at a constant repetition cycle, amplifies an intermittent high-frequency signal corresponding to the control signal, and supplies the amplified signal to an antenna. A control circuit, comprising: a high-frequency power extracting means for extracting a part of the output of the high-frequency power amplifier; and a high-frequency detecting circuit for generating a detection output representative of the peak value in response to the output of the extracting means and the control signal. An output level control circuit of a high-frequency power amplifier, comprising: a detecting means for receiving the high-frequency signal and generating an output representative of the peak value of the signal; and an output of the detecting means during the ON period. And a difference voltage generating means for generating a voltage representative of a difference between the repetition period and the output during the immediately preceding OFF period. Output level control circuit of the high-frequency power amplifier, characterized in that. 2. An output level control circuit for a high-frequency power amplifier according to claim 1, wherein said detection means includes a detection diode. 3. The detection means sets the output of the high-frequency detection circuit to a predetermined voltage during the OFF period, and applies a forward bias current of a magnitude corresponding to the voltage to the detection diode during the ON period. 3. The high-frequency power amplifier output level control circuit according to claim 2, further comprising a supply unit. 4. The method according to claim 1, wherein the value of the forward bias current is
4. The output level control circuit for a high-frequency power amplifier according to claim 3, wherein the output voltage of the high-frequency detection circuit in the period F is set to a value that becomes a reference value. 5. An output of said detecting means which sampled and held the output of said detecting means during said OFF period for each of said repetition periods, and sampled and held the output during said OFF period and an ON period immediately thereafter. 5. An output level control circuit for a high-frequency power amplifier according to claim 4, further comprising: a sample-and-hold circuit that outputs the output of the sample-and-hold circuit from an output of the detection unit for each of the repetition periods. . 6. The detecting means includes: a diode for generating a voltage representing the peak value of the high-frequency signal; a smoothing circuit connected to an output of the diode; and an amplifier circuit for amplifying an output of the smoothing circuit. 2. The output level control circuit for a high-frequency power amplifier according to claim 1, further comprising: 7. An output level of a high-frequency power amplifier that responds to a control signal having an ON period and an OFF period at a constant repetition cycle, amplifies an intermittent high-frequency signal corresponding to the control signal, and supplies the amplified signal to an antenna. A control circuit, comprising: a high-frequency power extracting means for extracting a part of the output of the high-frequency power amplifier; and a high-frequency detecting circuit for generating a detection output representative of the peak value in response to the output of the extracting means and the control signal. An output level control circuit of a high-frequency power amplifier, comprising: a detection unit that receives the high-frequency signal and generates an output representative of a peak value of the signal; Means for converting, and said A corresponding to the output of said detection means during said OFF period.
Signal accumulating means for accumulating the output of the / D conversion means over the repetition period and outputting the output of the A / D conversion means at the beginning of the OFF period and the ON period immediately after the OFF period; Means for subtracting the output of the signal storage means for each repetition period. 8. An output level of a high-frequency power amplifier which responds to a control signal having an ON period and an OFF period at a constant repetition period, amplifies an intermittent high-frequency signal having a waveform corresponding to the control signal, and supplies the amplified signal to an antenna. The control circuit generates a detection output representative of the peak value in response to the control signal and an extraction output from the high-frequency power extraction means for extracting a part of the output of the high-frequency power amplifier, and outputs the detection output of the high-frequency power amplifier. A high-frequency detection circuit for supplying power to a gain control means for controlling a power amplification factor; a detection means for receiving the high-frequency signal and generating an output representative of a peak value of the signal; and an output of the detection means during the ON period. And a difference voltage generating means for generating a voltage representative of the difference between the output and the output during the immediately preceding OFF period for each of the repetition periods. High-frequency detecting circuit according to claim Mukoto. 9. The high-frequency detection circuit according to claim 8, wherein said detection means includes a detection diode. 10. The detection means sets an output of the high-frequency detection circuit to a predetermined voltage during the OFF period, and
10. The high-frequency detection circuit according to claim 9, further comprising: means for supplying a forward bias current having a magnitude corresponding to the voltage to the detection diode during the period. 11. The value of the forward bias current is
3. The output voltage of the high-frequency detection circuit during an FF period is set to a value that becomes a reference value.
0 high frequency detection circuit. 12. The output means of the detection means, wherein the difference voltage generation means samples and holds the output of the detection means during the OFF period for each of the repetition periods, and samples and holds the output during the OFF period and the ON period immediately thereafter. 12. The high-frequency detection circuit according to claim 11, further comprising: a sample-and-hold circuit that outputs an output of the detection unit; and a unit that subtracts an output of the sample-and-hold circuit from an output of the detection unit for each repetition period. 13. The detecting means includes: a diode for generating a voltage representing the peak value of the high-frequency signal; a smoothing circuit connected to an output of the diode; and an amplifier circuit for amplifying an output of the smoothing circuit. 9. The high-frequency detection circuit according to claim 8, comprising: 14. An output level of a high-frequency power amplifier that responds to a control signal having an ON period and an OFF period at a constant repetition period, amplifies an intermittent high-frequency signal corresponding to the control signal, and supplies the amplified signal to an antenna. The control circuit generates a detection output representative of the peak value in response to the control signal and an extraction output from the high-frequency power extraction means for extracting a part of the output of the high-frequency power amplifier, and outputs the detection output of the high-frequency power amplifier. A high-frequency detection circuit for supplying to a gain control means for controlling a power amplification rate, wherein the high-frequency detection circuit receives supply of the high-frequency signal and generates an output representative of a peak value of the signal; Means for A / D-converting the output of the detection means;
Signal accumulating means for accumulating the output of the / D conversion means over the repetition period and outputting the output of the A / D conversion means at the beginning of the OFF period and the ON period immediately after the OFF period; Means for subtracting the output of the signal storage means for each repetition period.