JPS6339921B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in multi-point analog output circuits used in control computers and the like.

FIG. 1 is a configuration and connection diagram showing a conventional example of a multi-point analog output circuit. 1 is a control circuit composed of a processor, 2 is a D/A conversion circuit that generates an analog output corresponding to the digital output from this control circuit 1, and 3 is an amplifier circuit that amplifies the output of this D/A conversion circuit 2. , 4 is a demultiplexer that switches the output of this amplifier circuit 3 to each channel, C ₁ to _{C o} are holding capacitors for each channel connected to each output terminal of this demultiplexer 4, and D ₁ to _{D o} are holding capacitors for each channel. Each channel is connected to a capacitor C ₁ -C _o , respectively, and consists of an amplifier circuit A ₁ -A _o , a transistor T ₁ -T _o and a current detection circuit R ₁ -R _o (usually composed of resistors). Voltage current conversion circuit, B ₁
~B _o is a zero point adjustment circuit at the input of the amplifier circuit A ₁ ~A _o , and L ₁ ~ _Lo is the voltage/current conversion circuit D ₁
~D _o is the load to which the output current is applied, respectively.

In the above configuration, the digital output from the control circuit 1 is converted into an analog signal by the D/A conversion circuit 2, and this analog signal is amplified by the amplifier circuit 3. The output of the amplifier circuit 3 is distributed to each channel by a demultiplexer 4, and a current output is generated from the voltage-current conversion circuits D ₁ to D _o of each channel.

A multi-point analog output circuit having the above configuration has the following drawbacks. That is, since the voltage-current conversion circuits D ₁ to D _o of each channel generate offsets of different values due to the amplifier circuits A ₁ to _{A o} , etc., as shown by the zero point adjustment circuits B ₁ to B _o , A zero point adjustment circuit is required for each channel. For this reason,
This causes problems such as a large number of adjustment resistances and a large amount of adjustment man-hours.

The present invention has been made in order to eliminate the above-mentioned drawbacks, and an object of the present invention is to realize a multi-point analog output circuit with a small number of zero point adjustment resistors and a small number of zero point adjustment steps.

According to the present invention, the analog output of each channel is A/D converted and fed back to the control circuit, and the control circuit outputs a digital value that cancels out the offset that exists for each channel of the output circuit. By adding, the above objective can be achieved.

The present invention will be explained below based on the drawings.

FIG. 2 is a configuration and connection diagram showing one embodiment of the present invention. 1 is a control circuit composed of a processor, 2
is a D/A conversion circuit that generates an analog output corresponding to the digital output from this control circuit 1, 3 is an amplifier circuit connected to this D/A conversion circuit, and B ₀ is a zero point adjustment at the input of this amplifier circuit 3. circuit,
4 is a demultiplexer that switches the output of this amplifier circuit 3 to each channel, C ₁ to _{C o} are holding capacitors that hold the output from each output terminal of this demultiplexer 4, and E ₁ to _{E o} are these holding capacitors.
a voltage-current conversion circuit for each channel connected to C ₁ to _{C o} , respectively, and composed of amplifier circuits A ₁ to A _o , transistors T ₁ to _{T o} , and current detection circuits R ₁ to _{R o} ;
L ₁ to _Lo are loads to which the output currents of the voltage-current conversion circuits E ₁ to _{E 2} are applied, respectively. 7 is a read back circuit that reads back the outputs from the current detection circuits R ₁ to _{R o} to the control circuit;
It is composed of a multiplexer 5 that selects one of the outputs from _R1 to _R0 , and an A/D conversion circuit 6 that generates a digital output corresponding to the output from the multiplexer 5 and applies it to the control circuit 1. . An embodiment of the current detection circuit R _i in FIG. 2 is shown in FIG. 3 along with its peripheral circuits. RA _i is an amplifier circuit that converts the current output of the i-th channel into voltage via a resistor, and one of its outputs is the amplifier circuit RA _i
and the other input is fed back to the read back circuit 7.

In the above configuration, when a digital output signal is applied from the control circuit 1, the D/A conversion circuit 2 generates an analog output corresponding to the digital output signal. This analog output is amplified by the amplifier circuit 3 and added to the i-th channel by the demultiplexer. The holding capacitor C _i holds the analog output, and the voltage-current conversion circuit E _i generates an output current corresponding to this held analog voltage, which is applied to the load.
Add to L _i . The current detection circuit R _i generates a voltage output corresponding to the output current and applies it to the multiplexer 5 .

The multiplexer 5 turns on the contact of the i-th channel according to the command from the control circuit 1, and the current detection circuit
The output voltage of R _i is applied to the A/D conversion circuit 6, and the corresponding digital output is read back to the control circuit 1.

Automatic adjustment of the zero point is performed as follows. First, the zero point is manually adjusted for channel 1 (any channel may be used) using the zero point adjustment circuit _B0 . In automatic adjustment mode, first control circuit 1
The voltage-current conversion circuit for the D/A conversion circuit 3
Set the output so that the output current from _E1 is 0. A circuit like the one shown in Figure 3 is used as a voltage-current conversion circuit.
When used as E ₁ , the output transistor T ₁
It is only necessary to set an output from the control circuit 1 such that the voltage is cut off. At this time, the outputs of the current detection circuits R ₁ to R _o of each channel e _a1 to e _ao (current detection circuits R ₁ to _{R o}
(equal to the offset voltage of) is fed back to the control circuit 1 via the readback circuit 7.
In the control circuit 1, the difference between the value of each channel and the value of one channel at this time Δe _a2 = e _a2 −e _a1 ..., Δe _ao = e _ao −
e _a1 (deviation of the offset voltages of the current detection circuits R ₂ to _{R o} from the offset voltage of the current detection circuit R ₁ ) is calculated and stored in the memory. Next, the control circuit 1 sets the output to the D/A conversion circuit 2 at 0%. The outputs e _b1 to _{e bo} of the current detection circuits R ₁ to R _o of each channel at this time are fed back to the control circuit 1 via the read back circuit 7, and as before, the control circuit 1 outputs each of the current detection circuits at this time. Difference between channel value and 1 channel value Δe _b2 = e _b2 −e _b1 ,…, Δe _bo = e _bo −
e _b1 (deviation from the value of channel 1 of the sum of offset voltages of amplifier circuit A _i and current detection circuit R _i in channels 2 to n) is calculated and stored in memory. Next, in the control circuit 1, in order to remove the offset component caused by the current detection circuit included in Δe _b2 to Δe _bo , Δe _c2 = Δe _b2 −Δe _a2 ,..., Δe _co = Δe _bo −
By calculating Δe _ao , the offset (difference) from one channel due to the amplifier circuit A _i of each channel can be found. Control circuit 1 in normal mode
From the output to channels 2 to n, respectively Δe _c2 ~
By subtracting Δe _co , it is possible to obtain a current output that does not include offset.

Note that in the A/D conversion circuit 6 of FIG.
By sharing the A conversion circuit 2, costs can also be saved.

In addition, in the embodiment shown in FIG. 2, one zero point adjustment circuit is provided at _B0 , but the D/A conversion circuit 2 and the amplifier circuit 3 are
If the control circuit 1 corrects each channel including the offset of the common portion of each channel, the zero point adjustment circuit can be completely eliminated.

As described above, according to the present invention, a multi-point analog output circuit with a small number of zero point adjustment resistors and a small number of zero point adjustment steps can be realized with a simple configuration. It is also less susceptible to changes in the zero point due to aging of the element.

[Brief explanation of the drawing]

FIG. 1 is a configuration connection diagram showing a conventional example of a multi-point analog output circuit, FIG. 2 is a configuration connection diagram showing an embodiment of the present invention, and FIG. 3 is an embodiment of the current detection circuit in FIG. 2. FIG. _{DESCRIPTION OF SYMBOLS 1...Control circuit, 6...A/D conversion circuit, 7...Read/back circuit, R1-Ro ...} Current detection circuit.

Claims (1)

[Claims] 1. In a multi-point analog output circuit that generates multi-point current output corresponding to digital signal output from a control circuit composed of a processor, there is a current detection circuit that converts the current output of each channel into voltage, and this current detection circuit. and a readback circuit that A/D converts the voltage output of and returns it to the control circuit. calculating the difference in offset error between the current output channel and the other channels, and correcting the digital signal output from the control circuit with a digital value that cancels out the offset error that exists for each channel of the current output. A multi-point analog output circuit characterized by being configured as follows.