JPH0677830A - Comparator and a/d converter using thereof - Google Patents

Abstract

PURPOSE:To provide a comparator and an A/D converter in which no error takes place even when fluctuation of a power supply voltage caused by a latch circuit is occurred. CONSTITUTION:The comparator is a comparator in which power supply systems 17, 18, 19 for an amplifier 3, a 1st latch circuit 4, a 2nd latch circuit 5 are separately provided. The power supply system is provided separately to the amplifier 3 and the 1st latch circuit 4 to prevent the effect of fluctuation of a power supply voltage caused by the 1st latch circuit 4 from being given onto the amplifier. The power supply system is provided separately to the 2nd latch circuit 5 to prevent the effect of fluctuation of a power supply voltage caused by the 1st latch circuit 4 and the 2nd latch circuit 5 from being given onto the 1st latch circuit 4. Thus, no error takes place in the case of comparison.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparator for comparing an input signal with a reference voltage and an A / D converter for converting an analog signal into a digital signal.

[0002]

2. Description of the Related Art An example of the structure of a conventional comparator is shown in FIG.

First, the operation of the amplifier 3 will be described.
An example of the configuration of the amplifier 3 is shown in FIG. This amplifier has
There are two states, an input state and an amplification state. The states of the analog switches 8 to 10 in each state are shown in FIG.

In the input state, the input signal 1 is applied to one end of the capacitor 6 through the analog switch 8. On the other hand, since the analog switch 10 connects the input end and the output end of the CMOS inverter 7, the other end of the capacitor 6 is C
It becomes the threshold voltage of the MOS inverter 7. Therefore, the capacitance 6 holds the difference between the input signal 1 and the two threshold voltages of the CMOS inverter 7.

Then, in the amplification state, the reference voltage 2 is applied to one end of the capacitor 6 through the analog switch 9.
When the reference voltage 2 is higher than the input signal 1, the voltage at this one end increases, and in the opposite case, it decreases. Since the voltage held by the capacitor 6 becomes constant after the end of the input period,
The voltage at the input terminal of the CMOS inverter 7 also rises or falls along with the rise and fall. Then, accordingly, the voltage at the output end of the CMOS inverter 7 drops or rises. The variation amount of this voltage is obtained by multiplying the difference voltage between the input signal 1 and the reference voltage 2 by the gain of the CMOS inverter 7. In this way, amplification is performed.

Next, the operation of the latch circuits 4 and 5 will be described. An example of the configuration of these latch circuits is shown in FIG. The latch circuit of FIG. 4 has two states, a transparent state and a holding state. The state of the analog switch in each state is shown in FIG.

In the transparent state, the input signal is applied to the CMOS inverter 11 through the analog switch 13 and amplified by the CMOS inverter 11 and the CMOS inverter 12. When the input signal is higher than the threshold voltage, the output voltage becomes a higher voltage, and when the input signal is lower than the threshold voltage, the output voltage becomes a lower voltage.

Then, in the holding state, the output voltage is applied to the CMOS inverter 11 through the analog switch 14. As a result, the output voltage becomes H level when the input signal is higher than the threshold voltage, and the output voltage becomes L level when the input signal is lower than the threshold voltage. In this way, the latch operation is performed.

Now, the comparator of FIG. 1 will be described. The timing of this comparator is shown in FIG.

In the input period (1), the amplifier 3 receives the input signal 1
Take in. In the comparison period (2), the amplifier 3 receives the input signal 1
And the difference voltage of the reference voltage 2 is amplified. The output is also transmitted to the latch circuit 4.

In the input period (3), the latch circuit 4 holds the output of the amplifier 3 as a digital value. The output is also transmitted to the latch circuit 4.

In the comparison period (4), the latch circuit 5 holds the output of the latch circuit 4. In this way, the comparison is performed.

FIG. 7 shows an example of the configuration of a conventional A / D converter. This is a 2-bit A / D converter. The comparators 15A, 15B, 15C are the comparators described above. The reference voltage 2A is applied to the comparators 15A, 15B and 15C.
And reference voltages generated by dividing 2B with a resistor are applied. The timing of this A / D converter can be represented in FIG. 6 as with the comparator described above. Each comparator is
Compare the input signal 1 and the given reference voltage,
The result is given to the encoder 16. Encoder 16
Calculates the input signal 1 between any two adjacent reference voltages generated by voltage division, based on the results given from the respective comparators. In this way, A / D conversion is performed.

[0014]

The comparator shown in FIG. 1 has the following problems.

During the input period, the amplifier 3 is in the input state and the latch circuit 4 is in the holding state. At this time, the output voltage of the latch circuit 4 is fixed at the H level or the L level. Then, in the comparison period, the amplifier 3 changes to the amplification state and the latch circuit 4 changes to the transmission state. At this time, since the analog value of the output of the amplifier 3 is input to the latch circuit 4, the output voltage of the latch circuit 4 also becomes an intermediate analog value between the H level and the L level. That is, when the comparator shifts from the input period to the comparison period, the output voltage of the latch circuit 4 greatly changes. The magnitude of this variation is on average one half of the output amplitude of the inverter. Along with this change, the power supply voltage of the latch circuit 4 also changes greatly.

At the same time, however, the amplifier 3 shifts from the input state to the amplification state. Amplifier 3 and latch circuit 4
If and share one power supply circuit, the power supply voltage of the amplifier 3 fluctuates at this time, and the CMOS in the amplifier 3 is changed.
The threshold voltage of the inverter also changes. As described above, the amplifier 3 performs amplification by using the threshold voltage of the CMOS inverter, so that an error occurs in the amplification in this case. This is the first problem.

On the other hand, during the comparison period, the latch circuit 4 is in the transparent state and the latch circuit 5 is in the holding state. At this time, the output voltage of the latch circuit 4 is an intermediate analog value between the H level and the L level. The output voltage of the latch circuit 5 is
It is fixed to H level or L level. Then, in the input period, the latch circuit 4 changes to the holding state and the latch circuit 5 changes to the transparent state. At this time, the output of the inverter of the latch circuit 5 changes from the previously held value to the output value of the latch circuit 4. That is, when the comparator shifts from the comparison period to the input period, the output voltage of the latch circuit 5 greatly changes. Along with this, the power supply voltage of the latch circuit 5 also greatly changes.

However, at the same time, the latch circuit 4 shifts from the transparent state to the holding state. If the latch circuit 4 and the latch circuit 5 share one power supply circuit, the power supply voltage of the latch circuit 4 changes at this time, and the threshold voltage of the CMOS inverter in the latch circuit 4 also changes. As described above, since the latch circuit 4 performs the holding operation using the threshold voltage of the CMOS inverter, an error occurs in the holding operation in this case. This is the second problem.

Conventionally, in order to eliminate such a defect, the power supply system of the comparator is divided into an analog system and a digital system, and even if the power supply voltage of the digital system fluctuates, the fluctuation of the analog system power supply voltage is prevented. The method of restraining is adopted.

However, when the amplifier 3 and the latch circuit 4 are analog and the latch circuit 5 is digital, the first problem remains. Further, when the amplifier 3 is an analog system and the latch circuits 4 and 5 are a digital system, the second problem remains. Therefore, in any case, an error occurred in the comparison with this comparator.

Further, the A / D converter using the comparator having such a problem also has the same problem.

The present invention has been made as a result of devising and researching the drawbacks of the conventional comparator and A / D converter as described above, and no error occurs even if the power supply voltage varies due to the latch circuit. It is intended to provide a comparator and an A / D converter.

[0023]

In order to solve the above problems, the present invention provides a comparator for amplifying a difference between an input signal and a reference voltage, and an output of the amplifier as a logical value. And a second latch circuit that receives the output of the first latch circuit as an input, the power supply system of the amplifier, the power supply system of the first latch circuit, and the second latch circuit. The power supply system of the second latch circuit is separated from each other.

An A / D converter according to a second aspect comprises a plurality of the comparators according to the first aspect, each comparator is supplied with the same input voltage and a different reference voltage, and the second comparator of each comparator is provided. The output of the latch circuit is input to the encoder circuit.

[0025]

The comparator according to the first aspect of the present invention has the above-mentioned construction and operates as follows.

By separating the power supply system of the amplifier and the first latch circuit, the fluctuation of the power supply voltage caused by the first latch circuit is prevented from reaching the amplifier. In addition, by separating the power supply system of the first latch circuit and the second latch circuit, the fluctuation of the power supply voltage caused by the second latch circuit is prevented from reaching the first latch circuit. As a result, no error occurs during comparison.

According to a second aspect of the present invention, an A / D converter is constructed by using the comparator according to the first aspect, whereby an A / D converter is provided.
No error occurs during conversion.

[0028]

(Embodiment 1) FIG. 1 shows an example of the configuration of a comparator according to claim 1 of the present invention. This structure is the same as the comparator described in the related art. However, the power supply systems of the amplifier 3, the latch circuit 4, and the latch circuit 5 are separated from each other.

Here, FIG. 8 shows an example of a method for separating the power supply system. In this case, a dedicated power source is prepared for each of the three circuits. According to this method, the power supply system can be completely separated.

FIG. 9 shows another example of the method for separating the power supply system. In this case, two power supplies are prepared, one of which is shared by the latch circuit 4 and the latch circuit 5. However, the power supply system of the latch circuit 4 and the latch circuit 5 is separated by the resistor 20. Where the resistor 20
Are not necessarily limited to resistors as circuit elements, but include wiring resistance, contact resistance, and the like. In FIG. 9, one power supply is shared by the latch circuit 4 and the latch circuit 5, but it is also possible to share one power supply by the amplifier 3 and the latch circuit 4 by a similar method. Further, it is possible to share one power supply for the amplifier 3, the latch circuit 4, and the latch circuit 5 in the same manner.

The timing of the comparator of the present invention is shown in FIG. This is also the same as the comparator described in the prior art,
The comparison is performed in the same manner.

As described in the problem to be solved by the invention, when the comparator of FIG. 1 shifts from the input period to the comparison period, the output voltage of the latch circuit 4 largely changes. Along with this, the power supply voltage of the latch circuit 4 also largely changes. However, since the power supply system of the amplifier 3 and the latch circuit 4 is separated, the power supply voltage of the amplifier 3 does not change. Therefore, no error occurs in amplification.

On the other hand, when the comparator of FIG. 1 shifts from the comparison period to the input period, the output voltage of the latch circuit 5 greatly changes. Along with this, the power supply voltage of the latch circuit 5 also greatly changes. However, since the power supply systems of the latch circuit 4 and the latch circuit 5 are separated, the power supply voltage of the latch circuit 4 does not change. Therefore, no error occurs in the holding operation. This solves the problems of the conventional technology.

(Embodiment 2) FIG. 7 shows an example of the configuration of the A / D converter according to claim 2 of the present invention.

This structure is the same as the A / D converter described in the prior art. However, the comparators 15A, 15B, 1
5C is the comparator of the first embodiment. At this time, the power supply systems of the amplifiers in the comparators are connected to each other and are not separated. The same applies to the first latch circuit and the second latch circuit.

If the A / D converter of the present invention is used, no error will occur during A / D conversion. This solves the problems of the conventional technology.

[0037]

As described above, according to the present invention, it is possible to obtain a comparator in which an error does not occur as compared with the conventional comparator.

(2) As explained above, according to the present invention, the A / D converter in which an error does not occur is compared with the conventional A / D converter.
A D converter can be obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention and a conventional comparator.

FIG. 2 is a configuration diagram of an amplifier used in FIG.

FIG. 3 is a state diagram of an analog switch used in FIG.

FIG. 4 is a configuration diagram of a latch circuit used in FIG.

FIG. 5 is a state diagram of an analog switch used in FIG.

6 is a timing diagram of the comparator of FIG.

FIG. 7 is a configuration diagram of a second embodiment of the present invention and a conventional A / D converter.

FIG. 8 is a configuration diagram of a comparator according to the first embodiment of the present invention.

FIG. 9 is a configuration diagram of a comparator according to the first embodiment of the present invention.

[Explanation of symbols]

 1 Input signal 2 Reference voltage 3 Amplifier 4,5 Latch circuit

Claims (2)

[Claims] 1. An amplifier which amplifies a difference between an input signal and a reference voltage, a first latch circuit which holds an output of the amplifier as a logical value, and a second which receives an output of the first latch circuit as an input. And a power supply system for the amplifier,
A comparator which separates a power supply system of the first latch circuit and a power supply system of the second latch circuit from each other. 2. A plurality of comparators according to claim 1, each of which is provided with the same input signal and a different reference voltage,
An A / D converter characterized in that the output of the second latch circuit of each comparator is input to an encoder circuit.