JPH0817460B2 - Key memory device - Google Patents

Description

The present invention relates to a circuit for processing a video signal represented by an electric signal, particularly a circuit for digitizing a video signal to generate a special effect, for displaying a video on a screen. The present invention relates to a device for storing a key signal indicating a position to be moved.

[Conventional technology]

Conventionally, as a device for storing a key signal, as shown in FIG. 6, a memory 611 corresponding to one screen is used, and an input key signal 601 is stored in the memory 611 and output. . Describing the operation of the circuit shown in FIG. 6, the key signal 601 is input to the memory 611, and the write control signal 602 controls permission / prohibition of writing to the memory 611. Key signal 6 written in memory 611
01 is sequentially read and becomes a key signal output 603.

[Problems to be Solved by the Invention]

In the conventional key memory device as shown in FIG. 6, even after the key signal 601 indicating a certain place on the screen is stored, the display position of the image is changed and the key signal is changed accordingly.
Unless the memory 611 is written again, the key output signal of the key memory circuit does not change. Therefore, it is impossible to display another image while moving the place by the key signal while displaying the image as a still image on a part of the screen.

An object of the present invention is to move another image by a key signal while still displaying the image as a still image on a part of the screen even when the image display speeds of the key signal input side and the key signal output side are different. It is to provide a key memory device having a display function.

[Means for solving the problem]

The present invention relates to a first memory means for successively storing and updating an input key signal, a means for controlling a timing for writing an input key signal in a memory, and a second memory means for writing control by the means. A means for erasing the stored contents of the second memory means, a key output signal output from the second memory means, and a key output signal output from the first memory means. A key memory device having means.

〔Example〕

 Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a key memory device according to the present invention.

In FIG. 1, 111 and 112 are memories, 113 is an OR circuit, 1
01 is a key input signal, 102 is a writing control signal to the memory 112, 103 is a deletion signal of the contents of the memory 112, 104 is a key output signal from the memory 111, 105 is a key output signal from the memory 112, and 106 is two. It is a signal obtained by the logical sum of the key output signals from the memory. The key input signal 101 is input to the memory 111 and the memory 112. The memory 111 writes the constantly input key signal 101 and outputs the updated key signal 104. On the other hand, in the memory 112, whether or not to write the key input signal 101 is controlled by the write control signal 102. Further, this memory 112 can erase the key signal written by the erase signal 103. The memory 111 and the memory 112 do not need to have the same key signal writing speed and reading speed. Therefore, the video display speeds on the key signal input side and the key signal output side may be different.

The key signal 105 output from the memory 112 indicates the fixed display position of the image, and the key signal 104 output from the memory 111 is constantly updated and the display position is changed, so these two key output signals are ORed together. By taking the logical sum with 113, the key signal 106 indicating both the fixed display position and the moving display position is obtained.

 FIG. 2 is a block diagram showing a second embodiment of the present invention.

In FIG. 2, 211 is an AND circuit, 212 is an inverting circuit, and 213.
214 is a selection switch, 215 and 216 are memories, 217 is an OR circuit, 2
01 is a key input signal, 202 is a signal obtained by inverting the key output signal 205 from the memory 216, and 203 is a key input signal by the signal 202.
201 is a gated signal, 204 is a write control signal to the memory 216, 206 is a key output signal from the memory 215, and 207 is a signal obtained by the logical sum of the key output signals from the two memories. The memory 215 always writes the input key signal and outputs the updated key signal. The memory 216 writes the key input signal only when writing is instructed by the writing control signal 204. Memory 21
In order to erase the contents of 6, writing may be performed with the selection switch 214 on the 2 side. The key input signal 201 is gated by the AND circuit 211 and then written into the memory 215. Here, when the selection switch 213 is on the 2 side, the AND circuit 211 becomes through and the input key signal 201 is written in the memory 215 as it is. FIG. 3 shows how this key signal is viewed on the screen. When the input key signal 201 is as shown in FIG. 3 (a), the key signal 206 output from the memory 215 is also the same. Next, when the selection switch 213 is on the 1 side, the memory 216
The input key signal 201 is gated by the output 205 of the key signal 203 stored in the memory and written to the memory 215. This is shown in FIG. When the shape of the key signal 205 stored in the memory 216 is as shown in FIG. 3 (b), the input key signal 201 as shown in FIG. 3 (a) is gated by the AND circuit 211, and FIG. 3 (c). It is written in the memory 215 in the form shown in. When the logical sum of the key output signal 206 of the memory 215 and the key output signal 205 of the memory 216 is calculated by the OR circuit 217, the logical sum signal 207 is as shown in FIG. 3 (d).

FIG. 4 is a block diagram showing the embodiment of FIG. 3 of the present invention.

In FIG. 4, 451 to 455 are memories, 456 is a 4-to-1 selection circuit, 457 and 459,461,463,468 are AND circuits, and 465 and 466 are NANs.
D circuit, 464 is an OR circuit, 458 and 460, 462, 467 are inverting circuits, 401 to 404 are key input signals, and 417 to 421 are key output signals. Memories 451 to 454 each contain 40 key input signals.
1 to 404 are constantly written at the video display speed of these key input signals, and the constantly updated key signals 409 to 412 are output at the video display speed of the key signal output side.

The key input signals 401 to 404 are further input to the 4-to-1 selection circuit 456.
, One of 401 to 404 is selected by the selection signal 406 and becomes the key signal 405. The key signal 405 is input to the memory 455, and is written in the memory 455 at the image display speed only when the writing control signal 407 permits writing. The memory 455 outputs the key signal 413 at the image display speed on the key signal output side. The contents of the memory 455 are erased by the erase signal 408. A key priority selection signal 414 determines the priority of the key signal 413 with respect to the key signals 409 to 412. That is, in the case where the image A whose position is shown by the constantly updated key signals 409 to 412 and the image B whose position is usually shown by the key signal 413 that represents a fixed position are combined and displayed on the same screen. , When the image A and the image B are displayed at the same position so as to overlap each other, it is a signal for designating which image is to be preferentially displayed.

The key priority selection signal 414 in the circuit of this embodiment is
A logical "1" is input when the key signals 409 to 412 have priority, and a logical "0" is input when the key signal 413 has priority. Traffic light 4
When 14 is logic “0”, it becomes “1” in the inverting circuit 467, and NAN
The D circuit 466 performs a logical product and inversion with the key signal 413 and outputs a signal 415. That is, the logic of the signal 415 becomes "0" when the key signal 413 exists. Signal 415 is AN
Input to D circuits 457, 459, 461, 463, and key signals 40 respectively
Gate 9,410,411,412. The signal 414 is also input to the NAND circuit 465, but if it is a logical “0”, the output 4 of the NAND circuit 465 will be output.
17 becomes logic "1", the AND circuit 468 becomes through, and the key signal 413 is directly output as the key output signal 422.
Next, when the signal 414 is logic "1", it is inverted by the inverting circuit 467 and logic "0" is added to the NAND circuit 466. The false signal 415 becomes logic "1", and the AND circuits 457, 459, 461, 463 are not gated. . In addition, the NAND circuit 465 operates as a circuit that inverts the signal 416. That is, the key signals 409, 410, 411, 412 are ORed by the OR circuit 464, and the signal 416 is inverted to obtain the signal 417. That is, the key signal 40
Signal 417 if any of 9,410,411,412 is present
Becomes a logical "0" and is input to the AND circuit 468, and the key signal 413
Will be gated.

A signal 423 obtained by inverting the key signal 409 by the inverting circuit 458 is also input to the AND circuit 459, and the key signal 410 is gated to form a key output signal 419. Similarly, a signal 423 is input to the AND circuit 461, and a signal 424 obtained by inverting the key signal 410 by the inverting circuit 460 is also input, and the key signal 411 is gated to form the key output signal 420. Similarly, the signal 423 and the signal 424 are also input to the AND circuit 463, and the signal 425 obtained by inverting the key signal 411 by the inverting circuit 462 is also input and the key signal 412 is gated to form the key output signal 421. These AND circuits 459,461,463
That is, the key signals 409, 410, 411, 412 are prioritized to be the key output signals 418, 419, 420, 421, respectively. In other words, when multiple images are displayed at the same position on the screen when combining and displaying the images whose positions are indicated by the key signals 409 to 412, the lower order key signals are masked by priority. -ing In the present embodiment, the priority order is in the order of the key signals 409, 410, 411, 412, each priority, masked by the upper key signal, and the signal gated by the signal 415 becomes the key output signal 418, 419, 420, 421, and is output. .

FIG. 5 shows a state in which the key signal is displayed on the screen. Fifth
(1), (2), (3), (4), and (5) represent key signals 409, 410, 411, 412, 413, respectively, and key output signals 418, 419, 420, 4 when the key priority selection signal 414 is logical "0".
21,422 in Fig. 5 (6), (7), (8), (9), (1
0) represents. Also, the state of the key output signals 418, 419, 420, 421, 422 when the key priority selection signal 414 is logical "1"
Figures (11), (12), (13), (14) and (15) are shown. FIG. 5 (16) shows a state of the key output signal 426 obtained by synthesizing all the key output signals 418, 419, 420, 421, 422 in the OR circuit 469. From these figures, it can be seen that the key signal of low priority is masked by the key signal of high priority. For example, FIG. 5 (6) shows a state in which (1) is masked by (5), and (7) shows a state in which (2) is masked by (5) and (1). In this way, giving priority to the key signal and masking it means that when displaying a plurality of images on the same screen, an image to be displayed in a portion where the images overlap is determined.

In this embodiment, a plurality of key signals are masked by priority. This requires that all key signals be synchronized at the same video display speed, but this is possible by providing a memory for all key input signals and reading them at the same video display speed. It is carried out.

〔The invention's effect〕

As described above, the present invention provides a memory for constantly writing and updating a key input signal, a memory that can control writing of the key input signal by a control signal, and has a means for erasing the contents of the memory, and the memory output from these two memories. By having the means to take the logical sum of the key signal
The key signal stored at a certain time point and the key signal at the current time point can be obtained at the same time. Therefore, the fine position adjustment of the key signal can be easily performed. Further, when the image display speeds of the key input signal and the key output signal are different, or when a plurality of key signals are input asynchronously, the key signals are synchronized and combined according to the present invention. You can

[Brief description of drawings]

FIG. 1 is a block diagram showing a key memory device of an embodiment of the present invention, FIG. 2 is a block diagram showing a second embodiment of the present invention, and FIG. 3 is (a), (b), (c). ) And (d) are explanatory diagrams in which key signals are illustrated to explain the second embodiment, FIG. 4 is a configuration diagram showing a third embodiment of the present invention, and FIG. 5 (1) to FIG.
(16) is an explanatory diagram in which key signals are designed to explain the embodiment of FIG. 3, and FIG. 6 is a configuration diagram showing a conventional example. 101,201 …… Key input signal, 102 …… Write control signal,
103 …… Delete signal, 104,105,106,205,206,207 …… Key output signal, 111,112,215,216 …… Memory, 113,217 …… OR
Circuit, 202 ... Inversion signal of key output signal from memory 216, 203 ... Key input signal after gate, 204 ... Memory
Write control signal for 216, 211 ... AND circuit, 212 ...
… Inversion circuit, 213,214 …… Selection switch, 401,402,403,4
04 …… Key input signal, 405 …… Key signal after selection, 406…
... Selection signal for 4-to-1 selection circuit 456, 407 ... Write control signal for memory 455, 408 ... Memory 455
Erase signal, 409,410,411,412,413 …… key signal from memory, 414 …… key priority selection signal, 415 ……
Key gate signal, 416 ... Key synthesis signal, 417 ... Key gate signal, 418,419,420,421,422 ... Key output signal, 42
3,424,425 …… Key inversion signal, 426 …… Key output composite signal, 451,452,453,454,455 …… Memory, 456 …… 4: 1
Selection circuit, 457,459,461,463,468 …… AND circuit, 458,460,
462,467 …… Inversion circuit, 465,466 …… NAND circuit, 469 …… O
R circuit, 601 ... key input signal, 602 ... write control signal for memory 611, 603 ... key output signal, 611 ...
memory.

Claims (1)

[Claims] 1. A first memory means for successively storing and updating an input key signal, a means for controlling a timing for writing an input key signal in a memory, and a second memory means for controlling writing by the means. A logical sum of a memory means, a means for erasing the stored contents of the second memory means, a key output signal output from the second memory means, and a key output signal output from the first memory means. A key memory device having means for obtaining.