JPH01869A - key memory device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to circuits that process video signals represented by electrical signals, particularly circuits that digitize video signals and generate special effects, for displaying images on a screen. The present invention relates to a device for storing a key signal indicating a position.

[Conventional technology]

Conventionally, as a device for storing key signals, a device has been used that uses a memory 611 corresponding to one screen as shown in FIG. 6, and stores an input key signal 601 in the memory 611 and outputs it. .

To explain the operation of the circuit shown in FIG. 6, the key signal 601
Memo! Input to J-611, write control signal 60
2 controls permission/prohibition of writing to the memory 611. Memo! Key signal 6 written to J-611
01 are read out sequentially and become the key signal output 603.

[Problem to be solved by the invention]

In the conventional key memory device as shown in FIG. 6, after storing a key signal 601 indicating a certain location on the screen, even if the display position of the image is changed and the key signal is changed accordingly,
Unless the memory 611 is written again, the key output signal of the key memory circuit will not change. Therefore, it is impossible to display an image as a still image on a part of the screen while moving another image using a key signal.

An object of the present invention is to display an image as a still image on a part of the screen and move the other image using the key signal even when the image display speeds on the key signal input side and the key signal output side are different. The object of the present invention is to provide a key memory device having a display function.

[Means to solve the problem]

The present invention provides a first method for sequentially storing and updating input key signals.
a memory means, a means for controlling the timing of writing the input key signal into the memory, a second memory means whose writing is controlled by the means, a means for erasing the memory contents of the second memory means, A key memory device characterized by comprising means for obtaining a logical sum of a key output signal output from the second memory means and a key output signal output from the first memory means.

〔Example〕

Next, embodiments of the present invention will be described using the drawings.

FIG. 1 is a block diagram showing a first embodiment of a key memory device according to the present invention.

In FIG. 1, 111 and 112 are memories.

113 is an OR circuit, 101 is a key input signal, and 102 is a memo! A write control signal to J-112, 103 is a signal for erasing the contents of memory 112, 104 is a key output signal from memory 111, and 105 is a memo! The key output signal 106 from J-112 is a signal obtained by ORing the key output signals from the two memories. key human power signal 1
01 is input to memory 111 and memory 112.

The memory 111 writes the key signal 101 that is constantly input, and outputs the updated key signal 104. On the other hand, in the memo ')-112, whether or not to write the key manual signal 101 is controlled by the write control signal 102. Also,
This memory 112 can erase the written key signal using the erase signal 103. Memory 111 and Memory 1
12, it is not necessary that the writing speed and the reading speed of the key signal match. Therefore, it does not matter if the video display speeds on the key signal input side and the key signal output side are different.

The key signal 105 output from the memory 112 indicates the fixed display position of the video, and the key signal 104 output from the memory 111 is constantly updated to change the display position, so these two key output signals are connected to an OR circuit. 113, a key signal 106 indicating both the fixed display position and the moving display position is obtained.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

In FIG. 2, 211 is an AND circuit, 212 is an inversion circuit, 213 and 214 are selection switches, 215 and 216 are memories, and 217t! OR circuit 2201 is a key human input signal, 202 is a memo! Key output signal 20 from J-216
203 is the signal obtained by gated key human signal 201 by signal 202, 204 is the memory 21
Write control signal to 6, 206 is memo! The key output signal 207 from J-215 is a signal obtained by ORing the key output signals from the two memories. The memory 215 constantly writes input key signals and always outputs updated key signals. Memo! J-216 writes the key manual signal only when writing is instructed by the write control signal 204. To erase the contents of the memory 216, it is sufficient to set the selection switch 214 to the 2 side and perform writing. The key input signal 201 is gated by an AND circuit 211 and then written to the memory 215. Here, when the selection switch 213 is on the 2 side, the AND circuit 2
11 is passed, and the input key signal 201 is written to the memory 215 as it is. FIG. 3 shows a screen view of this key signal. The input key signal 201 is as shown in FIG.
In the case shown in a), the key signal 206 output from the memory 215 is also the same. Next, the selection switch 213 is set to 1.
If on the side, note! Key signal 2 stored in J-216
The input key signal 201 is gated by the output 205 of 03 to memo! Written to J-215. This situation is shown in FIG. Memo! , the key signal 205 stored in I-216
3(b), the input key signal 201 as shown in FIG. 3(a) is gated by an AND circuit 211, and becomes the shape shown in FIG. 3(c), and is stored in the memory. 215
will be written to. When the key output signal 206 of the memory 215 and the key output signal 205 of the memory 216 are logically summed by the OR circuit 217, the logical sum signal 207 becomes as shown in FIG. 3(d).

FIG. 4 is a block diagram showing the embodiment of FIG. 3 of the present invention.

In FIG. 4, 451 to 455 are memories.

456 is a 4-to-1 selection circuit, 457 and 459,461°4
63.468 is an AND circuit, 465 and 466 are NAND
AND circuit 4 is an OR circuit, 458 and 460°462.4
67 is an inverting circuit, 401 to 404 are key input signals, and 417 to 421 are key output signals. memory 45
1 to 454 always write the key human power signals 401 to 404 at the video display speed of these key human power signals, and always output the updated key signals 409 to 412 at the video display speed of the key signal output side.

The key human signals 401 to 404 are further input to a 4-to-1 selection circuit 456, and the selection signals 406
One of the four signals is selected and becomes the key signal 405. This key signal 405 is input to the memory 455, and is written into the memory 455 at the video display speed only when the write control signal 407 permits writing. memory 455
outputs the key signal 413 at the video display speed on the key signal output side. The contents of the memo u-455 are erased by the erase signal 408. A key priority selection signal 414 determines the priority of the key signal 413 relative to the key signals 409 to 412. In other words, the key signals 409 to 4 are constantly updated.
In the case where image A whose position is indicated by 12 and image B whose position is indicated by a key signal 413 that normally indicates a fixed position are combined and displayed on the same screen, image A and image B
This is a signal that specifies which image should be displayed with priority when the two images are displayed overlapping each other at the same position.

The key priority selection signal 414 in the circuit of this embodiment is
Logic “1” when key signals 409 to 412 are prioritized
, a logic "0" is input when the key signal 413 is given priority. When the signal 414 is logic "0", the inverting circuit 4
67 becomes “1”, and the NAND AND circuit 466 signal 4
13 and is logically ANDed and inverted, and a signal 415 is output. That is, when the key signal 413 is present, the logic of the signal 415 becomes "0". Signal 415 is input to AND circuits 457, 459, 461, and 463, which gate key signals 409, 410, 411, and 412, respectively. The signal 414 is input to the NAND AND circuit 465, but if the logic is "0", the NAND AND circuit 465417
becomes a logic "1", the AND circuit 468 is turned on, and the key signal 413 is output as it is as the key output signal 422. Next, when the signal 414 is logic "1", it is inverted by the inverting circuit 467 and the logic "0" becomes NANDAND.
Because of the circuit 466, the signal 415 becomes logic “1”, and the AND
No gating is performed on circuits 457, 459, 461, 463. Furthermore, the NAND circuit 465 functions as a circuit that inverts the signal 416. That is, the key signal 409,410°411.41
2 are logically summed by an OR circuit 464, and the resulting signal 416 is inverted to form a signal 417. In other words, the key signal 409,4
If any of the signals 10, 411, and 412 exists, the signal 417 becomes logic "0" and is input to the AND circuit 468, which gates the key signal 413.

The AND circuit 459 inputs the key signal 409 to the inverting circuit 45.
A signal 423 inverted at 8 is also input, gates the key signal 410, and produces a key output signal 419. A signal 423 is similarly input to the AND circuit 461, and a signal 424 obtained by inverting the key signal 410 by an inverting circuit 460 is also input, gates the key signal 411, and generates a key output signal 420.
It is said that Signals 423 and 424 are similarly input to the AND circuit 463, and a signal 425 obtained by inverting the key signal 411 by the inverting circuit 462 is also input.
2 is gated and used as a key output signal 421. These AND circuits 459°461.463 prioritize the key signals 409, 410°411.412,
Key output signals 418, 419, 420, 421 respectively
It is said that In other words, key signals 409 to 412
When a plurality of key signals exist at the same position on the screen when combining and displaying the respective images whose positions are indicated by , the lower key signals are masked based on the priority order. In this embodiment, the priority is key signal 4.
09, 410, 411, 412, and depending on their respective priorities, the signal masked by the higher key signal and gated by the signal 415 is the key output signal 418.
, 419, 420° 421, and are output.

FIG. 5 shows how the key signal is viewed on the screen.

Figure 5 (1); (2), (3), (4), (5
) are key signals 409°410.411,412 respectively
, 413, and the key priority selection signal 414 is logic "0".
” key output signals 418, 419, 420, 42
1,422 in Figure 5 (6), (7), (8), (
9), GO) is represented. In addition, the key priority selection signal 41
Key output signals 418 and 419 when 4 is logic “1”,
420, 421, 422 are shown in Figure 5 αl), (Iri, 0■, (14), (lω). This shows the key output signal 426 synthesized by the OR circuit 469. From these figures, it can be seen that a key signal with a low priority is masked by a key signal with a high priority. For example, FIG. 1) is masked by (5), and (7) is how (2) is masked by (5) and (1). In this way, key signals are prioritized and masked. This means that when displaying multiple images on the same screen, the images to be displayed in the overlapping portions are determined.

In this embodiment, a plurality of key signals are masked by priority. This requires that all key signals be synchronized at the same video display speed, but this is possible by providing a memory for all key human input signals and reading them out at the same video display speed, and combining the key signals. It is carried out.

〔Effect of the invention〕

As explained above, the present invention consists of a memory for constantly writing and updating key human input signals, a memory that can control the writing of key human input signals using a control signal, and has a means for erasing the memory contents, and a memory for outputting data from these two memories. By having a means for calculating the logical sum of the key signals, the key signal stored at a certain point in time and the key signal at the present moment can be obtained simultaneously, and therefore, fine position adjustment of the key signal can be easily performed. Furthermore, in cases where the video display speed of the key input signal and the key output signal are different, or when multiple key signals are input asynchronously, the present invention can synchronize the key signals and synthesize them. Can be done.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a key memory device according to an embodiment of the present invention, Fig. 2 is a block diagram showing a second embodiment of the present invention, and Figs. 3 (a), (b), (c). , (d) is an explanatory diagram in which key signals are stylized to explain the second embodiment, FIG. 4 is a configuration diagram showing the third embodiment of the present invention, and FIG.
) to 0e are explanatory diagrams in which key signals are stylized to explain the embodiment of FIG. 3, and FIG. 6 is a configuration diagram showing a conventional example. 101.201...Key human signal, 102...
...Write control signal, 103...Erase signal, 104°105.106,205,206,207
・Group key output signal, 111, 112, 215, 21
6...Memory, 113.217...
OR circuit, 202...Inverted signal of key output signal from memory 216, 203... Key manual signal after gate, 204... Write control signal for group memory 216, 211... Group/AND circuit, 212
...Inverting circuit, 213, 214... Selection switch, 401, 402, 403, 404...
...key human input signal, 405... key signal after selection, 406... selection signal for 4-to-1 selection circuit 456, 407... write control signal for memory 455, 408...Memo! J-45
Erasing signal for 5, 409, 410, 411, 412
, 413... mark, key signal from memory, 414...
...Key priority selection signal, 415...Key gate signal, 416...Key synthesis signal, 417
...Key gate signal, 418.419,420
,421,422...Key output signal, 423,
424, 425...Key inversion signal, 426...
...Key output composite signal, 451,452°453.
454,455...Memory, 456...
...4-to-1 selection circuit, 457, 459, 461, 463
,468...AND circuit, 458,460,4
62,467...Inversion circuit, 465,466...
...NAND AND circuit 9...OR circuit, 601...Key human input signal, 602...
・Memo! Write control signal for J-611, 603
...Key output signal, 611...Memory. Agent Patent Attorney Uchihara Oto
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Claims (1)

[Claims] a first memory means for successively storing and updating input key signals; a means for controlling the timing of writing input key signals into the memory; a second memory means whose writing is controlled by the means; It has means for erasing the memory contents of the second memory means, and means for obtaining the logical sum of the key output signal output from the second memory means and the key output signal output from the first memory means. A key memory device featuring: