JPH0358120B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to an image display device equipped with an image memory, a CPU, a display device such as a CRT.

(b) Prior art In display devices with digital image memory, the position of displayed content on a part of the screen can be corrected,
To change it, you must memorize all previously displayed positions on the image, erase the previously written content, and then write a new one.

(c) Problems to be Solved by the Invention For example, when displaying temporal changes such as pulse-like distribution and blood flow velocity distribution in the horizontal direction (time axis) at the top, middle, and bottom of the screen, Since each screen is displayed continuously in the lower row, the upper row will be erased and the next change to be shown will be displayed again, or in the case of moving images, the screen will be displayed at the previous position in time. After erasing a certain image, the same or slightly changed image will be displayed in the next position, and it is necessary to write data to the image memory for erasing, correction, and change, and each time the CPU Such processing transfer is performed via.

In particular, when displaying moving images, the amount of information is large and must be transferred at high speed for reading and writing, but it is inefficient for the CPU to handle the processing each time.

In view of the above, an object of the present invention is to erase the previous image when displaying a moving image, etc. where there is a correction or change between images whose position changes temporally in a part of the screen. An object of the present invention is to provide an image display device that can reduce data transfer and processing between an image memory and a CPU for data writing.

(d) Means for solving the problem The above purpose is to provide an image memory that holds data regarding display contents and erasure control thereof, and a means for transferring and writing both data to the image memory via a CPU. , an image display means for reading only display data from the image memory and displaying the image on a display such as a CRT; a judgment/subtraction circuit for both of the data read from the image memory in synchronization with the image display; comprising a means for transferring and writing the output data of the circuit to the image memory, and the determination/subtraction circuit reduces the display content data by a fixed number by erasing data each time the image is displayed, or This is achieved by subtracting the erasure control data by a fixed number each time the image is displayed, and changing the display content data based on the result and outputting the result.

(e) Effect The data held in the image memory is composed of the display contents of a certain image and the data related to its erasure control, and on the other hand, the display contents data is read out for display on a display device such as a CRT. On the other hand, the data of the display contents changes for each display, and after a certain time, it is sent to a judgment/arithmetic circuit that outputs it as "0", and the output data is fed back to the image memory and written, and that time The image is then erased from the screen, and the data for this erasure does not need to be transferred to the image memory via the CPU.

(F) Embodiments Preferred embodiments of the present invention will be explained based on the drawings.

FIG. 1 is a schematic block diagram showing an embodiment of the present invention, in which 10 is a CPU, 12 is a CRT display, 14 is a write circuit, 16 is a read circuit, 18 is a digital image memory, and 20 is a synchronization signal. 22 is a read circuit, 24 is a judgment and subtraction circuit, and 26 is a write circuit.

Note that solid lines indicate the flow of data, and dotted lines indicate the flow of synchronization signals.

According to the present invention, first, each address of the image memory 18 includes at least display content data and erasure control information such as erasure of display content and density change, as shown in FIG. Alternatively, the first bit may be interpreted as a non-erasable bit, as shown. In the illustrated example, each address has N bits.

Based on this configuration, the data of the content to be displayed and the control data regarding its erasure are initially written into the image memory 18 by the CPU 10 via the writing circuit 14. For display on the screen, the readout circuit 16
The image memory is read out and displayed on the CRT display 12.

At the same time, in the present invention, the readout circuit 22
synchronously reads out the contents of the image memory 18, and the data is transferred to the determination/subtraction circuit 24.

Here, the determination/subtraction circuit 24 determines the displayed content, and if it is not ``0'', then determines the first bit, that is, unless the non-erasable bit is ``ON'', it decrements the erase control data. Then, unless the result is "0", the same display content and erase control information after subtraction are written into the image memory 18 again.

If the erase control data becomes "0" as a result of the calculation, such data is written into the image memory 18 by the write circuit 26 so as to erase (clear) the displayed content.

Alternatively, brightness, density, etc. can be changed by using other calculation examples, such as subtracting a certain number or erasure control data from the display content data, or by rewriting the display content according to other calculation results of the erasure control data. can.

Therefore, the judgment/subtraction circuit 24 and the writing circuit 2
6 is operating, there is no need for the CPU 10 to write data related to image changes at the same position, that is, data transfer processing.

Note that since the above-mentioned subtraction is performed in synchronization with the synchronization signal, it is also possible to preset the time until erasure from the display screen based on the erasure control data using data from the CPU 10. Become. If the screen does not need to be erased, the non-erasable bit can be set to "ON".

Furthermore, if the display content data is subtracted by a certain value or divided by a certain value using the erasure control data, a display device having an afterimage effect etc. can be realized.
The afterimage time can also be controlled by setting data from the CPU 10.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing an embodiment of the present invention, and FIG. 2 is a format example of an image memory according to the present invention. 10 is CPU, 12 is CRT display, 18
20 is an image memory, 20 is a synchronizing signal generator, 22 is a readout circuit, 24 is a judgment/arithmetic circuit, and 26 is a write circuit.

Claims (1)

[Claims] 1. An image memory that holds data related to display contents and erasure control thereof, a means for transferring and writing both data to the image memory via a CPU, and a means for reading only the display data from the image memory and displaying it on a CRT, etc. an image display means for displaying an image on a display; a determination/subtraction circuit for both data read from the image memory in synchronization with the image display; and means for transferring and writing output data of this circuit to the image memory. The determination/subtraction circuit subtracts the display content data by a fixed number from erasure control data for each image display and outputs the result, or subtracts the erasure control data by a fixed number for each image display. An image display device characterized in that display content data is changed and outputted according to the result.