JPH08172109A - Lsi design support system - Google Patents

Abstract

PURPOSE: To provide an LSI design support system which can automatically select the combination of a chip pad matching with the assembling conditions of wire bonding and the inner lead of an LSI package in the design for assembling an LSI chip in which more chip pads than the outer pins of the LSI package are prepared in advance into the LSI package. CONSTITUTION: The inner lead of an LSI package is connected to a chip pad in the direction of the inner lead by a wire by an initial wire generation means 13 with respect to the LSI chip and the LSI package inputted by a chip data input means 11 and an LSI package data input means 12. The assembling check means 16 is sequentially utilized by a wire adjustment means 14 with respect to the wire, and in the case where assembling requirements are not matched, the connection of a wire is sequentially changed to an adjacent chip pad. Thereby, the chip pad matching with assembling requirements is automatically combined with the inner lead of the LSI package.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to _an LSI design system, and in particular _{, an} LSI design system in which more chip pads than the number of external pins of an LSI package are preliminarily used in an LSI such as a gate array.
The present invention relates to an LSI design support system that is prepared on a chip, connects a chip pad that meets assembly conditions to an LSI package internal lead, and designs an electrical connection between an LSI chip and an external pin of the LSI package.

[0002]

2. Description of the Related Art A conventional LSI design support system is LS
When deciding the connection between the I chip and the LSI package, it was done manually whether or not actual assembly with a wire bonder was possible, but with the recent increase in the number of pins of the LSI chip and microfabrication, for example, JP-A-2-236675. As shown in Japanese Patent Publication, a computer is used to create _an LSI chip _{and an} LS.
When making an electrical connection with an external pin of the I package, interactively specify the connection between the chip pad and the internal lead of the LSI package while checking if it can be assembled with a wire bonder used in the actual assembly, and LS
The external pin electrical connection relationship of the I package is determined.

FIG. 9 is a block diagram showing an example of a conventional LSI design support system. Processing apparatus 1 performs more input data, processing instruction _{to the} keyboard 3, a mouse 2, a magnetic storage device 5 through the interface unit 21. Further, the data such as the LSI chip, the LSI package, the wire, and the error stored in the storage unit 22 via the interface unit 21 is output to the display 4, and the processing result is output to the magnetic storage device 5, the printer 6, and the plotter 7. . The chip data input means 11 registers data regarding the LSI chip, such as the chip outer shape and pad coordinates, in the storage unit 22 via the interface unit 21. The LSI package data input means 12 receives L via the interface unit 21.
Data relating to the LSI package such as the internal lead shape of the SI package and the external pin numbers connected to the internal lead are registered in the storage unit 22. Pin-connection means 1
7 is a chip pad and LS registered in the storage unit 22.
The electrical connection between the external pins of the LSI package and the chip pad is designated by designating the bonding point on the internal lead of the I package and designating the position where the wire of the wire bonder is stretched. When assembling the LSI chip and the LSI package by wire bonding from the position of the wire registered in the storage unit 22 and the data about the LSI chip and the data about the LSI package, the assembly checking unit 16 does not short-circuit the wires with each other, or Check for short circuit with other electrically independent internal leads. When an error is detected by the assembly check means 16, the pin connection means 17 changes the chip pad connected by a wire. Finally the data editing means 15 _edits LSI package by wire, the drawing showing the assembled state of the LSI chip, and outputs via the interface unit 21.

[0004]

DISCLOSURE OF THE INVENTION The conventional LSI described above
Design support system, in determining the electrical connection between the external pins of the chip pad and the LSI package, specifying the connection with the inner leads of the chip pad and LSI packages on one _not One manual, and the specified connection is wire bonder or the like If the actual assembling conditions are not satisfied, the manual correction is made to meet the assembling conditions.
Due to the recent increase in the number of pins of LSIs, the number of connections between chip pads and internal leads is also increasing. In particular, an LSI in which more chip pads than the number of external pins of the LSI package are prepared in advance on the LSI chip such as a gate array.
In this case, more chip pads must be connected to the chip pads that match the assembly conditions and the leads inside the LSI package, and it takes time to specify and modify by a conventional manual. In addition, as the number of LSI packages increases, LS must be designed in combination.
The number of combinations of I chips and LSI packages has also increased, and there has been a problem that it takes time to design.

[0005]

Means for Solving the Problems] LSI design support system of the present invention, LSI chip layout, _and chip data input means for inputting shape data regarding LSI package you want to include _LSI chip entered in the chip data input means LSI package data input means _for inputting data, chip data input means and chip input by the LSI package data input means, and LS
Assembling check means _for checking whether or not the assembling conditions in the work for assembling the I package are satisfied, and the chip data inputting means for all the internal leads to be connected to the chip pads of the LSI package input by the LSI package data inputting means. The initial wire generating means for automatically combining the chip pads on the LSI chip input in 1. and the assembling condition check of the chip pad and the internal lead combined by the initial wire generating means _are performed by using the assembling check means. If the LS does not match, the combination of the chip pad and the internal lead is automatically changed,
For I package data input means all inner leads to be connected to the chip pads of the LSI package entered in, characterized in that it comprises _a wire adjusting means for the combination of the assemblable chip pads.

[0006]

Embodiments of the present invention will now be described with reference to the drawings.

[0007] FIG. 1 shows the LSI design support system of the present invention.
It is a block diagram which shows one Example.

In this embodiment, as shown in FIG. 1, the processing device 1 includes a keyboard 3 via an interface unit 21,
The mouse 2, the magnetic storage device 5, and the network 8 are used to input data and instruct processing. Also the interface unit 2
LSI chip stored in the storage unit 22 via
Data such as the SI package, wires, and errors are output to the display 4, and the processing result is output to the magnetic storage device 5, printer 6, plotter 7, and network 8. The chip data input means 11 registers the LSI chip layout data including the chip outline and chip pad coordinates in the storage unit 22 via the interface unit 21. The LSI package data input means 12 includes an interface unit 21.
Via the internal lead shape of the LSI package data,
Specify the external pin number connected to the internal lead, the external pin number to be unconnected, the wire bonder model and assembly conditions used in the actual assembly, the wire material used in the assembly, the thickness, and the LSI package material. Register in the storage unit 22. The assembling check means 16 includes the storage unit 2.
2. When the chip pad and the internal lead of the LSI package are actually assembled by wire bonding from the position of the wire registered in 2 and the layout data of the LSI chip and the data about the LSI package registered by the LSI package data input means, the wires are connected to each other. Check items such as if there is a short circuit. The initial wire generation means 13 calculates the direction of the internal lead of the LSI package registered in the storage unit 22, and determines the wire that connects to the chip pad registered in the storage unit 22 that is closest to that direction. Register with. Wire adjusting means 1
Reference numeral 4 performs an assembly check by wire bonding on the wire registered in the storage unit 22 by using the assembly check means 16. If an assembly error is met, the error of the chip pad to which the wire is connected is eliminated. Repeating the change to the chip pads in the same direction, the wires connecting to the chip pads that can be assembled to the LSI package internal leads to be connected to all the chip pads registered in the storage unit 22 are changed. Storage of results 2
Register in 2. The data editing unit 15 collects data and assembling of all wires registered in the storage unit 22 from the LSI chip, the LSI package, and the wire bonder model to be actually assembled in the storage unit 22 in a data format suitable for the wire bonder model. The drawing for use is automatically edited and the data is output via the interface unit 21.

FIG. 2 is a diagram for explaining the assembly of an LSI chip and an LSI package by a wire bonder. LSI
The chip pads 32 on the chip _30, the wire ₃₃ is bonded onto _the inner lead 31 connected to the external pins 34 of the LSI package. As a result, the chip pad and the external pin of the LSI package are electrically connected.

FIG. 3 shows that the gate array such as a gate array is preliminarily L
More chip pads than the number of external pins of SI package
₃₂ is an LSI chip prepared on the LSI chip and L
It is a figure explaining the connection by the wire ₃₃ with the internal lead _{31 of} SI package. _From an external pin number of LSI packages combining the LSI chip 30 _on, i.e. than the number of inner _leads, a number of chip pads 32.
The internal leads 31 of the LSI package are connected to the chip pads by wires that match the assembly conditions.

FIG. 4 is a diagram for explaining an example of the assembly check. Chip pad 32 on LSI chip 30 and LSI
When the internal lead 31 of the package is connected to the wire 33, the assembly check is performed by focusing on each wire. Items to be checked include a wire length 40 that represents the horizontal distance between the start point and the end point of the wire of interest, a wire interval 42 that represents the distance between the wire of interest and the other wire closest to it, There is a wire / lead distance 41 that represents the distance between the wire and the nearest inner lead, and each value indicates an error unless it is within a certain range.

In the case of an assembly check error, the wire length is 40
The self-wire error in which an error occurs only in the wire focused on, such as the wire interval 42, the wire / lead interval 41
As described above, the wires are classified into two types, that is, a mutual error in which an error occurs due to the relationship between the focused wire, the other wire, and the internal lead.

FIG. 5 is a diagram for explaining the initial wire generation means in the LSI design support system of this embodiment. Initial wire generating means _focuses to the inner lead 31 of one LSI package, the lead direction 105 determined, the nearest chip pad in that direction (chip pad 10
0) is obtained and connected to the focused internal lead 31.

Next, the method of calculating the internal lead direction of the LSI package will be described in detail. On the inner lead 31, there is a basic bonding point 104 representing a position for bonding a wire. First, among the lines forming the outline of the inner lead, the lead side which is the line closest to the basic bonding point 104. 102, and then the distance to the basic bonding point 104 is a line having a projection point direction that forms an angle of 90 degrees or more from the projection point direction to the lead side 102 that is found from the lines that form the contour of the internal lead. Find the closest lead side 103. Determined lead sides _102, the line segment if the line shape of the lead side edge ₁₀₃ of the segment, in the case of arc have _use the arc tangent of the projection point from the basic bonding point 104, read sides 102 And lead side 1
Find the bisector of 03. LS on the obtained bisector
The vector facing the I-chip 30 side is the lead direction 10
It becomes 5.

Next, a method for obtaining the chip pad closest to the internal lead direction will be described in detail. The chip pad boundary line 35 is a maximum rectangle that does not include the center coordinates of all the chip pads on the LSI chip 30 and includes the center of the LSI chip. First, this chip pad boundary line 35
Of the chip pad boundary line 3 from the basic bonding point 104 in the internal lead direction obtained by the above _{calculation method.}
The chip pad that has the shortest distance to the line segment extended to 5 and to which the wire is not already connected (chip pad 10
0) is the chip pad closest to the internal lead direction.

FIG. 6 is a diagram for explaining an example of a wire adjusting method with a self-wire error used by the wire adjusting means in the LSI design support system of this embodiment. _It is assumed that the chip pad 211 on the LSI chip 30 and the internal lead 221 are connected by the wire 201. This wire 201
When a wire length error, which is a self-wire error, occurs in the chip pads on both sides of the chip pad ₂₁₁ , the chip pad that eliminates the error, that is, the chip pad that shortens the wire length is determined. The wire 201 is replaced with the obtained chip pad 212, and the internal lead 221 and the chip pad 212 are connected by the wire. However, the chip pad 212 has already been connected to the inner lead 222 and the wire 20.
2 is connected, the wire 202 is replaced with the chip pad 213, which is the one that further eliminates the error, so that the internal lead 222 and the chip pad 213 are connected by a wire, and a plurality of wires are not connected to one pad. To do so.

FIG. 7 is a diagram for explaining an example of a wire adjusting method for a mutual wire error used by the wire adjusting means in the LSI design support system of this embodiment. It is assumed that the chip pad 211 on the LSI chip 30 and the internal lead 221 are connected by the wire 201, and the chip pad 212 and the internal lead 222 are connected by the wire 202. If the error _{that has} small wire spacing 231 are mutually wire error between the two wires 201 and the wire 202 is generated, to as away from each other of the chip pads.
That is, the wire 201 is replaced from the chip pad 211 to the chip pad 214, and the wire 202 is replaced from the chip pad 212 to the chip pad 213. In this case, the connection relationship between the wire and the internal lead is not changed.

FIG. 8 is a flow chart showing the operation of the wire adjusting means in the LSI design support system of this embodiment.

The wire adjusting means (14 in FIG. 1) first initializes by substituting 0 into the repeat counter value I for counting the repetition of the whole process (step A1) _. Next, the wire counter value J for deciding the wire to be sequentially processed
0 is substituted for initialization (step A2), and then 0 is substituted for an error counter value K indicating the number of wires having an assembly condition error registered in the storage unit (22 in FIG. 1) for initialization. (Step A3), next, paying attention to the wire indicated by the wire counter, an assembly check is performed using the assembly check means (16 in FIG. 1) described in FIG. 4, and the check result is stored in the storage unit (22 in FIG. 1). Register with (Step A
4), it is determined whether there is a self-wire error in the assembly check performed in step A4. If there is a self-wire error, the process proceeds to step A6, and if not, the process proceeds to step A7 (step A5). If there is a self-wire error in step A5, as described with reference to FIG. 6, the error is resolved by the chip pads adjacent to the chip pad to which the wire in which the error has occurred (the wire indicated by the wire counter value J) is connected. Replace the wire on the other chip pad. If the chip pad to be replaced is already connected to another internal lead by a wire, the chip pads to which the wires are sequentially connected are shifted so that one chip pad is not connected to two or more wires (step A6),
Next, 1 is added to the error counter value K indicating that there was an assembly error (step A9), and further step A10.
Proceed to. If there is no self-wire error in step A5, it is judged in the assembly check in step A4 whether there is a mutual wire error. If there is a mutual wire error, the process proceeds to step A8. If not, the process proceeds to step A10 (step A7). ). If there is a mutual wire error in step A7, as described with reference to FIG. 7, the two wires in which the mutual error has occurred are reattached to the chip pads in the direction in which they separate from each other. If the chip pad to be replaced is already connected to another internal lead by a wire, the chip pads to which the wires are sequentially connected are shifted so that one chip pad is not connected to two or more wires (step A8), and proceeds to step A9.
If there is no mutual wire error in step A7, 1 is added to the wire counter value J representing the wire of interest (step A10), and the wire counter value J is registered in the storage unit (22 in FIG. 1). If it is the same as the number of wires, the process proceeds to step 12. If not, the process returns to step A4 to check the assembly of the next wire (step A1).
1). When the wire counter value J becomes equal to the number of wires registered in the storage unit (22 in FIG. 1) in step A11, 1 is added to the repetition counter value I representing the repetition of the whole process (step A12), and then If the error counter value K is 0, the process proceeds to step A14. If _the error counter value K> 0, the process proceeds to step A15 (step A13). If the wire counter value J is 0 at step A13, , Indicating that there is no assembly check error in all the wires registered in the storage unit (22 in FIG. 1), that fact is registered in the storage unit (22 in FIG. 1) (step A14), and the wire adjusting means (FIG. The processing of 14) of 1 is ended. In step A13, the error counter value K
> 0, when the maximum number of repetitions maxI smaller than repetition counter value I is set, the flow returns to step _A2, and from the processing (step A2 of the wire that is registered in the storage unit 22 to the Perform A13). If the repeat counter value I becomes equal to maxI, the process proceeds to step A16 (step A15). In step A15, when the repetition counter value I becomes equal to the maximum number of repetitions maxI, the storage unit (2 in FIG. 1).
The fact that the wire assembly error registered in 2) could not be resolved is registered in the storage unit (22 in FIG. 1) (step A16), and the processing of the wire adjusting means is terminated.

Next, the operation will be described mainly with reference to FIG. 1 and supplementarily with reference to FIGS. 4, 5, 6, 7, and 8. In chip data input means _11, to register the chip outline of LSI chips to be assembled, the LSI chip layout data including a chip pad coordinates in the storage unit 22. Chip data input means 1
The internal lead shape of the LSI package that you want to combine with _the registered LSI chip in 1, _the external pin number that is connected to the internal lead, the external pin number that you want to disconnect, the model of the wire bonder used in the actual assembly, and the assembly conditions The material and thickness of the wire used for assembly and the material of the LSI package are registered in the storage unit 22. Then using the initial wire generating means 13 described in FIG. 5, sequentially obtains the internal read direction for all inner leads other than the inner lead connected to the non-connection external pin which is _registered in the storage section 22 Further, the connection to the closest chip pad is registered in the storage unit 22. This initial wire generating means ₁₃ means that unique chip pads are connected by wires to all internal leads that must be connected to the chip pads. Then the wire adjusting means 14 described in FIG. 8, will eliminate the assembling error checking of all of the wires that are registered in the storage unit 22, _whether any error is eliminated, the storage unit 2
Register in 2. When all the assembly errors are eliminated by the wire adjusting means 14, the data editing means 15 registers the coordinate values of both ends of all the wires, which are registered in the storage unit 22, of the pads to which the wires are connected. And the coordinate value of the part connected to the internal lead and the wire bonder model actually used in the assembly process, in the data format suitable for the wire bonder model, data and chip outline for driving the wire bonder, chip pad , A wire and an internal lead shape of an LSI package are automatically edited and data is output through the interface section 21.

[0021]

As described above, the present invention provides an LSI
When deciding the connection between the chip and the LSI package, it is possible to automatically decide the connection suitable for the assembly condition in the wire bonder or the like, which has the effect of reducing the design time.

Since checking, design, data, and drawings are automated, there is an effect that even an unskilled person can create designs, data, and drawings.

Further, since the operator's instruction is not input during the processing, batch processing can be performed, and many LSs can be processed at one time.
This has the effect of allowing unattended design of a combination of an I chip and an LSI package.

[Brief description of drawings]

[Figure 1] An embodiment of the LSI design support system of the present invention
It is a block diagram shown.

FIG. 2 is a diagram illustrating assembly of an LSI chip and an LSI package by a wire bonder.

FIG. 3 is an LS in which more chip pads than the number of external pins of the LSI package are prepared on the LSI chip in advance.
It is a figure explaining the connection by a wire between an I chip and an internal lead of an LSI package.

FIG. 4 is a _{diagram illustrating an example of an} assembly check in the embodiment of FIG.

5 is a diagram illustrating the initial wire generating means _{in FIG.}

6 is a diagram illustrating an example of a wire adjusting method with a self-wire error used _{in the} wire adjusting means in FIG.

7 is a diagram illustrating an example of a wire adjusting method with a mutual wire error used _{in the} wire adjusting means in FIG.

FIG. 8 is a flowchart showing the operation _{of the} wire adjusting means in FIG.

FIG. 9 is a block diagram showing an example of a conventional LSI design support system.

[Description of marks _Nos.]

 1 Processing Device 2 Mouse 3 Keyboard 4 Display 5 Magnetic Storage Device 6 Printer 7 Plotter 8 Network 11 Chip Data Input Means 12 LSI Package Data Input Means 13 Initial Wire Generating Means 14 Wire Adjusting Means 16 Data Editing Means 16 Assembly Checking Means 17 Pin Connection Means 21 Interface Part 22 Storage Part 30 LSI Chip 31 Internal Lead 32 Chip Pad 33 Wire 34 External Pin 35 Chip Pad Boundary Line 40 Wire Length 41 Wire Interval 42 Wire Lead Interval 100 Pad 102 Lead Side 103 Lead Side 104 Basic Bonding Point 105 Lead Direction 201 Wire 202 Wire 211 Chip Pad 212 Chip Pad 213 Chip Pad 214 Chip Pad 221 Internal Lead 22 2 Internal lead

Claims (3)

[Claims] 1. A LSI chip layout, _and the LSI package data input means for inputting _the chip data input means for inputting shape data, data related to LSI package you want to include _LSI chip entered in the chip data input means, said chip Data input means and LSI package Assembly checking means _for checking whether or not assembly conditions in the work of assembling the chip and the LSI package input by the data input means are satisfied, and the LSI input by the LSI package data input means
The initial wire generating means for automatically combining the chip pads on the LSI chip input by the chip data inputting means with all the internal leads to be connected to the chip pads of the package, _and the initial wire generating means for combination. The assembly condition check of the chip pad and the internal lead is performed by using the assembly check means. If the assembly condition is not satisfied, the combination of the chip pad and the internal lead is automatically changed, and the LSI input by the LSI package data input means is input. for all inner leads to be connected to the package of the chip pads, LSI design support system characterized by comprising _a wire adjusting means for the combination of the assemblable chip pads. 2. The initial wire generating means calculates an internal lead direction, which is the direction of the internal lead of the LSI package input by the LSI package data input means, and inputs by the chip data input means in the internal lead direction. The LSI design support system according to claim 1, wherein the LSI design support system is combined with the closest chip pad on the LSI chip. 3. The wire adjusting means pays attention to one combination in order from the chip pad and the internal lead combined by the wire adjusting means, and checks the assembly condition of the internal lead by using the assembly checking means. And then
If you did not meet the assembled condition, characterized in that _intends sequentially repeated rows for all internal leads that they would change the combination of the next chip pads of the chip pads are combined with internal leads of interest The LSI design support system according to claim 1.