JPH05174099A - Editor for wiring layout design - Google Patents

Abstract

PURPOSE:To prevent the generation of an error on a rule. CONSTITUTION:The editor is constituted by providing a graphic data storage means for storing existing graphic data, a data input means 7 for inputting layout data of a wiring in accordance with a graphic of the existing graphic data, a temporary storage means 2 for storing temporarily the layout data of the wiring inputted newly, a rule data output means for outputting rule data in which a reference rule for verifying the layout data of the wiring is stored, a layout verifying means 5 for verifying through the reference rule the consistency of the layout data of the wiring stored in the temporary storage means 2 and the existing graphic data, and a data integrating means 6 for integrating the layout of the wiring stored in the temporary storage means 2 into the existing graphic data in accordance with a result of verification.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an editor for wiring layout design, and more particularly, the editor for wiring layout design includes a package pin lead (hereinafter referred to as a lead) on a package side of a semiconductor integrated circuit and a chip. Suitable as a wiring editor for bonding wires between side pads.

Generally, a wiring editor is used in the layout design of a bonding wire that connects between a package-side lead and a chip-side pad in a semiconductor integrated circuit. When designing the layout of bonding wires, the number of bonding wires is extremely small compared to the pattern wiring inside the chip, the wiring is laid out in a straight line, and the custom product reflects the complex intention of human beings. Or, since it is necessary to reflect an ambiguous intention including human tastes, it is difficult to automate the layout. Therefore, the manual operation is performed via the editor in this way.

[0003]

2. Description of the Related Art Conventionally, the layout of bonding wires in a wiring editor is performed in the order shown in FIGS. First, in FIG. 3A, the pads 22 are arranged in a row inside the chip adjacent to the chip boundary side 21, and the leads 23 on the package side are similarly arranged outside the chip. It is shown.

In FIG. 7, the leads 23 and 23K and the pads 22 and 22K are 23K and 22K for the power source VDD and VSS with an asterisk indicating the connection target point, and other signals (SIG). 23) and 23), each of the leads and pads for signals is marked with a white circle at a wiring candidate point for which wiring is to be laid out, and a black circle is shown at a wiring fixed point where wiring layout has already been performed. It is marked.

The leads and pads having the same purpose as each other are required to be connected by a linear wiring without crossing other wirings. The wiring is extremely fine, and its length is, for example, about 2 to 3 mm.

Following the layout of the wiring 24 which has already been determined in FIG. 7A, first, the lead 23K with an asterisk forming the connection target point is selected as one end point,
When this is confirmed, it becomes a black circle, and then the pad 22K similarly marked with a star is selected as the other end point ((b) in the same figure), and as soon as this end point is confirmed, a straight line connecting both end points The wiring 24K is laid out, and the layout of this wiring is fixed as it is ((C) in the same figure). In this way, the bonding wires connecting all the leads and the pads are sequentially laid out.

The layout design data of the bonding wire whose layout has been completed by the wiring editor is then sent to the computer, and the computer verifies the validity of the layout design through the automatic verification program. The automatic verification program includes physical verification (DRC: design
Rule check) and electrical verification (ERC: electrical rule check).

In the DRC and ERC, for example, the limitation of the length of the wiring and the distance between the wirings are kept as predetermined, whether the wirings cross each other, the division of leads and pads for power supply and signals, and Even for power supplies, it is checked whether the potential of the power supply is designed correctly and its accuracy is verified.

[0009]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention As shown in FIG.
Power supply VDD lead 23K and power supply VSS pad 22K
When and are mistakenly connected, those having different power supply potentials are connected to each other, and when the bonding wire 24K intersects the side of the lead 23K,
The distance between the bonding wire 23K and the lead 23L adjacent to the side of the lead 23K becomes insufficient, and when the bonding wires 24 and 24K cross each other, both are short-circuited. Even in such a case, since the presence of an electrical or physical error is pointed out in the automatic verification, the designer restarts the wiring editor and corrects the error pointed out in the automatic verification.

Generally, in the layout design of wiring such as bonding wire, the modification of one wiring on the layout is accompanied by the modification of another wiring including the adjacent wiring. In this case, the influence is exerted on the adjacent wiring. It will be propagated one after another, and the total amount of corrected wiring will be enormous.
Further, in the data obtained by correcting a part of the layout that has been finished, an error often occurs at another place. Therefore, in the conventional bonding wire layout design, the layout design, the DRC process and the ERC process are likely to be repeated many times, which causes a problem in the process and a large number of man-hours.

In view of the above problems in the conventional wiring editor for the wiring layout design, the present invention is to perform online D editing during the wiring editing before the wiring layout is completed.
As a result of performing the RC and ERC checks, some modifications of the wiring are completed without many other modifications, and each modification is completed, so that the man-hours for layout design can be kept small and the process can be reduced. The purpose of the present invention is to provide an editor for wiring layout design in which problems hardly occur.

[0012]

FIG. 1 shows the principle of the present invention. In the figure, 1 is wiring data input means, 2 is data temporary storage means, 3 is layout data storage means, 4
Is a rule data input means, 5 is a layout verification means, 6
Is a data embedding unit, 7 is a design data input unit, 8 is a layout data output unit, and a, b, c and d are newly input wiring data, existing design data, rule data and a layout which has already been decided. The data.

In order to achieve the above-mentioned object, the editor for wiring layout design of the present invention, as shown in FIG. 1, is a design data inputting means for inputting existing design data (b) including at least graphic data ( 7), a layout data storage means (3) for storing the already decided layout data (d) including at least the existing design data (b), and the information of the already decided layout data (d). Wiring data input means (1) for inputting wiring data (a), and wiring data (a) newly input by the wiring data input means (1).
And a rule data input means (4) for inputting rule data (c) in which a reference rule for verifying the wiring data (a) is input, Layout verification means (5) for verifying the consistency between the wiring data (a) stored in the data temporary storage means (2) and the already determined layout data (d) via the reference rule (c). ), The wiring data (a) stored in the data temporary storage means (2) is stored in the layout data storage means and has already been confirmed. The wiring data embedding means (6) for incorporating the layout data (d) into the newly established layout data and outputting the already determined layout data (d). It is characterized in further comprising a layout data outputting means.

[0014]

The wiring data newly input by the wiring data input means is temporarily stored in the data temporary storage means, and the wiring data stored in the data temporary storage means and the layout data stored in the layout data storage means have already been determined. The layout data is verified by the layout verification means incorporated as part of the editor function that receives the rule data from the rule data storage means each time the wiring data is created through the standard rule, and it is determined that there is consistency as a result of this verification. Only when the newly input wiring data is incorporated into the layout data that has already been determined through the data embedding means and becomes the newly determined layout data, a new rule data is violated. For the wiring data input to, the layout data is Since the integration is eliminated, and the layout data of the wiring obtained through the layout data output means, and thus does not include the data of the wiring having the error that violate the standard rules.

In the verification, the verification target is limited to newly input wiring data. Therefore, the verification process can be performed incrementally by repeating the wiring and verification little by little. Therefore, according to the wiring editor according to the present invention, the verification CPU time can be minimized and the verification time can be saved.

[0016]

The present invention will be further described with reference to the drawings. Figure 2
FIG. 3 is a block diagram showing a device configuration of an editor for designing a wiring layout according to an embodiment of the present invention. In the figure, this editor inputs wiring data for the layout of bonding wires via the mouse 17 in the figure in accordance with the existing design data including the figure displayed on the display 14.

The newly input wiring data is temporarily stored in the data temporary storage means. When confirming newly input wiring data, D
The RC and ERC function parts are activated online, and the newly input wiring data and layout data (leads, lead bonding points, pads, chip frames, various text information (bonding point number, potential information, Bonding information, etc.), existing wiring data (when modifying or adding wiring data before starting the editor this time) and wiring data that has already been fixed, and if there is already fixed wiring data, and , It is verified that there is no rule error between the newly input wiring data via the reference rule.

The existing design data including the graphic data and the rule data having the standard rule are stored in the data disk 19 outside the editor before the wiring editor is started, and each input means is started through the start of the wiring editor. Is read by the MPU 11 and stored in the main storage device 12. Also, the wiring data newly input from the mouse 17 is confirmed only when the layout verification is performed by the MPU 11 via the rule data and the consistency is verified, and the wiring data is incorporated into the existing design data. The layout data has already been decided. The wiring data that is sequentially input is incorporated into the already determined layout data through verification each time.

At the time of this verification, the target of the consistency verification is limited to the wiring data for which the layout has been newly input, and the verification CPU time is the minimum necessary time, thus saving the verification CPU time. ing.

The detailed prescribed numerical value in each standard rule of the rule data is stored in the auxiliary disk 13 or the external disk 19 as a separate file from the rule data, and this numerical value is read at the time of wiring verification. , Combined with the reference rules stored in the main memory 12,
It is used for layout verification of newly input wiring.

Further, the verification process can be performed incrementally by repeating the wiring, verification, and incorporation into the already determined layout data little by little.

FIG. 3 is a process flow chart for determining the layout of each bonding wire in the editor of FIG. 2, and FIGS. 4 to 6 are examples of screen displays displayed on the display when determining the layout. .. 4 corresponds to the process flow diagram shown by the solid line in FIG. 3, and FIGS. 5 and 6 correspond to the process flow diagram shown by the solid line and the broken line.
FIG. 3 will be described below with reference to FIGS. 4 to 6.

In the processing flow diagram of the solid line in FIG. 3 showing the processing in the editor of the first embodiment, in this editor,
If the end points of one and the other wiring are temporarily determined (P1, P
2) The layout data of the wiring that connects both end points is temporarily stored, and the undetermined wiring is drawn by, for example, a broken line on the screen (FIG. 4B). Immediately thereafter, the DRC and ERC function parts incorporated in the editor program are activated online to activate the design and electrical rule verification function (P3), and the temporarily stored wiring data includes the already determined layout including the graphic data. Collated with the data.

As described above, when the wiring connecting both end points is determined, it is checked whether or not the wiring causes a physical or electrical error with the determined layout data (P4). If it is determined that no error occurs as a result of the check, the temporarily stored wiring is internally determined (P5), and the line connecting both end points changes to a solid line on the display. Further, when it is confirmed that there is an error, the line connecting both end points is internally deleted and the display is also deleted or changed to another color or the like (P6).

As shown in FIGS. 4A to 4C, in the case of wiring including an error such as connecting the power supply VDD lead 23K and the power supply VSS pad 22K, it is determined that there is an error as a result of verification. Since it is determined, the temporary storage is canceled without being incorporated in the decided layout data, the broken line disappears, and the initial state is restored or another broken line is displayed. For this reason, the input person can investigate the correct end point again and perform the correct input.

The method of designating the electrical attribute (wiring use) of each lead and pad on the data is as follows. For each lead, the lead number of the lead is shown in the lead. For example, a lead number is attached to the bonding position in each lead. Also, the leads for the respective power supply lines VDD and VSS are
In the text file, the lead numbers for each power source are described and stored as a list of power source lead numbers. Therefore, at the time of verification, this text file is read and referred to from the lead number, and is used for recognizing the electrical attribute (wiring purpose) of each lead. Leads with lead numbers not present in these lists are determined to be for signals.

For each pad, the use and pad number of the pad are shown in the pad. For example, at the bonding position in each pad, # PW1, #GND, and #S
Reference numerals such as IG are attached to the pads, which mean the pads for the power supply VDD, the power supply VSS, and the signal, respectively, and the pad numbers of the pads are added to these pads.

In the wiring editor of the second embodiment, as shown by the solid line and the broken line in FIG. 3, layout verification is performed collectively for a plurality of wirings. This state is shown in the plan views of FIGS. In the wiring layout of this bonding wire in FIG. 5, seven bonding wires 24A to 24G are sequentially designated while temporarily stored and the layout verification of these seven wires is performed simultaneously. Since these are temporary wirings, they are shown by broken lines unlike the wirings in the already determined layout data.

As shown in FIG. 5, of the seven bonding wires 24A to 24G, 24A connects a lead 23A forming a signal line labeled SIG to a power supply pad 22A labeled VDD. The bonding wire 24C has a small incident angle α with the chip side of the wire, the wire length L is longer than the reference, and the wire is the tip side of the lead 23C. It has been specified that it has a physical error of not intersecting with but intersecting with its side.

In addition, bonding wires 24E and 24
D is a designation that has a physical error that wires are crossing each other, and bonding wire 24G is lead 2
The designation is made with an electrical error that the power supply potentials of both 3G and the pad 22G are different.

The input bonding wire 24A
When layout verification is performed on the entire ~ 24G, FIG.
As shown in FIG. 5, the wiring designation having an error is displayed by deleting the color of the broken line and indicating that there is an error, or deleted. Further, the wiring having no error is changed to a color of the fixed wiring which is different from the previous color and is the same as the existing design data. It should be noted that only one of the bonding wires 24D and 24E is fixed, and the other 24E is eliminated as an error display.

As described above, in the second embodiment, a plurality of wirings are verified at the same time. However, all newly input wirings have not yet been confirmed and the verification result is not good. In this case, it is not automatically excluded and incorporated into the decided layout data. Therefore, even if an error occurrence is detected, it is not necessary to correct the determined layout data, and the layout, DRC and ER
It is possible to prevent the situation where the process C is repeated.

In the above, when the DRC and ERC are activated, the DRC and ERC are automatically set every time one wire is wired.
There are two types of modes, one is a mode in which the editor is activated and the other in which the editor operator explicitly activates the DRC and ERC after wiring several lines. The two types of modes are provided at the start of the wiring or during the wiring. The operator can select it at any time.

Therefore, in the former mode, the DRC
Since the activation of the ERC and the ERC is performed regardless of the intention of the editor operator at the time of input for confirming the layout of one to several wires, the editor operator does not need to be aware of these activations. Further, in the latter mode, when the editor is terminated, if the wiring which is not verified remains, the lock is applied so that the editor cannot be terminated. Instead of this, a method of automatically activating the verification function at the end of editing can also be adopted.

Therefore, regardless of which of the above two modes is selected, inadvertent verification will not occur.

Further, it is possible to forcibly confirm the wiring determined as an error as a result of either verification without excluding it, and to reflect the special intention of the editor user.

Although the layout of the bonding wire between the lead of the package pin and the pad of the chip has been described in the above embodiment, the editor according to the present invention is
The layout is not necessarily limited to the bonding wire only, and may be adopted, for example, for partial correction of wiring layout data performed by automatic wiring.

Further, in order to distinguish between the undetermined wiring, the wiring to be excluded by the verification, and the fixed wiring in the fixed layout data, in addition to the line type, for example, color or blinking is used. However, the wirings to be eliminated can be temporarily put in a suspended state after verification, and the suspended state can be released when the next lead or pad is subsequently designated.

[0039]

As described above, according to the editor for wiring layout design of the present invention, the wiring newly input by the editor has the rule data consisting of the reference rule with the fixed layout data. The layout data obtained in the layout design is highly reliable because it is incorporated into the layout data that is first determined when it is checked via the There is no fear of affecting the definite wiring in the data, the design process can be easily protected, and the remarkable reduction in the number of design steps can be achieved.

Further, it is possible to forcibly determine the wiring determined as an error as a result of the verification without excluding it,
By reflecting the special intention of the editor user, it is possible to deal with special exceptions (data).

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block diagram showing a device configuration of an editor for wiring layout design according to an embodiment of the present invention.

FIG. 3 is a process flow chart in the editor of FIG.

4A to 4C are partial plan views of a semiconductor integrated circuit for sequentially explaining the operation of the first embodiment, where FIG. 4A is before layout input and FIG. After layout, (c) is after layout verification.

FIG. 5 is a plan view of a semiconductor integrated circuit before verification, that is, before confirmation of an input, which is an operation explanatory view in the second embodiment.

FIG. 6 is a plan view of the semiconductor integrated circuit after verification, that is, immediately after the input is confirmed, which is an explanatory view of the operation in the second embodiment.

7A to 7C are plan views of a semiconductor integrated circuit for explaining the operation in a conventional editor. FIG. 7A is before layout input, FIG. 7B is during layout input, and FIG. After input.

[Explanation of symbols]

 1: Wiring data input means 2: Data temporary storage means 3: Layout data storage means 4: Rule data input means 5: Layout verification means 6: Data incorporation means 7: Design data input means 8: Layout data output means a: New Input wiring data b: Existing design data c: Rule data d: Layout data already determined 21: Chip boundary side (chip frame) 22, 22A, 22C, 22K: Pads 23, 23A, 23C, 23K: Read 24, 24A to 24G: Bonding wire

Claims (7)

[Claims] 1. Design data input means (7) for inputting existing design data (b) including at least graphic data, and already-established layout data (d) including at least the existing design data (b). Layout data storage means (3) for storing; wiring data input means (1) for inputting wiring data (a) in accordance with the information of the already determined layout data (d); and the wiring data input means Data temporary storage means (2) for temporarily storing the wiring data (a) newly input by (1), and rule data (c) in which a reference rule for verifying the wiring data (a) is stored. ) For inputting the rule data, the wiring data (a) stored in the data temporary storage means (2), and the already determined layout data. a layout verification means (5) for verifying the consistency with the d) via the reference rule (c); and a data temporary storage means (2) when it is judged that there is consistency as a result of the verification. The wiring data (a) thus created is incorporated into the already-established layout data (d) stored in the layout-data storage means to newly create the already-established layout data (d).
An editor for wiring layout design, comprising: wiring data embedding means (6), and layout data output means (8) for outputting the already determined layout data (d). 2. The editor for wiring layout design according to claim 1, which is an editor for layout design of bonding wires of a semiconductor integrated circuit. 3. The newly input wiring data includes data relating to two or more wirings, and the consistency between the wirings is verified through the reference rule. An editor for the wiring layout design described in 2. 4. The editor for wiring layout design according to claim 1, wherein the layout verification means (5) can be activated online while the editor is activated. 5. The layout verifying means (5) automatically inputs each wiring of the wiring data, automatically after all the wiring data is input, or each time a plurality of wirings of the wiring data are input. The editor for wiring layout design according to claim 1, wherein the editor can be selectively activated via an external signal. 6. The data temporary storage means (2) further receives new wiring data prior to the incorporation of the wiring data already verified by the layout verification means (5), and the layout verification means ( 5. The wiring layout design according to claim 1, wherein 5) performs the verification of the consistency with respect to the newly input wiring data excluding the already verified wiring data. Editor of. 7. The data embedding means (6) does not embed or forcibly embeds the wiring determined to be an error as a result of the verification in the wiring data, into the already determined layout data. 7. The editor for wiring layout design according to claim 1, wherein it is possible to select whether or not to perform.