JPH0417071A - Lsi design supporting system - Google Patents

Abstract

PURPOSE:To make wire connection which is not in contravention of rules regarding adjacent wires and lead pins by indicating an area which is in contravention of a rule established between lead pins and their adjacent wires before performing a wire connecting process and another area which is in contravention of a rule established between each adjacent pins whenever wire connecting work is performed. CONSTITUTION:A wire-lead interval contravening area detecting section 7 which indicates an area which is in contravention of a rule established between adjacent wires and lead pins at the front end section of each lead pin in frame data is provided in an LSI design supporting system provided with a chip designing section 1, frame designing section 2, data synthesizing section 3, wire connecting diagram preparing section 4, etc. In addition, a wire-to-wire interval contravening area detecting section 8 which indicates an area which is in contravention of a rule established between connected adjacent wires is also provided. Therefore, such wire connection that is not in contravention of the interval rule between adjacent wires and lead pins can be made and the occurrence of error and number of modifying works can be reduced at the time of checking rules. As a result, an improvement in designing efficiency and reduction in designing period can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an LSI design support system for creating a chip-frame connection diagram of an IC chip.

[Conventional technology]

FIG. 3 is a block diagram of a conventional IC chip chip-frame connection diagram creation system. In the figure, (11
(2) is a chip design department that interactively designs the layout of an IC chip; (2) is a chip design department that interactively designs the layout of an IC chip; The frame design section (3) interactively designs the frame that becomes the external terminal of the C chip, which takes in chip drawing data and frame drawing data from the chip design section (1) and the frame design section (2) and writes it onto the frame drawing data. (4) is a data synthesis unit that arranges the chip drawing data at the ideal position; (4) is a wiring diagram creation unit that makes connections between the IC chip and the frame in the composite drawing data created by the data synthesis unit (3); (5) (6) is a rule checking unit that checks whether the wiring diagram between the chip and the frame created by the wiring diagram creation unit (4) satisfies the wiring rules, and (6) is an error in the rule checking unit (5). This is a completed wiring diagram storage unit that stores the chip-to-frame wiring diagram that has not been generated.

FIG. 4 shows the composite drawing data created by the data composition section (3). In the figure, (9) is chip drawing data input from the chip design section (1), and α0) is frame drawing data input from the frame design section (2).

Next, the operation will be explained. The chip design unit (11) and frame design unit (2) interactively design IC chips and frames, respectively.Then, the data synthesis unit (3)
The designed chip drawing data and frame drawing data are taken in, and composite drawing data is created in which the chip drawing data is arranged at the ideal chip position on the frame drawing data. In this composite drawing data, the wiring diagram creating section (4) automatically or interactively connects the chips and frames to create a chip-frame wiring diagram. Next, when the created chip-frame wiring diagram is actually connected during the manufacturing process, a rule check is made to see if it satisfies the established wiring rules in order to prevent wire breakage and contact between wires. Check in part (5). The chip-to-frame wiring diagrams that pass this wiring rule check are stored in the completed wiring diagram storage section (5), but the chip-to-frame wiring diagrams that fail are revised again in the wiring diagram creation section (4). and the rule check section (5) performs a check.

[Invention or problem to be solved]

Conventional LSI design support systems that create chip-frame connection diagrams are configured as described above, so whether or not the connected wires meet the established rules with adjacent wires and lead pins is The decision was made by checking the wires after connecting all the wires together with other rules regarding connections. Therefore, the wires are connected without considering the rules regarding adjacent wires and lead pins, and if a rule error occurs, it is necessary to make corrections such as moving the wire, or take the rules regarding adjacent wires and lead pins into account. Because of this, there is a possibility that an error may occur again, and the rule checking and correction work is extremely inefficient.

This invention was made in order to solve the above-mentioned problems, and it is possible to specify areas that violate the rules established between lead pins and adjacent wires before performing wire connection processing, and to
To obtain an LSI design support system that allows wire connections that do not violate rules regarding adjacent wires and lead pins by indicating areas that violate rules established between wires and adjacent wires each time a wire is connected. purpose.

[Means to solve the problem]

The LSI design support system according to the present invention includes a wire that indicates an area that violates a rule defined between adjacent wires and lead pins at the tip of each lead pin in frame data.
It is equipped with a lead spacing violation area detection section and a wire-to-wire spacing violation area detection section that indicates an area of the connected wire that violates a rule defined between adjacent wires.

[For production]

The wire-to-lead interval violation area detection unit and the wire-to-wire interval violation area detection unit in the present invention indicate a prohibited area for adjacent wires to pass on the chip-frame connection diagram during the connection operation.

[Embodiment] Hereinafter, one embodiment of the present invention will be described with reference to the drawings. 1st
In the figure, (1) is the chip design section that interactively designs the layout of the IC chip, (2) is the frame design section that interactively designs the frame that will become the external terminal of the IC chip, and (3) is the chip design section. Department (1) and Frame Design Department (2)
(4) is a data synthesis unit that takes in chip drawing data and frame drawing data from and arranges the chip drawing data at an ideal position on the frame drawing data;
a wiring diagram creation unit that automatically or interactively connects the IC chip and the frame in the composite drawing data created in 3);
(5) is a rule checking unit that checks whether the wiring diagram between the chip and the frame created by the wiring diagram creation unit (4) satisfies the wiring rules; (6) is the rule checking unit (5) ) is a completed wiring diagram storage section that stores the chip-to-frame wiring diagram that has passed the test. The lid pin spacing violation area detection unit (8) is a wire-to-wire spacing violation area detection unit that indicates on the drawing during the connection work a gap violation area for adjacent wires of connected wires.

FIG. 2 is a wiring diagram between a chip and a frame during wiring processing in which a spacing violation area is specified by the wire/lead pin spacing violation area detection unit (7) and the wire/wire spacing violation area detection unit (8) in FIG. 1. It is an enlarged view of. In the figure, (9) shows the chip drawing data input from the chip design department (1), α0) shows the frame drawing data input from the frame design department (2), and (11) shows the connection route between the IC chip and the frame. Connection wire, (1 is a wire/lead pin spacing violation area indicated by the wire/lead pin spacing violation area detection unit (7), 0 is a wire/wire spacing violation indicated by the wire/wire spacing violation area detection unit (8) It is an area.

Next, the operation will be explained. A chip design section (1) and a frame design section (2) interactively design IC chips and frames, respectively. Thereafter, the designed chip drawing data and frame drawing data are taken from the respective design sections into the data synthesis section (3), and the chip drawing pigs are arranged at ideal positions on the frame data. On this composite drawing data, a wire/lead interval violation area detection unit (7)
Then, at the tip of each lead pin in the frame data, an area that violates the rule defined between the adjacent wire take-off and the do-pin is indicated. In the wiring drawing creation section (4), the IC is
Connections are made between the chip and the frame, but each time a wire is connected, the wire-wire spacing violation area detection unit (8) creates an area that violates the rules set between adjacent wires of that wire. Indicate on the chip-frame connection drawing you are working on. In this way, after all the wires to be connected are connected, the rule checking section (5) ensures that the rules established to prevent wire breakage and contact between wires are satisfied when the wires are connected in the actual manufacturing process. The chip-to-frame connection diagrams that pass the test are stored in the completed connection diagram storage section (6). In addition, the failed chip-frame connection diagram is corrected again by the connection diagram creation section (4) and checked by the rule check section (5).

〔Effect of the invention〕

As described above, according to the present invention, the spacing violation area and the spacing violation area associated with the connected wire are indicated at the tip of each lead pin before wire connection. It is possible to connect wires without infringing on the area where the interval of the LEET pin is violated, and the number of errors and correction operations during rule checking is greatly reduced, which improves design efficiency and has the effect of shortening the design period.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an LSI design support system showing an embodiment of the present invention, and FIG. 2 is a diagram showing a gap between chip frames during wiring process, indicating areas where the distance between wires and lead pins with respect to adjacent wires in FIG. 1 is violated. Enlarged diagram of wiring diagram,
Figure 3 shows the L diagram for creating a conventional chip-frame connection diagram.
FIG. 4, a block diagram of the SI design support system, is a diagram showing a composite drawing pig that combines a chip drawing pig and frame drawing data. In the figure, (1) is the chip design department, (2) is the frame design department, (3) is the data synthesis department, (4) is the wiring diagram creation department, (5) is the rule check department, and (6) is the completed connection. Figure storage section, (7) is wire/lead pin interval violation area detection section,
(8) is a wire-wire interval violation area detection unit, (9) is chip drawing data, 00 is frame drawing data, (1
υ is a connection wire, (12 is a wire-to-lead spacing violation area, and (13 is a wire-to-wire spacing violation area.

Claims (1)

[Claims] A chip design department that interactively designs IC chips, and an IC
a frame design unit that interactively designs a frame to be an external terminal of the chip; and a data synthesis unit that arranges chip data input from the chip design unit at an ideal position on the frame data input from the frame design unit. , a wiring diagram creation unit that automatically or interactively creates a wiring diagram that describes wires that indicate the connection route between the chip and the frame in the composite drawing data created by the data synthesis unit, and a created chip-frame wiring diagram. There is a rule check section that checks whether or not the wiring rules established to prevent wire breakage and contact between wires are met during the actual manufacturing process, and chips that pass the rule check section.
It consists of a complete wiring diagram storage section that stores inter-frame wiring diagrams, and in the composite drawing data created by the data composition section, an area that violates the rules defined between the adjacent wire and lead pin at the tip of each lead pin of the frame data. An LSI design characterized by comprising a wire/lead spacing violation area detection unit that points to an area where a rule defined between adjacent wires is violated in a connected wire, and a wire/wire spacing violation area detection unit that points out an area that violates a rule defined between adjacent wires in connected wires. support system.